JP2003131888A - Method of scheduling instruction between procedures - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce pipeline installation at the time of executing an instruction extending to other procedures. SOLUTION: Compile processing for data flow information collection between procedures is performed or data flow information between procedures is generated from saving restoration rules of registers at the time of calling a function in advance, and instructions are scheduled by using the information, so that pipeline installation extending to other procedures is reduced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a compiler,
The present invention relates to a compiler that performs instruction scheduling in consideration of dependency across procedures and resource competition.

[0002]

2. Description of the Related Art For compilers such as FORTRAN and C language, for instructions in a function, resources in a microprocessor (hereinafter simply called resources) necessary for executing instructions such as an arithmetic unit and a memory access unit used by each instruction. ), Or when there is a dependency between instructions such that the result of the previous instruction is used by the latter instruction, the time required for the previous instruction to output the result
There is a technique called instruction scheduling that reduces the occurrence of pipeline stalls by rearranging instructions in consideration of (hereinafter, referred to as latency). This is P
hillip B. Gibbons, Steven S. Muchnick "Efficient I
nstruction Scheduling for a Pipelined Architectur
e "Procedings of the SIGPLAN symposiumon compiler
1896, pp.11-16.

[0003]

Instruction scheduling is usually a minimum instruction sequence that does not include a branch, only for instructions in a basic block, or when instruction scheduling is performed over a plurality of basic blocks. However, in all cases, scheduling is performed in consideration of resource contention and latency due to inter-instruction dependency for instructions in a function, and resource contention and latency across functions are not considered.

[0004]

In order to solve the above problems, according to the present invention, when performing instruction scheduling, the program is scanned to check the inter-procedure instruction dependency and the resources used by each instruction, The high-speed operation of the microprocessor becomes possible by scheduling the inter-instruction sequence so that pipeline stall installation due to inter-instruction interdependence and resource competition does not occur.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a computer system provisionally mounted by a compiler according to the present invention. As shown in the figure, the computer system comprises a CPU 101, a display device 102, a keyboard 103, a main storage device 104, and an external storage device 107. The main memory 104 holds a compiler 105 and an intermediate code 106 required in the compilation process. The external storage device 107 holds a source program 108 and an object program 109. The compilation processing is performed by the CPU 101 executing the compiler 104. The user gives a command to the compiler 104 from the keyboard 103, and the display device 102 notifies the user of the end of compilation or an error.

FIG. 2 shows a procedure for performing interprocedural scheduling using the compiler to which the present invention is applied. Source program consisting of multiple files
The data flow information collection process is performed on 108 in step 201 to obtain data flow information 202. Details of the data flow information will be described later with reference to FIG. Next, in step 203, the previously acquired data flow information 2
02 and the source program 108 are compiled to obtain the optimized object code 109.

FIG. 3 is a flow chart showing the flow of the compiling process according to the present invention. The compiler process is
First, in step 201 parsing, source program 1
08 is read and the intermediate code 106 that can be processed in the compiler is generated. The parsing process is described in, for example, "Compiler I" by Aho, Cessie, and Ullman: Compiler I (Science, 1990), pp. 30-74, and will not be described here. Next, in step 302, data flow analysis processing is performed for each function included in the source program 108. The data flow analysis processing is also described in "Compiler II, Aho, Cesi, Ullman: Science II" (Science Co., 1990), pages 741 to 772, and will not be described here. Then go to step 303,
The interprocedural dataflow information 202 necessary for scheduling the function currently being compiled is executed by performing interprocedural dataflow information input processing, which is one of the characteristic processes of the present invention.
From the file. Then go to step 304,
Interprocedural instruction scheduling processing, which is one of the characteristic processing of the present invention, is performed. Step 203 will be described in detail with reference to FIG. Next, in step 305, interprocedural dataflow information output processing, which is one of the characteristic processes of the present invention, is performed, and interprocedural dataflow information 202 of the function currently being compiled is output to a file. Next, in step 204, the object code is generated, the object code is generated, and the processing is terminated. Regarding the object generation processing 204, similarly, "Aho, Cecie, Ullman: Compiler II" (Science, 1990) pages 624-7
Since it is described on page 07, it will not be described in detail here.

FIG. 4 is a detailed diagram of the interprocedural data flow information. Data flow information is in register number field 40
1, reference type field 402, field for the number of cycles from the start of the referenced instruction to the end of the function
403 and an intermediate language field 404 to which the reference is made. These pieces of information are obtained from the schedule table described in FIG. If there is a branch in the function and there are multiple references that can be the first reference of a register or the last reference, for the first reference, only the reference that starts at the earliest timing, the last definition, Regarding references, only the definition or reference that requires the shortest number of cycles from the start of the referenced instruction to the end of the function shall be recorded.

FIG. 5 is a detailed diagram of an interprocedural instruction scheduling process, which is a characteristic process of the present invention. First,
In step 501, a directed acyclic graph (dag), which is a directed acyclic graph showing the dependency relationship of each instruction, is generated. Regarding the method of generating dag, "Aho, Cesi, Ullman: Compiler II" (Science, 1990) 665
Since it is described on pages 674 to 674, it is not explained here. Next, in step 502, based on the dag information,
Perform instruction scheduling. The instruction scheduling procedure is described in "Ikuo Nakata: Compiler Construction and Optimization" (Asakura Shoten, 1999), pages 358 to 382, and will not be described here. The interprocedural instruction scheduling, which is a feature of the present invention, is realized by generating the dag using the information of the interprocedural data flow information 202. For how to use the information,
This will be described with reference to FIG.

FIG. 6 is an example of a program for performing interprocedural scheduling. The function foo defined in steps 603 to 606 is replaced with the function func declared in steps 608 to 612.
However, the structure is called in step 610.

FIG. 7 shows an example in which the program shown in FIG. 6 is represented by an intermediate language for performing scheduling.

FIG. 8 shows the function foo among the intermediate words of FIG.
Which is the dag generated from steps 701 to 704. Each node of dag corresponds to the instruction of the program. In the figure, 1001 to 1006 are da corresponding to steps 701 to 704.
It is a g node. Further, between the dag nodes, edges having a dependency relationship are provided from the dependency source to the dependency destination. The numerical value described next to the edge is the number of cycles required between the instruction having the dependency and the instruction having the dependency, between the instructions having the dependency relationship. Here, the following assumption is made as a computer to be scheduled. (1) One integer operation and one memory operation instruction can be issued at the same time. (2) Integer operation instructions are in the form of d = ADD s1, s2 (register operation of d = s1 + s2, s2 can be a constant) and are completed in 2 cycles. (3) The memory operation instruction is d = LOAD addr (load from address addr to register d) or STORE addr = s (register s
To the addr address), the LOAD instruction completes in 3 cycles and the STORE instruction completes in 1 cycle. (4) When processing is performed in the order of LOAD and STORE from the same register, STORE can be started 5 cycles after the start of LOAD.

Hereinafter, it is assumed that the computers to be scheduled are computers of the same assumption.

FIG. 9 is a block diagram of the computer of FIG.
It is a schedule table that is the result of scheduling from dag. From this schedule table, the inter-procedural data flow information described in FIG. 4 can be obtained. For example, since it is known that the first definition of r1 is the load instruction of cycle 901, the interprocedural data flow information entry 40
You can get information of 5. Similarly, since the last definition of r1 is found to be the add instruction of cycle 904, the information of entry 406 is obtained, and the last reference of r1 is found to be the store instruction of cycle 906, so entry 4
07 information is obtained.

From the above description, the function foo of the program of FIG. 6 is compiled in the step 201 data flow information collection compilation processing, and instruction scheduling is performed to obtain the schedule table of FIG.
Of obtaining inter-procedural data flow information.

Next, a method of performing interprocedural instruction scheduling using the data flow information 202 will be described.

FIG. 10 is a dag of the function func generated from the intermediate language of steps 705 to 715 of FIG. 7 using the interprocedural data flow information of FIG. Normally, the number of cycles required from a call to a dependent instruction is da
Although g is generated, the interprocedural instruction scheduling method of the present invention uses information of interprocedural data flow information. Since the load instruction of the node 1002 writes to r1, this instruction can be started 5 cycles after the start of the store instruction of cycle 906 in FIG. Five cycles after the store instruction in cycle 906 starts, cycle 907
Since there is a return instruction of, in dag of FIG. 10,
5-1 = 4 cycles after the call instruction 1001. This is obtained from the field of the number of cycles in the entry 407 of the interprocedural data flow information in FIG. 4 which is the total number of cycles of the function minus the number of cycles in which the reference is executed.

FIG. 11 is a schedule table as a result of scheduling the function func from dag in FIG.

FIG. 12 is a simulation result of the number of cycles required when the scheduling results of FIGS. 9 and 11 are actually executed. Function according to the schedule
func is executed in 10 cycles.

As an example of the conventional method, FIG. 13 is a dag when it is assumed that three cycles are required between a call instruction and an instruction having a dependency without using interprocedural data flow information. Unlike FIG. 10, it is assumed that the number of cycles between the nodes 1301-1302 is three.

FIG. 14 is a schedule table as a result of executing the instruction schedule by the dag of FIG. cycle
The commands 1404 and 1405 are the reverse of those in FIG.

FIG. 15 is a simulation result of the number of cycles required when the schedule results of FIGS. 9 and 14 are actually executed. Store instruction in cycle 1507 and 1512
Since 5 cycles are required between the load instructions of, the waiting time of 1 cycle is included,
It takes a lot of cycles.

In the above embodiment, interprocedural data flow information
The data flow information collection compilation process 201 is required to generate 202, but in the present invention, by preparing simple data flow information in advance, the accuracy may be slightly lowered, but the data flow information between procedures Can be used for instruction scheduling. For example
With regard to the save and restore code of the callee save register, which register save and restore code is generated at the beginning and end of the program can be predicted fairly accurately by the register save and restore rules at the time of a call. There are cases. At this time, the inter-procedural data flow information, which is assumed based on the information, is created in advance, so that the data flow information collecting compilation process 201 can be omitted.

FIG. 16 shows an example of the save / restore code of the callee save register. Here, r6 to r8 are callee sav
used in a function, assuming it is an e-register
The callee save register is saved on the stack starting from the one with the smallest register number at the beginning of the function (steps 1604-1
606), it is assumed that it is decided at the end of the function that the register with the largest register number is restored to the register from the stack (steps 1601 to 1603). Although not shown in the figure, it is assumed that r6 to r8 are used in the program and the contents are changed.

FIG. 17 shows interprocedural data flow information when the save / recover code shown in FIG. 16 is generated.
Here, the number of cycles from issuance to completion of the function can be known from the order of register save and recovery.
Here, assuming that only the information of the register recovery code is used, only the information of the recovery code is generated. callee
Assuming that all the save registers are used, interprocedural dataflow information can be obtained without performing the dataflow information collecting compilation process 201. After that, as described above, if the compiling process 203 is performed, it is possible to perform instruction scheduling that recommends pipeline stall in consideration of data flow information between procedures.

[0027]

According to the present invention, it is possible to reduce pipeline stalls at the time of executing instructions that extend between procedures.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system in which a compiler that performs instruction scheduling according to the present invention operates.

FIG. 2 is a flowchart showing a compiling procedure for performing instruction scheduling according to the present invention.

FIG. 3 is a flowchart showing a processing flow of a compiler that performs instruction scheduling according to the present invention.

FIG. 4 is a diagram showing inter-procedural data flow information.

FIG. 5 is a flowchart showing a procedure of interprocedural instruction scheduling processing.

FIG. 6 is a diagram showing an example of a source program.

FIG. 7 is a diagram showing an example of a source program after the middle.

FIG. 8 is a diagram showing a dag of a function foo.

FIG. 9 is a diagram showing a schedule table as a result of instruction scheduling of a function foo.

FIG. 10: Function fu considering inter-procedural data flow information
The figure which shows dag of nc.

11 is a diagram showing a schedule table as a result of instruction scheduling from dag in FIG.

12 is a diagram showing a result of simulating the number of cycles when the schedule result of FIG. 10 is actually executed.

FIG. 13 is a diagram showing a dag of a function func created by a conventional technique.

FIG. 14 is a diagram showing a schedule table as a result of instruction scheduling from dag in FIG.

FIG. 15 is a diagram showing a result of simulating the number of cycles when the schedule result of FIG. 14 is actually executed.

FIG. 16 is a diagram showing an example of save and restore code of a callee save register.

FIG. 17 is a diagram showing interprocedural data flow information generated from the save / restore rules of the callee save register.

[Explanation of symbols]

101 ... CPU, 102 ... Display device, 103 ... Keyboard, 104 ... Main storage device, 105 ... External storage device.

Claims (5)

[Claims] 1. A method of checking data dependency and resource conflict between procedures in a compiler,
An instruction scheduling method having a step of performing instruction scheduling in consideration of a result of examination. 2. The compiler has a step of simply predicting data dependence and resource conflicts across procedures from rules at the time of procedure call, and a step of performing instruction scheduling based on the result of the prediction. An instruction scheduling method characterized by the above. 3. An instruction scheduling method, wherein in a compiler, instructions are arranged so as to reduce the occurrence of pipeline stall in an instruction string that extends between procedures. 4. Claim 1 or claim 2 or claim 3.
Compiler using the instruction scheduling method of. 5. A recording medium storing the compiler according to claim 3.