JP2003124843A - Sttd decoding method and sttd decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the power consumption for CDMA communication based upon the IMT2000 by suppressing an increase in the circuit scale of a circuit which demodulates an STTD encoded signal by interpolative synchronous detection. SOLUTION: While two successive symbols are paired, STTD (Space Time Block Coded Transmit Antenna Diversity) encoding is carried out, so the conventional method for demodulation by symbols is not employed and terms common to an operation coefficient generated by an operation coefficient generation part 5 or symbol data read out of a symbol storage memory 2 are put together in one to perform time-division operation over the two symbols, thereby decreasing the frequency (i.e., bus toggle rate) of a data read from a memory.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an STTD decoding method and an STTD decoder.

[0002]

2. Description of the Related Art The ITU (International Telecommunication Union) is developing a world-wide standard for mobile communication, IMT2000, which is one of the IMT2000 compatible standards.
-CDMA (Wide band Code Division Multiple Acces)
s) method was approved.

In the W-CDMA system, a transmission diversity technique is adopted as one of the techniques for improving the reception characteristic of a terminal. There are several modes for transmit diversity in W-CDMA. One of them is STTD (Space TimeBlock Coded Transmit Ante).
nna Diversity).

STTD is a signal processing that is optionally adopted when a base station of CDMA communication transmits information belonging to a dedicated downlink physical channel (DPCH) to a mobile station in an open loop mode. Is.

The STTD encoding will be described below.

As shown in FIG. 8A, the information symbols S1 and S2 are continuously input to the STTD encoder 112. In the figure, T and 2T indicate the passage of time.

The STTD encoder 112 includes the antenna 1
The 18 transmission symbols and the transmission symbols for the antenna 120 are output in parallel. The transmitted symbols for antenna 118 are "S1, S2", which is exactly the same as the input symbol.

On the other hand, the transmission symbols for the antenna 120 are "-S2 ^* , S1 ^*" . Here, “*” represents a complex conjugate number.

That is, the transmission symbol for the antenna 118 is obtained by calculating the conjugate complex number of the input data for two input symbols, changing the transmission order of the symbols, and multiplying the first transmission symbol by "-1". Desired.

As shown in FIG. 8B, the 4-phase phase modulation symbol (QPSK symbol) consists of 2-bit data representing the position on the phase plane (I, Q plane). The first bit shows the I component and the second data shows the Q component. The I component and the Q component respectively correspond to the real number component and the imaginary number component of the complex envelope of the modulated wave.

Let QPSK symbol be Sn. The symbol Sn consists of 2-bit data corresponding to a real number component and an imaginary number component. Each bit takes either "+1" or "-1".

That is, Sn = (± 1, ± 1).
In the following description, for example, S1 = (1,1) and S2
= (-1,1). Then, S1 ^* = (1, -1)
And −S2 ^* = S1 ^* = (1, −1).

As shown in FIG. 8A, the antenna 118
The signal transmitted from the signal arrives at one antenna 166 of the receiver (mobile station) 168 via the path and the path. On the other hand, the signal transmitted from the antenna 120 reaches one antenna 166 of the receiver (mobile station) 168 via the path and the path.

As shown in FIG. 8C, the received wave obtained by combining the signal passing through the path and the signal passing through the path and the received wave obtained by combining the signal passing through the path and the signal passing through the path , Fading is different.

That is, the probability that the valleys of the received waves and the peaks and the peaks of the received waves temporally overlap with each other is low. In FIG. 8C, the amplitudes of the received waves at time t1 and time t2 are different.

Further, by performing a predetermined decoding process on the received signal, the receiver 168 determines that the received signal wave is the one transmitted from the antenna 118 or the one transmitted from the antenna 120. You can distinguish what is.

Therefore, it is possible to improve the received signal quality by selecting a received wave having a large amplitude or combining the received waves.

Therefore, even if the receiver (mobile station) 168 has only one antenna 166, it is possible to improve the reception quality as in the case of performing antenna diversity reception.

[0019]

In a CDMA receiver,
In order to improve the detection characteristic, interpolation synchronous detection using pilot symbols is often performed. Interpolation synchronous detection is
Estimate the amplitude and phase shift that occurs in the transmission signal due to Rayleigh fading in the propagation path (atmosphere) from the detection result of the pilot signal included in the reception signal (more accurately, estimate the transfer function of the propagation path) This is a technique of interpolating the phase of an information symbol sandwiched between two pilot symbols using the transfer function thus obtained to obtain a more accurate demodulated signal.

The phase compensation in this interpolative synchronous detection is performed by complexly multiplying the received symbol by an arithmetic coefficient corresponding to the estimated transfer function, but the STTD-encoded signal is different from the ordinary received signal. , Two consecutive symbols are encoded as one set,
Complex multiplication operation becomes complicated.

Since the complex multiplier is composed of a combination of the multiplier and the adder, the increase in the number of element circuits to be used is directly associated with the increase in the complexity of the operation, the scale of the complex multiplier is increased, and the power consumption is increased. Bring about an increase in The mobile phone needs to satisfy the strict demand for low power consumption, and the increase in the scale of the complex multiplier is against this demand.

The present invention solves such a problem by
It is an object of the present invention to efficiently perform interpolative synchronous detection also on a TTD-encoded signal and suppress an increase in circuit scale and power consumption.

[0023]

It is common knowledge that interpolation synchronous detection is performed for each symbol, but in the present invention, STTD is used.
For encoded signals, two consecutive symbols may be regarded as one set, and "computation coefficient (coefficient corresponding to transfer function)" and "received symbol data itself" in the operation of complex multiplication may be commonly used. A possible term is picked up, and paying attention to this commonality, the complex multiplication operation is alternately performed on two symbols in a time division manner. For example,
The first half of the first symbol, the first half of the second symbol, the second half of the first symbol, and the second half of the second symbol are calculated.

If the coefficient and the symbol data can be commonly used, it is not necessary to update the coefficient and the symbol data for each time-division operation. Therefore, the number of times the coefficient or symbol data is read from the memory (the number of read accesses) can be reduced. This also reduces the toggle rate of the bus (indicating the rate of change of data communicated over the bus), which reduces the charge and discharge current and reduces circuit power consumption. Can be realized.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

Before explaining the structure of the STTD decoder,
First, a propagation model of an STTD encoded signal (transmission signal), and a basic configuration and an arithmetic expression of complex multiplication when performing interpolation synchronous detection on the receiving side based on a conventional method will be described.

FIG. 9 shows a propagation model of the STTD encoded signal. In FIG. 9, T indicates the symbol time,
S1 is a transmission symbol 1 including I and Q components, and S2 is a transmission symbol 2.

The transmitting station basically uses two time-continuous symbols and two transmitting antennas to encode and transmit information symbols.

That is, at time T, the transmission antenna 1 and the transmission antenna 2 are respectively the conjugate complex numbers of the transmission symbols S1 and S2 multiplied by -1.
Send at the same time.

Next, at time 2T, the conjugate complex numbers of the transmission symbol S2 and the transmission symbol S1 are simultaneously transmitted from the transmission antenna 1 and the transmission antenna 2, respectively. After that, the same operation is repeated using the next two consecutive symbols.

As described above, STTD encoding is realized by combining two transmission symbols, performing temporal encoding, and simultaneously transmitting from two spatially different transmission antennas. Next, the transmitted information symbol is amplitude-varying and phase-varying under the influence of Rayleigh fading in a mobile communication environment, and is received.

That is, the symbol transmitted from the transmitting antenna 1 is received after being multiplied by the transfer function (channel estimation value) α1 of the amplitude fluctuation and the phase fluctuation. Similarly, the symbol transmitted from the transmission antenna 2 is received after being multiplied by the transfer function (channel estimation value) α2 of the amplitude fluctuation and the phase fluctuation.

At this time, it is reported that the propagation delay between the two antennas at the receiving end is sufficiently shorter than the chip rate, and the received symbol R1 or R2 is the information symbol transmitted simultaneously from the two antennas. It is received in the added state. Therefore, if the white noise is ignored, the received symbols R1 and R2 are expressed by the following equation (1).

R1 = S1.alpha.1-S2 * .alpha.2 (S2 * indicates a conjugate complex number of S2) R2 = S2.alpha.1 + S1 * .alpha.2 (S1 * indicates a conjugate complex number of S1) ... Equation (1) receiver Then, the received symbols R1 and R represented by the equation (1)
2 and the estimated values α1 and α2 of the transfer function in the propagation path of each transmitting antenna, synchronous detection and STTD decoding are performed to demodulate S1 and S2. That is, when the transmission symbols S1 and S2 are demodulated using the equation (1), the equation (2)
It is expressed as.

2 · S1 = R1 · α1 * + R2 * · α2 2 · S2 = −R1 · α2 + R2 · α1 * Equation (2) Here, STTD decoding is realized by changing the calculation procedure of synchronous detection. Therefore, the circuit configuration is as shown in FIG.
A synchronous detection circuit in the interpolated synchronous detection system shown in FIG. Specifically, the calculation of the above formulas (1) and (2) can be performed by, for example, a calculation circuit having a configuration as shown in FIG.

However, in order to realize the synchronous detection accompanied by STTD decoding, the following problems occur as compared with the conventional synchronous detection for each symbol.

That is, when the transmission diversity by STTD is not applied, the same unencoded symbols are simultaneously transmitted from two antennas. Therefore, when the white noise is ignored, the received symbols R1 and R2 are represented by the following equation (3).

S1 = R1 · α * (here, α = α1 + α2) S2 = R2 · α * (Equation (3)) Here, Equation (2) (operational expression when STTD encoding is performed) and Equation (3) 3) (arithmetic expression when STTD encoding is not performed) is expanded in consideration of the I component and the Q component, the following expressions (4) and (5) are obtained, respectively. S1i = α1i ・ R1i ＋ α1q ・ R1q ＋ α2i ・ R2i ＋ α2q ・ R2q S1q = -α1q ・ R1i ＋ α1i ・ R1q ＋ α2q ・ R2i-α2i ・ R2q S2i = α1i ・ R2q ・ α2q ・ α2q ・ α2i ・ R2q・ R1q… Equation (4) S1i = αi ・ R1i ＋ αq ・ R1q S1q = -αq ・ R1i + αi ・ R1q S2i = αi ・ R2i ＋ αq ・ R2q S2q = ‐αq ・ R2i + αi ・ R2q… Equation (5) Formula (4) (STTD encoded signal) 11 (a) and 11 (b) show the order of the time-division processing of each of the calculation formulas for decoding (1) and the formulas (5) (calculation formulas when demodulating a signal without STTD encoding).

FIG. 11A shows an arithmetic expression of the interpolated synchronous detection (also used for STTD decoding) when performing STTD.
In the figure, ~ indicates the order of the time division processing. Figure 11
(B) shows a processing procedure of interpolation synchronous detection in the case of no STTD encoding. Similarly, in the figure, indicates the order of processing.

As is apparent from comparison between FIGS. 11A and 11B, when it is attempted to realize STTD decoding according to the conventional technique, the synchronous detection without STTD is as follows.
The process for restoring one symbol (S1 (or S2)) is only (or) process, whereas in the case of performing STTD decoding, the information symbol S
To demodulate 1 (S2), and (and)
It is necessary to perform the processing of in a time-sharing manner.

Therefore, as compared with the synchronous detection which does not use STTD, the configuration when performing STTD decoding is 1
The number of complex multiplications is required twice to demodulate the information symbols. In other words, the STTD decoding requires twice the amount of calculation as compared with the case where STTD is not applied, so that the power consumption of the circuit is doubled as compared with the conventional one.

Since the complex multiplier is composed of a combination of a multiplier and an adder, the circuit scale also increases.
The increase in power consumption of the complex multiplier greatly affects the talk time of the receiver.

The above is the result of the examination made by the inventor of the present invention.

In the present invention, in STTD decoding,
Instead of demodulating the information symbols S1 and S2 in sequence,
Two symbols are collectively considered as one set, and terms that can share coefficients and symbol data are preferentially processed in time division,
The bus toggle rate of input data to the phase compensation unit (which may be considered as the number of read accesses to the memory) is reduced to 1/2. The details will be described below.

(Embodiment 1) FIG. 7 is a block diagram showing a basic configuration of a synchronous detection circuit for performing interpolation interpolation synchronous detection.

The received symbols are despread by the despreading unit 1, and the demodulated information symbols are stored in the symbol storage memory 2 and input to the pilot symbol extracting unit 3. Pilot symbols used for transfer function estimation are extracted by pilot symbol extracting section 3 and input to transfer function estimating section 4.

The transfer function estimation unit 4 estimates the transfer function of the propagation path using known pilot symbols over several slots before and after the slot to be detected.

In the phase compensator 6, the symbol storage memory 2
The information symbol to be detected is read out of the information symbols accumulated in 1., and the phase of the information symbol is compensated by complex multiplication of the phase compensation amount obtained by the transfer function estimation unit 4. The output result of the phase compensator 6 is sent to the rake combiner 7.

The transfer function estimation and the coherent detection in the interpolative coherent detection are performed by, for example, "Seiichi Sampei, Fading distortion compensation method of 16QAM for land communication, B-B".
2 Vol.J72-B-2 PP.7-15 January 1989 ”.

FIG. 1 shows the STTD decoder (ST) of the present invention.
FIG. 9 is a block diagram showing an example of a specific configuration of an interpolation synchronous detection circuit having a TD decoding function).

In the phase compensator 6 of the circuit shown in FIG.
Instead of performing the operation for each symbol as in the conventional example of (a) and (b), the time division operation over two consecutive symbols is alternately performed as shown in FIG. As is clear from FIG. 2, in the circuit of FIG. 1, by preferentially performing time-division processing only on the portion where the calculation coefficient (transfer function) α can be commonly used,
Reduce the number of memory accesses (bus toggle rate).

The configuration and operation of the circuit shown in FIG. 1 will be described below.

In FIG. 1, first, the received symbols are despread by the despreading unit 1, and the demodulated information symbols are stored in the symbol storage memory 2 and input to the pilot symbol extracting unit 3.

The pilot symbols used for transfer function estimation are extracted by pilot symbol extracting section 3 and input to transfer function estimating section 4. Transfer function estimation unit 4
Then, the transfer function α1 in the propagation path of the two transmitting antennas,
α2 is estimated and input to the transfer function selection unit 5.

Next, the operation of the phase compensator 6 will be described in four stages. The phase compensating unit 6 performs each of the operations (1) to (3) shown in FIG. 2 in a time-division manner to obtain QPSK symbols (S1i, S1q) and QPSK symbols (S2i, S
2q) is demodulated.

In the first stage, the calculation shown in FIG. 2 is performed. That is, the in-phase / quadrature components R1i and R1q of the received information symbol R1 are read from the symbol storage memory 2 and supplied to the symbol input terminals Di and Dq of the phase compensating unit 6.

On the other hand, the coefficients (α1i, −α1q, α1q, α1i) generated from the arithmetic coefficient generating unit 5 are input to the ports (aw, ax, ay, az) to which the coefficient α of the phase compensation unit 6 is given. It

Then, multiplication by the multipliers 10 to 13
Addition is performed by the adders 14 and 15. This allows
The calculation shown in the upper left of FIG. 2 ends. The calculation result is supplied to the rake combining unit 7.

In the second stage, the processing shown in the lower right of FIG. 2 is performed. It should be noted here that, in the processing and the processing, since the symbols to be calculated do not change from Ri and Rq, it is not necessary to update the data.

Therefore, in the second stage, the phase compensator 6
The input to the input ports Di and Dq of is not changed, but only the coefficients given to the input ports aw, ax, ay, and az of the phase compensation unit 6 are changed. That is, the coefficients are -α2i, -α2q,
α2q and −α2i. As a result, the calculation of FIG. 2 is performed. The result of this operation is sent to the rake combiner 7 and added to the result of the complex multiplication in the first stage.

In the third stage, the operation shown in the upper right of FIG. 2 is performed. In the third stage, the in-phase / quadrature components R2i, R2q of the information symbol R2 are read from the symbol storage memory 2.
Is newly read, and the input port Di of the phase compensation unit 6 is
Input to Dq.

On the other hand, the input ports aw, ax,
For ay and az, α2i, α2q, and
-Α2q and α2i are input respectively. This calculation result is sent to the rake combining section 7 and added to the complex multiplication results in the first and second stages.

In the fourth stage, the arithmetic processing shown in the lower right of FIG. 2 is performed. It should be noted here that in processing and processing, the symbols to be operated are R2i, R
Since it does not change from 2q, it means that the data need not be updated.

Therefore, the input port D of the phase compensation unit 6
Without changing the inputs to i and Dq, α1i, α1q, -α1q, to the input ports aw, ax, ay, and az of the phase compensation unit 6
Input α1i, respectively. The result of this operation is
The result is sent to the rake combiner 7 and is added to the complex multiplication results of the first to third stages.

As a result, STTD decoding and synchronous detection are performed, and the symbols S1 and S2 are demodulated.

As is apparent from FIG. 2, in the STTD decoding method according to the present embodiment, information symbols (input ports Di, D of the phase compensator 6 are included in the four time division processes.
The information symbol input to q is updated only twice, so that the number of memory accesses and the bus toggle rate can be halved as compared with the conventional method in which data is updated for each time division process. Therefore, the power consumption of the circuit can be reduced. That is, according to the configuration of the present invention, when the bus widths of the input ports of the phase compensation unit 6 are the same, the power consumption can be reduced by 25% by the above operation.

In the above example, the phase compensator 6 is composed of a complex multiplier using four multipliers.
No matter how many multipliers are used, the information symbols R1 and R
It goes without saying that it can be implemented by using an arithmetic method in which 2 is fixed in a plurality of stages of processing.

(Embodiment 2) FIG. 3 shows an STT of the present invention.
It is a block diagram which shows the other structural example of a D decoder.

The characteristic of the STTD decoder of FIG. 3 is that, unlike the case of FIG. 1 (method of fixing the symbol data and changing the operation coefficient), the operation coefficient is commonly used and the symbol data is changed.

The concept is the same as that of the above-mentioned embodiment. The synchronous detection (S
The operation for TTD decoding (also used as TTD decoding) is four time division processes as shown in FIG.

The phase compensator 8 shown in FIG. 3 is as follows. That is, in the first stage, the process of FIG. 4 is performed. From the symbol storage memory 2, the information symbol R1
(R1i, R1q) is read and R1i, R1q, −
R1q and R1i are input ports Dw, Dx and D of the phase compensation unit 8.
Input to y and Dz.

Then, α1i and α1q are input from the arithmetic coefficient generating unit 9 to the input ports ai and aq of the phase compensating unit 8, respectively. Then, the calculation of the processing of FIG. 4 is performed, and the result is sent to the rake combining section 7 and is temporarily stored in the rake combining section 7.

In the second stage, the processing shown in FIG. 4 is performed.
That is, the input ports ai and aq of the phase compensation unit 8 are not changed, and the input ports Dw, Dx, Dy and Dz of the phase compensation unit 8 are not changed.
To R2i, R2q, R2q, and R2i, respectively. The calculation result is also sent to the rake combining unit 7 and added to the complex multiplication result in the first stage.

At the third stage, the transfer function estimation unit 4 outputs α
2 (α2i, α2q) is newly read and input to the input ports ai, aq of the phase compensation unit 8. Then, R2i, R2q, -R2q, R2i are input from the symbol storage memory 2 to the input ports Dw, Dx, Dy, Dz of the phase compensation unit 8, respectively. The calculation result is sent to the rake combining unit 7 and added to the complex multiplication results in the first and second stages.

In the fourth stage, the inputs to the input ports αi and αq of the phase compensating unit 8 are not changed, and the input ports Dw, Dx, Dy and Dz of the phase compensating unit 8 are connected to -R1i, -R1q and R1.
q and -R1i are input respectively. The result is also sent to the Rake combining unit 7 and added to the complex multiplication results in the first to third stages. As a result of the first to fourth stage processing, STTD decoding and synchronous detection are performed, and the symbols S1 and S2 are demodulated.

As is clear from FIG. 4, the second embodiment
In the STTD decoding method according to the above method, the change in the operation coefficient (that is, the transfer function estimated value) α1 or α2 input to the input ports αi and αq of the phase compensation unit is suppressed to two out of four times. , Bust toggle rate is 1/2
Is reduced to.

Therefore, according to the configuration of the present invention, by the above operation, it is possible to reduce the power consumption by 25% when the bus width of the input port of the phase compensation unit is the same.

In the above example, the phase compensating unit 8 is composed of a complex multiplier using four multipliers.
No matter how many multipliers are used, the transfer function estimated value α1,
It goes without saying that the calculation can be carried out using an arithmetic method in which α2 is fixed in a plurality of stages of processing.

The procedure of an example of the STTD decoding method of the present invention described above can be summarized as shown in FIG.

That is, the transfer function of the propagation path is estimated based on the pilot signal, the received information symbols (R1, R2) included in the received signal are corrected by the estimated transfer function, and the interpolated synchronous detection is performed. And demodulating the two continuous information symbols (S1, S2), the respective equations of complex multiplication necessary for demodulating each of the two continuous information symbols (S1, S2) are estimated. The transfer function (α1, α2) or the received symbol (R
1, R2), the first half term and the second half term are divided, and the first half terms of each arithmetic expression are set as a set, and each of the first half terms is calculated by the time division method (step 10).
0).

The latter half of each arithmetic expression is set as a set, and each of the latter half of the arithmetic is performed in a time division manner (step 101).

The first half term and the second half term are summed to demodulate each of the two continuous information symbols (S1, S2) (step 102).

(Third Embodiment) FIG. 6 is a block diagram of a CDMA receiver equipped with the synchronous detection circuit (also serving as the STTD decoder) described in the above embodiments.

The CDMA receiver shown in FIG. 6 has a receiving antenna 10, a high frequency signal processing section 11 for filtering at a predetermined frequency and demodulating into a baseband signal, and an A / D converting section 12 for converting an analog signal into a digital signal. And a despreading unit 13 that despreads the received signal at a predetermined timing to demodulate the data, and synchronous detection and STTD of the despread data.
Synchronous detection and STTD decoder (STTD) for decoding
Decoding section 14 and despreading, synchronous detection and ST
A rake combining unit 15 that rake combines TD-decoded multipaths and a channel codec unit 16 that performs channel decoding are provided. The received signal is demodulated into a baseband signal in the high frequency signal processing unit 11, and A / D
After being converted and converted into digital data, the despreading unit 1
Input to 3. The despreading unit 13 despreads and demodulates the data by the despreaders for the desired number of multipaths and the number of multiplex codes. The synchronous detection / STTD decoder (STTD decoding unit) 14 and the rake combining unit 15 perform rake combining by compensating the multipath phase of each of these plural data for each code.

The synchronous detection circuit (also STTD decoding section) 14 has the same configuration as that of the first or second embodiment, and is useful for reducing power consumption.

[0086]

As described above, according to the present invention, the order of time division processing in STTD decoding using synchronous detection is not demodulation of information symbols S1 and S2 in order, but two consecutive symbols are regarded as one. By processing as a unit and paying attention to the commonality of operation coefficients and data, the number of data updates can be reduced (memory access can be reduced). As a result, the bus toggle rate of the input in the phase compensation unit can be reduced to 1/2, and low power consumption of the circuit is achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an STTD decoder (STTD decoder / synchronous detection circuit) according to a first embodiment of the present invention.

2 is a diagram for explaining a procedure of a complex multiplication operation in the STTD decoder of FIG.

FIG. 3 is a block diagram showing a configuration of an STTD decoder (STTD decoder / synchronous detection circuit) according to a second exemplary embodiment of the present invention.

4 is a diagram for explaining the procedure of a complex multiplication operation in the STTD decoder of FIG.

FIG. 5 is a flowchart showing a procedure of synchronous detection (also used for STTD decoding) in the STTD decoder of the present invention.

FIG. 6 is a CDMA equipped with the STTD decoder of the present invention.
Block diagram showing the configuration of the receiver

FIG. 7 is a block diagram showing a basic configuration of a synchronous detection circuit.

FIG. 8A is a diagram for explaining the contents of STTD encoding. FIG. 8B is a diagram showing the relationship in the phase plane of the QPSK signal encoded by STTD. FIG. 8C is a diagram for explaining the effect of STTD encoding.

FIG. 9 is a diagram showing a propagation model until the STTD encoded signal reaches the receiving side.

FIG. 10 is a circuit diagram showing a configuration example of an arithmetic circuit required when performing STTD decoding based on a conventional method.

11A is a diagram showing the contents of complex multiplication in interpolated synchronous detection when STTD decoding is performed by the conventional method, and FIG. 11B is a complex multiplication in interpolated synchronous detection of complex multiplication without STTD decoding. Figure showing the contents of

[Explanation of symbols]

1,13 despreader 2 symbol storage memory 3 Pilot symbol extraction part 4 Transfer function estimation unit 5 Calculation coefficient generator 6 Phase compensation section 7,15 Lake synthesis section

Claims (3)

[Claims] 1. Two consecutive information symbols (S1, S
The signal transmitted from the transmission side after STTD encoding is applied to 2) is received by the reception side after the amplitude and phase fluctuations corresponding to the transfer function of the propagation path are received, and becomes the pilot signal inserted in the reception signal. The transfer function of the propagation path is estimated based on the transfer function, the received information symbols (R1, R2) included in the received signal are corrected by the estimated transfer function, and the interpolated synchronous detection is performed to perform the two continuous operations. When demodulating the information symbols (S1, S2), each of the two consecutive information symbols (S1, S2)
Each arithmetic expression of the complex multiplication necessary for demodulating is divided into the first half term and the second half term based on the commonality of the estimated transfer functions (α1, α2) or the received symbols (R1, R2), Each of the first half terms of each of the arithmetic expressions is set as a set, and each operation of the first half of the terms is performed in a time-sharing method. Each of the latter half terms is calculated, and the first half terms and the latter half terms are summed up to demodulate each of the two consecutive information symbols (S1, S2).
TTD decoding method. 2. An STTD decoder that performs interpolated synchronous detection to demodulate an STTD encoded signal, wherein the STTD decoder stores a received information symbol after despreading, and is used for transfer function estimation from the signal after despreading. A pilot symbol extracting section for extracting a pilot symbol to be used, a transfer function estimating section for estimating a transfer function in a propagation path, and an operation coefficient generating section for generating an operation coefficient necessary for STTD decoding based on the estimated transfer function estimated value. , When performing the complex multiplication operation of the interpolating synchronous detection that also serves as STTD decoding, each operation expression necessary for demodulating each of two consecutive information symbols is calculated by using the estimated transfer function or the received information symbol Based on the commonality, it is divided into the first half term and the second half term, and the first half terms of each arithmetic expression are set as a set. A phase compensator that performs each operation of the first half of the term by the time division method, sets the second half of the terms of each operation expression as a set, and performs each operation of the second half of the term by the time division method The result of complex multiplication in the phase compensation unit is added to demodulate two consecutive received information symbols, and
And a RAKE synthesizing section for synthesizing the STTD decoder. 3. A receiving antenna, a high-frequency signal processing unit for filtering at a predetermined frequency and demodulating into a baseband signal, an A / D conversion unit for converting an analog signal into a digital signal, and a receiving signal being reversed at a predetermined timing. 3. A despreading unit for spreading and demodulating data, an STTD decoder for interpolating and interlocking coherent detection according to claim 2 for performing coherent detection of the data after despreading, and a channel codec unit for performing channel decoding. CDMA receiver.