JP2003124824A5

JP2003124824A5 -

Info

Publication number: JP2003124824A5
Application number: JP2001317577A
Authority: JP
Filing date: 2001-10-16
Publication date: 2005-02-24
Anticipated expiration: 2021-10-16

Claims

A reference filter for band-limiting a complex input signal having two types of white baseband signals having a uniform spectrum as real parts and imaginary parts, respectively;
A delay unit for delaying the complex input signal by a time corresponding to the propagation delay of the reference filter;
An amplitude controller for outputting a complex impulse signal having an amplitude proportional to the excess when the amplitude component of the reference filter output signal exceeds a set value;
A peak factor reduction apparatus comprising: a subtractor that subtracts an amplitude control unit output signal from a delayer output signal .

The amplitude control unit
An absolute value circuit that outputs an absolute value based on the real and imaginary parts of the reference filter output signal;
A dead zone circuit that outputs an absolute value circuit output signal exceeding a predetermined value;
An impulse generation circuit for shaping an output signal of a dead zone circuit to generate an impulse signal having an amplitude proportional to the amplitude of the output of the dead zone circuit;
A first divider for dividing the absolute value circuit output signal from the real part of the reference filter output signal and outputting the cosine of the complex signal;
A second divider that outputs the sine of the complex signal by dividing the absolute value circuit output signal from the imaginary part of the reference filter output signal;
First and second delay devices for delaying the first and second divider outputs according to the processing delay of the impulse generator;
The first and second multipliers for generating a real part and an imaginary part of a complex impulse signal by multiplying the output signal of the impulse generation circuit by the output signal of the first and second delay elements, respectively. The peak factor reduction device according to 1.

The impulse generator circuit
A third delay device for delaying the output signal of the dead zone circuit by one sample;
A differentiation circuit that performs waveform differentiation by taking the difference between two consecutive samples of the dead zone circuit output signal;
A fourth delay device for delaying the differential circuit output signal by one sample;
A third multiplier that takes the product of each of the differentiator output signal and the fourth delayer output signal;
A negative value determiner that outputs an impulse signal having a unit amplitude when the third multiplier output is negative;
A gain circuit for normalizing the negative value detector output signal with the maximum impulse response value of the reference filter;
3. The peak factor reduction device according to claim 2, comprising a fourth multiplier that takes a product of each of the gain circuit output signal and the third multiplier output signal.

3. The peak factor according to claim 2, wherein the amplitude control unit omits the impulse generation circuit and replaces the dead zone circuit output signal with a gain circuit that reciprocates the maximum impulse response value of the filter. Reduction device.

5. The amplitude control unit is suspended when the sum of absolute values of the real part and the imaginary part of the reference filter output signal is equal to or less than a set value of a dead zone circuit. The peak factor reduction device described in 1.

A peak factor reduction device using a plurality of the peak factor reduction devices according to claim 1 in a plurality of cascade connection.

A baseband signal processing device comprising: the peak factor reduction device according to any one of claims 1 to 6; and a band limiting filter that limits a band of the peak factor reduction device output signal.

A spreading unit for spreading at least one digital modulated signal using a spreading code;
A multiplexing unit for multiplexing the spread signal;
An interpolator that oversamples the output signal of the multiplexing unit;
The interpolator output signal is input, a reference filter for band-limiting a complex input signal having two types of baseband signals as real parts and imaginary parts, respectively, and a complex input signal for a time corresponding to the propagation delay of the reference filter. a delay device for delaying an amplitude control unit for outputting a complex impulse signal having an amplitude which the amplitude components of the referenced filter output signal is proportional to the excess when exceeded the set value, the output signal from the delay unit and peak factor reduction device characterized in that it is composed of a subtractor for subtracting the No. LSE out of amplitude control unit,
A digital-analog converter for converting a digital output signal, which is an output of the peak factor reduction device, into an analog signal;
A radio transmitter comprising: a filter for smoothing the analog output signal; a frequency modulation unit; a power amplifier; and a control unit.

The amplitude control unit includes an absolute value circuit that outputs an absolute value based on a real part and an imaginary part of the reference filter output signal, and a dead zone circuit that outputs an excess of a predetermined value of the absolute value circuit output signal;
9. The radio transmitter according to claim 8, wherein the control unit supplies a set value signal of the dead zone circuit to the peak factor reduction device.

10. A radio predistortion device having an input / output characteristic that is an inverse function of a nonlinear input / output characteristic of a power amplifier is disposed between the baseband signal processing device and the digital-analog converter. Transmitter.