JP2003124814A - Digital-to-analog converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a high-accuracy digital-to-analog converting circuit which is adaptive to an input signal of different sampling frequency. SOLUTION: A sampling rate converting circuit (SRC) 110 converts the sampling frequency of an input signal Sin to 48 kHz or 96 kHz and a digital signal S2 generated through specific signal processing by a DSP 120 is outputted to a 1-bit DAC 130 to generate a 1-bit signal S3, which is outputted to a PDM circuit (pulse density modulator) 140. The PDM circuit can set the gain of a low-pass filter connected to a trailing stage to a fixed value not dependent on the sampling rate of the input signal by controlling the waveform rate of a pulse-density modulated signal S4 to a constant rate by setting specific data in a specific cycle of a clock signal CLK with respect to the 1-bit data inputted from the 1-bit DAC according to the sampling frequency of the input signal Sin , so that the high-precision signal processing can be actualized while the filter constitution is made simple.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog conversion circuit that can handle a plurality of sampling frequencies.

[0002]

2. Description of the Related Art Usually, as a modulated clock signal used in a 1-bit DAC (digital / analog conversion circuit),
A clock signal having a frequency that is a multiple of 2 or an integral multiple thereof such as 512 times or 768 times the sampling frequency f _s is used. Further, if the jitter of the modulated clock signal is large, the characteristics are deteriorated. Therefore, it is desirable to use a crystal oscillator capable of generating a clock signal at a stable oscillation frequency without using a PLL circuit for generating the clock signal. Therefore, the sampling frequency f _s that can be handled by the 1-bit DAC is fixed, and is not suitable for use in handling data of various sampling frequencies.

To support a plurality of sampling frequencies f _s , a sampling rate converter (Sampling Rate)
Converter: SRC) is required to perform interpolation or thinning processing to convert the data acquired at different sampling frequencies into a fixed sampling frequency f _s . For example, if the sampling frequency f _s of the 1-bit DAC is 48k
When fixed to Hz, sampling frequency f _s = 32k
Hz or f _s = 44.1 kHz data is f _s = 4
After being converted into 8 kHz data, it is converted into an analog signal with a 1-bit DAC.

[0004]

By the way, in the above-mentioned conventional digital / analog conversion circuit, even high-quality audio data having a high sampling frequency is downsampled to a low sampling frequency and processed. There is a waste of losing the high quality properties of. For example, data having a sampling frequency of 96 kHz is down-sampled to 48 kHz, and the characteristics of the data having a sampling frequency of 96 kHz are wasted. On the other hand, a 1-bit DAC with a sampling frequency of 96 kHz
When the sampling frequency of 1 is set, when processing data of a low sampling frequency, waste is still caused due to processing steps.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a highly accurate digital / analog conversion circuit which can cope with different sampling frequencies and which has little jitter.

[0006]

In order to achieve the above object, a digital / analog conversion circuit of the present invention is a digital / analog conversion circuit for converting a digital signal into an analog signal, and has a sampling rate of the digital signal. Accordingly, the sampling frequency of the digital signal is set to the one of the first and second sampling rates.
Sampling rate conversion means for converting to any one,
A 1-bit DAC for over-sampling the digital signal after conversion of the sampling rate at a predetermined magnification and converting it into 1-bit data, and an oscillating means for generating a clock signal having an oscillation frequency that is an integral multiple of the over-sampling frequency. And a pulse for holding the sampling data at a predetermined value in a predetermined cycle of the clock signal so as to keep the waveform ratio constant with respect to the oversampled 1-bit data according to the sampling rate after the conversion. It has a modulation circuit and a constant gain filter for extracting a predetermined low frequency component from the signal modulated by the pulse modulation circuit.

Further, in the present invention, it is preferable that the first sampling rate is 48 kHz and the second sampling rate is 96 kHz.

[0008]

1 is a block diagram of a digital / digital converter according to the present invention.
It is a circuit diagram which shows one Embodiment of an analog conversion circuit. As shown in the figure, the digital / analog conversion circuit of the present embodiment includes a sampling rate converter 110 and a DSP 1.
20, 1-bit DAC130, PDM (Pulse Density
Modulator) circuit 140, low-pass filter (LPF)
150 and a crystal oscillator 160.

The configuration and function of each component of the digital / analog conversion circuit of this embodiment will be described below.

The sampling rate converter 110 is
The input signal S _in is converted into data having a predetermined sampling frequency. Here, the input signal S _in is, for example, PCM audio data. The sampling frequency of the input signal S _in is determined by the standard of each audio signal, and is, for example, 32 kHz, 44.1 kHz, 48 kHz.
And 96 kHz. As described above, in order to process the input signals S _in having different sampling frequencies, the processing circuits of the subsequent stages are complicated in circuit configuration to cope with a plurality of sampling frequencies, resulting in an increase in circuit scale and an increase in cost.

Therefore, in the digital / analog conversion circuit of the present embodiment, the sampling rate converter 110 is used to interpolate different sampling frequencies or reduce the sampling frequency to 4
Convert to either 8 kHz or 96 kHz.

When the sampling frequency f _s of the input signal S _in is 48 kHz or 96 kHz, the input signal and the master clock signal of the digital / analog conversion circuit,
For example, if the data is not synchronized with the oscillation signal of the crystal oscillator, it is necessary to convert the timing by the sampling rate converter 110 in order to synchronize the data with the master clock signal. Sampling rate converter 11
The converted data output by 0 becomes PCM data having a sampling frequency of 48 kHz or 96 kHz, and the converted data is input to the DSP 120. The sampling rate converter 110 also generates a flag signal S _f indicating the bit rate of the output data and outputs it to the PDM circuit 140.

The DSP 120 performs necessary processing on the input data and outputs the processing result to the 1-bit DAC 130 as PCM data. In addition, DSP1
The processing in 20 is not essential, and when this processing is not necessary depending on the standard of the input signal S _in , the state of signal quality, etc., the output data of the sampling rate converter 110 can be directly output to the 1-bit DAC 130. . The 1-bit DAC 130 converts the input PCM data into an analog signal, and the conversion result is the PDM circuit 140.
Output to.

The PDM circuit 140 performs PDM modulation (pulse density modulation) on the input signal in accordance with the clock signal CLK generated by the crystal oscillator 160, and outputs the modulated signal to the low pass filter 150.

The low pass filter 150 includes the PDM circuit 4
With respect to the PDM modulation signal input from 0, its harmonic component is attenuated and a signal S _out in a predetermined low frequency band is output. The output signal S of the low pass filter 150
_out is the result of digital / analog conversion of the digital signal S _in input to the sampling rate converter 110.

The configurations of the 1-bit DAC 130 and the PDM circuit 140, which are the components of the digital / analog conversion circuit of this embodiment, will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing a configuration example of the 1-bit DAC 130. As illustrated, here, as an example, the 1-bit DAC 130 is assumed to be configured by a third-order ΔΣ (delta sigma) modulator.

As shown in FIG. 2, a 1-bit DAC 130 is provided.
Are three integrators 10, 20, 30, a quantizer 40, and multipliers 101, 103, 104, 105, 107, 10
8 and subtractors 102 and 106. Each of the integrators 10, 20 and 30 is composed of an adder and a delay device. For example, the integrator 10 includes an adder 11 and a delay device 12. The delay device 12 gives a delay of one sample period to the input signal. The adder 11 calculates the sum of the input signal and the output signal of the delay device, and outputs the addition result to the delay device 12. The quantizer 40 quantizes the input signal and outputs a digital signal.

As shown in FIG. 2, the result obtained by multiplying the input signal X (input signal S2 in FIG. 1) by the constant a by the multiplier 101 is input to the subtractor 102. Subtractor 102
Output signal multipliers 103, 10 of the multiplier 101
The subtraction result with the output signal of 8 is obtained, and the subtraction result is output to the integrator 10. The integration result obtained by the integrator 10 is input to the integrator 20 via the multiplier 104.
The integration result of the integrator 20 is passed through the multiplier 105 to the subtractor 1
It is input to 06. The output signal of the integrator 20 is also output to the multiplier 108. The subtractor 106 performs a subtraction process on the output signal of the multiplier 105 and the output signal of the multiplier 107, and the subtraction result is input to the integrator 30. The integrator 30 integrates the input signal and outputs the integration result to the quantizer 40.
Is output to.

The quantizer 40 quantizes the input signal and outputs a delta-sigma modulated signal Y (output signal S3 in FIG. 1). The output signal Y of the quantizer 40 contains the quantization noise Q. As illustrated, the output signal of the quantizer 40 is output to the multiplier 103 and the multiplier 107, respectively.

1-bit DAC constructed as described above
The input digital signal X is converted into a delta-sigma modulated signal Y by 130. The delta-sigma modulated signal Y is input to the PDM circuit 140 at the subsequent stage. The configuration example of the 1-bit DAC 130 shown in FIG.
1-bit D of the present invention, which is composed of a modulator
The AC is not limited to such a configuration example, and may be configured by, for example, a primary or secondary ΔΣ modulator.

Next, FIG. 3 shows an example of the configuration of the PDM circuit 140. As illustrated, the PDM circuit 140 includes a counter 142, a basic waveform synthesizing circuit 144, and a PDM waveform synthesizing circuit 146.

The counter 142 receives the clock signal CLK generated by the crystal oscillator 160 and counts accordingly. The counter 142 is composed of, for example, an n-bit binary counter and has a clock signal C.
By counting LK, n-bit count data S _C is generated and output to the basic waveform synthesis circuit 144.

The basic waveform synthesis circuit 144 includes a counter 14
The basic waveform S _A of the PDM signal is generated according to the n-bit count data S _C supplied from 2 and the flag signal S _f indicating the bit rate output from the sampling bit rate conversion circuit 110. PDM waveform synthesis circuit 14
6 is the basic waveform S _A and the output signal S3 of the 1-bit DAC
The PDM modulated signal S4 is synthesized in accordance with

In the PDM circuit 140 configured as above,
The 1-bit DAC 130 outputs the delta
Depending on the bear modulation signal S3 and its bit rate, the PD
The M modulation signal S4 is generated. For example, sampling
When the bit rate is 48 kHz, the bit rate flag signal S _f 
Is held at level 1 and sampling rate is 96kHz
When z, the bit rate flag signal S_f Is above level 1
Held at level 2 different from. Therefore, the PDM circuit
140 is a bit rate flag signal S_f Depending on the level of
Know the sampling rate, and adjust the PDM waveform accordingly.
Control synthesis.

The operations of the 1-bit DAC 130, the PDM circuit 140, etc. will be described below with reference to the signal waveform diagrams. FIG. 4 is a waveform diagram showing signal waveforms during operation of the digital / analog conversion circuit of this embodiment. The operation of the digital / analog conversion circuit of this embodiment will be described below with reference to this waveform diagram. FIG. 4A shows a modulated clock signal CLK generated by the crystal oscillator 160.
Shows the timing of. Here, the sampling frequency f _s of the input signal S _in is set to, for example, 48 kHz.
The crystal oscillator 160 provides a clock signal that is 512 times the sampling frequency f _s of the input signal S _in , that is, 24.5.
The 76 MHz modulated clock signal CLK is generated, and PD
It is supplied to the M circuit 140.

FIG. 4B shows a waveform of 1-bit data oversampled at a sampling frequency of 64 _fs when the sampling frequency f _s is 48 kHz. As shown in the figure, since the frequency of the clock signal CLK is generated to be 512 times the sampling frequency, the period T ₁ of 1-bit data oversampled at the sampling frequency of 64 _fs is 8 periods of the clock signal CLK. Equivalent to.

1-bit data oversampled at a sampling frequency of 64 _fs is generated by the 1-bit DAC 130 shown in FIG. 1 and output to the PDM circuit 140. In the PDM circuit 140, as shown in FIG. 3, the PDM waveform synthesis circuit 146 synthesizes PDM waveforms according to the sampling rate of 1-bit data. As shown in FIG. 4B, for example, when the 1-bit data is “1”, the over-sampled 1-bit data is held at the data “1” (for example, high level) for 8 cycles of the clock signal CLK. . On the other hand, as shown in FIG. 4C, the PDM waveform synthesizing circuit 146 controls the clock signal C in the PDM modulation signal S4.
Data "1" is held in 6 cycles out of 8 cycles of LK, and the remaining 2 cycles are replaced with data "0".
When the 1-bit data is "0", the clock signal C
All eight cycles of LK become "0", and the PDM waveform synthesis circuit 146 holds the output data S4 at "0" as it is.

Here, when the ratio of the valid section of the data to the total section of the 1-bit data output from the 1-bit DAC 130 is defined as the waveform rate, as described above,
As a result of the pulse density modulation in the PDM circuit 140, when the sampling frequency is 48 kHz, 1-bit DAC1
In the entire section of 1-bit data output from 30, that is, in the 8 cycles of the clock signal, the ratio of the valid section of the data is 6 cycles, and the waveform ratio is 6/8 = 3/4. That is, when the delta-sigma modulated signal output from the 1-bit DAC 130 corresponds to the data "1", 3/4 of the period of the PDM signal waveform is high level, ¼
The section is converted to a low-level pulse signal and the waveform ratio is 3
It becomes constant at / 4.

Next, the sampling frequency is 96 kHz.
The case will be described. Figure 4 (d) shows the sampling frequency.
Wave number f_s Is 96 kHz, oversampling
The waveform of 1-bit data is shown. As shown,
Sampling f _s Is 96kHz, 64f_s And oh
Cycle T of 1-bit data sampled by bar sampling₂ Is
This corresponds to four cycles of the lock signal CLK.

At this time, the PDM waveform synthesizing circuit 146 sets P according to the sampling rate of 1-bit data.
The waveform of the DM modulation signal is synthesized. As shown in FIG. 4E, for example, when the 1-bit data is “1”, the oversampled 1-bit data is held in the data “1” for four cycles of the clock signal CLK.
On the other hand, the PDM waveform synthesizing circuit 146 selects 3 out of 4 cycles of the clock signal CLK in the output data S4.
The data "1" is held for the period and the remaining one period is replaced with the data "0". In the case of 1-bit data "0", all four cycles of the clock signal CLK become "0", and the PDM waveform synthesis circuit 146 holds the output data S4 as it is as "0".

That is, as a result of the pulse density modulation in the PDM circuit 140, when the sampling frequency is 96 kHz, the waveform of data "1" in the 1-bit data output from the 1-bit DAC 130 corresponds to four cycles of the clock signal CLK. Of these, the waveform ratio of the output pulse signal is changed so that three cycles are at a high level and the remaining one cycle is at a low level. Therefore, the 1-bit DAC 130
Of the output signal of 1 is the pulse corresponding to the data “1” which is continuously held at the high level for one cycle of the pulse.
It is converted into a high level pulse signal in the 3/4 section of the cycle and a low level pulse signal in the 1/4 section, and the waveform ratio is 3/4,
It will be constant.

As described above, in the digital / analog conversion circuit of this embodiment, the PDM circuit 140 is responsive to the sampling rate of the input 1-bit data.
The pulse density modulation is performed so that the ratio of the effective data in the entire data section of the waveform of the output PDM modulated signal, that is, the waveform rate is constant. For example, when the sampling rate is 48 kHz, of the 8 cycles of the clock signal CLK corresponding to 1-bit data "1", 6 cycles are held at "1" (high level) and 2 cycles are "0". Hold on. On the other hand, the sampling rate is 9
At 6 kHz, of the four cycles of the clock signal CLK corresponding to 1-bit data "1", three cycles are held at "1" and the remaining one cycle is held at "0".

As a result, the sampling frequency is 48k.
PDM at either Hz or 96 kHz
Since the waveform ratio of the output signal S4 of the circuit 140, that is, the output signal of the PDM waveform synthesis circuit 146 shown in FIG. 3 is held equal, the gain characteristic of the low-pass filter 150 provided on the output side of the PDM circuit 140 is changed. Different sampling frequencies of 48 kHz or 96 kHz can be accommodated, the configuration of the low-pass filter 150 composed of analog filters can be simplified, control of filter characteristics by switching of sampling frequencies becomes unnecessary, and It is possible to construct a high-precision analog filter that can handle the sampling frequency.

As described above, according to the present embodiment, the PD ratio of the output signal of the PDM circuit is always kept constant without depending on the sampling frequency.
The gain characteristic of the analog low pass filter provided for extracting the low frequency component of the PDM modulated signal output from the M circuit can be held constant, and the characteristic can be improved while simplifying the configuration of the low pass filter. Accurate signal processing can be realized.

[0035]

As described above, according to the digital / analog conversion circuit of the present invention, the waveform ratio of the output signal of the PDM circuit is kept constant without depending on the sampling frequency. The gain characteristic of the low-pass filter can be held constant, and the characteristic can be improved while simplifying the configuration of the filter.
Further, according to the present invention, it is possible to provide a PDM modulation clock signal by using a high-precision crystal oscillator instead of the PLL circuit, suppress the influence of jitter of the clock signal generated by the PLL circuit, and Since it is not necessary to increase the frequency of the crystal oscillator, there is an advantage that a highly accurate digital / analog conversion can be easily realized while simplifying the circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a digital / analog conversion circuit according to the present invention.

FIG. 2 is a circuit diagram showing an example of a ΔΣ modulator that constitutes the 1-bit DAC of the present embodiment.

FIG. 3 is a PDM forming the 1-bit DAC of the present embodiment.
It is a circuit diagram showing an example of a circuit.

FIG. 4 is a waveform diagram showing the operation of the digital / analog conversion circuit of the present embodiment.

[Explanation of symbols]

110 ... Sampling rate converter (SRC), 1
20 ... DSP, 130 ... 1-bit DAC, 140 ... PD
M circuit, 142 ... Counter, 144 ... Basic waveform synthesis circuit, 146 ... PDM waveform synthesis circuit, 150 ... Low pass filter (LPF).

Claims (2)

[Claims] 1. A digital / analog conversion circuit for converting a digital signal into an analog signal, wherein a sampling frequency of the digital signal is selected from among a first sampling rate and a second sampling rate according to the sampling rate of the digital signal. Sampling rate conversion means for converting any one of them, 1-bit digital-analog conversion means for over-sampling the digital signal after conversion of the sampling rate by a predetermined magnification, and converting it to 1-bit data, and the over-sampling Oscillation means for generating a clock signal having an oscillation frequency that is an integral multiple of the frequency, and the clock signal for holding the waveform ratio constant for the oversampled 1-bit data according to the sampling rate after the conversion. For a predetermined period of A digital / analog conversion circuit having a pulse modulation circuit for holding sampling data at a predetermined value by a constant gain filter and a constant gain filter for extracting a predetermined low frequency component from the signal modulated by the pulse modulation circuit. 2. The first sampling rate is 48k
Hz and the second sampling rate is 96 kHz
The digital / analog conversion circuit according to claim 1, wherein z is z.