JP2003124813A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve S/N while suppressing an increase in power consumption and an increase in chip layout area. SOLUTION: One inverting amplifier 1 is provided in front of an analog ΔΣmodulator 13 to amplify only one of differential inputs and a digital gain circuit 4 is provided behind a digital filter 3, so that the digital gain circuit 4 compensates a deficiency in gain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and is particularly suitable for application to a gain controllable A / D converter.

[0002]

2. Description of the Related Art In a conventional A / D converter, when an A-time input signal amplification effect is obtained by a gain setting signal,
There has been a method of amplifying a digital signal by A times using a digital gain circuit. However, in this method, the noise component is also amplified by A times, so that the effect of improving the S / N ratio cannot be obtained.

Therefore, there is a method of amplifying the analog input signal on the analog side of the A / D converter in order to amplify only the signal component without amplifying the noise component. FIG. 6 is a block diagram showing a schematic configuration of a conventional A / D converter. In FIG. 6, the A / D converter is provided with an analog section and a digital section, the analog section is provided with inverting amplifiers 11 and 12 and an analog ΔΣ modulator 13, and the digital section is provided with a digital filter 14. ing.

Here, the inverting amplifier 11 is provided with an operational amplifier OP11, a resistor R11, a variable resistor R12 and a capacitor C21. The non-inverting input terminal of the operational amplifier OP11 is connected to the analog operating point voltage and the operational amplifier OP11 is inverted. The resistor R11 is connected to the input terminal, and the variable resistor R12 and the capacitor C21 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier OP11.

The inverting amplifier 12 has an operational amplifier O.
P12, resistors R13 and R14, and a capacitor C22 are provided, and the non-inverting input terminal of the operational amplifier OP12 is connected to the analog operating point voltage and the operational amplifier OP12.
A resistor R13 is connected to the inverting input terminal of 12 and a resistor R14 and a capacitor C22 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier OP12.

The output terminal of the operational amplifier OP11 is connected to the inverting input terminal of the analog ΔΣ modulator 13, and the operational amplifier OP12 is connected via the resistor R13.
Of the operational amplifier OP12, and the output terminal of the operational amplifier OP12 is connected to the non-inverting input terminal of the analog ΔΣ modulator 13. Here, the resistance value of the variable resistor R12 of the inverting amplifier 11 is set by the gain setting signal, and when a gain of A times is obtained, the resistance value of the variable resistor R12 and the resistance R1 are set.
The ratio R12 / R11 with the resistance value of 1 is set to A.

Further, in order to invert the input signal, the resistance R
Ratio of resistance value of 14 and resistance value of resistor R13 R14 / R1
3 is set to be 1. Analog input signal VI
When N1 is input to the inverting input terminal of the operational amplifier OP11 via the resistor R11, the analog input signal VIN1
Is inverted and amplified by the inverting amplifier 11 to R12 / R11 = A times. Then, the analog signal VIN2 inverted and amplified by A times is input to the inverting input terminal of the analog ΔΣ modulator 13 and the inverting amplifier 12.

When the analog signal VIN2 that has been inverted and amplified by A times in the inverting amplifier 11 is input to the inverting amplifier 12, the analog signal VIN2 is inverted and the inverted analog signal VIN3 is output from the analog ΔΣ modulator 13. It is input to the non-inverting input terminal. Analog signal V
When IN2 and VIN3 are input to the analog ΔΣ modulator 13, the analog ΔΣ modulator 13 samples the signals at a predetermined cycle sufficiently faster than their signal frequencies and performs quantization to thereby convert the analog signals VIN2 and VIN3. The difference is converted into a noise-shaped digital signal.

Then, the digital signal obtained by the analog ΔΣ modulator 13 is input to the digital filter 14, the noise generated at the time of noise shaping is removed by the digital filter 14, and further thinned to a desired output data rate, It is output as a digital signal.
As a result, it is possible to perform A / D conversion while amplifying only the signal component A times without amplifying the noise component.

[0010]

However, the A / D converter in FIG. 6 requires the inverting amplifier 11 for amplifying the analog input signal and the inverting amplifier 12 for inverting the analog input signal. Becomes
Therefore, the A / D converter of FIG. 6 has a problem that the power consumption increases and the chip layout area also increases.

Therefore, an object of the present invention is to provide an A / D converter with a gain control function capable of improving the S / N ratio while suppressing an increase in power consumption and an increase in chip layout area. Is.

[0012]

In order to solve the above-mentioned problems, according to the A / D converter of claim 1, a single-ended analog input signal is converted into a differential analog input signal, and the differential analog input signal is converted. In an A / D converter capable of converting an input signal into a digital signal and variably setting a gain of the input analog signal, the single-ended analog input signal is a non-inverting input of the differential analog input signal, and the single It is characterized in that an inverting amplifier for inverting the end analog input signal and changing the gain based on the gain setting signal is provided, and an output signal of the inverting amplifier is used as an inverting input signal of the differential analog input signal.

As a result, it is possible to amplify only one of the differential analog input signals and control the gain of the analog signal input to the A / D converter. Therefore, it becomes possible to perform amplification in the analog section with one inverting amplifier, and even when the gain control of the A / D converter is performed, an increase in noise is suppressed while suppressing an increase in layout area and power consumption. It becomes possible to reduce.

According to another aspect of the present invention, the A / D converter further includes a digital gain circuit that changes the gain of the digital signal converted from the differential analog input signal based on the gain setting signal. Is characterized by. This makes it possible to compensate for the lack of gain even when the gain is less than the input full-scale range of the A / D converter due to the one-sided amplification of the differential analog input signal.

According to another aspect of the A / D converter of the present invention, the means for converting the differential analog input signal into a digital signal is a differential delta-sigma modulator having the differential analog input signal as an input. , And a digital filter for digitally processing the output of the differential delta-sigma modulator. As a result, it is possible to perform A / D conversion while shifting the noise outside the band of the input signal, and it is possible to remove the noise generated at that time and improve the conversion accuracy.

According to another aspect of the A / D converter of the present invention, the digital gain circuit includes a shifter for bit-shifting the digital signal.
As a result, it is possible to suppress an increase in the circuit size of the digital gain circuit, and it is possible to suppress an increase in the layout area even when the gain control is performed in the digital section.

According to another aspect of the A / D converter of the present invention, the digital gain circuit controls the number of bit shifts of the shifter based on the gain setting signal. As a result, multi-valued gain setting signals enable multi-stage gain setting.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A according to an embodiment of the present invention
The / D converter will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of an A / D converter according to an embodiment of the present invention.

In FIG. 1, the A / D converter is provided with an analog section and a digital section, the analog section is provided with an inverting amplifier 1 and an analog ΔΣ modulator 2, and the digital section is provided with a digital filter 3 and a digital filter. A gain circuit 4 is provided. Here, the inverting amplifier 1 is provided with an operational amplifier OP1, a resistor R1, a variable resistor R2, and a capacitor C1.
The non-inverting input terminal of 1 is connected to the analog operating point voltage, and the inverting input terminal of the operational amplifier OP1 has a resistor R
1 is connected, a variable resistor R2 and a capacitor C1 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier OP1, and the output terminal of the operational amplifier OP1 is connected to the inverting input terminal of the analog ΔΣ modulator 2. .

Here, the resistance value of the variable resistor R2 of the inverting amplifier 1 and the gain of the digital gain circuit 4 can be set by a gain setting signal. The analog input signal VIN1 is directly input to the non-inverting input terminal IN + of the analog ΔΣ modulator 2, and is also input to the inverting input terminal of the operational amplifier OP1 via the resistor R1.

When the analog input signal VIN1 is input to the inverting input terminal of the operational amplifier OP1 via the resistor R1,
The analog input signal VIN1 is converted by the inverting amplifier 1 into
It is inverted and amplified by (R2 / R1) times. And (R2 /
The analog signal VIN2 inverted and amplified R1) times is input to the inverting input terminal IN− of the analog ΔΣ modulator 2.

When the analog input signal VIN1 is analog ΔΣ
When the analog signal VIN2 that has been inverted and amplified by (R2 / R1) times is input to the inverting input terminal IN− of the analog ΔΣ modulator 2 while being input to the non-inverting input terminal IN + of the modulator 2, the analog ΔΣ modulator 2
Converts the difference between the analog signals VIN1 and VIN2 into a noise-shaped digital signal by performing quantization while sampling the signals at a predetermined cycle sufficiently faster than the signal frequencies.

Then, the digital signal obtained by the analog ΔΣ modulator 2 is input to the digital filter 3,
The noise generated at the time of noise shaping is removed by the digital filter 3, further thinned to a desired output data rate, and then input to the digital gain circuit 4.
Then, after being further amplified by the digital gain circuit 4,
It is output as a digital signal.

As a result, the analog ΔΣ modulator 2
The gain control can be performed by providing only one inverting amplifier 1 in the preceding stage, and the S / N ratio can be improved while suppressing an increase in the chip layout area.
Further, by providing the digital gain circuit 4 in the subsequent stage of the digital filter 3, it is possible to realize the gain effect by bit shifting to the higher bit side.

For this reason, in the present system in which only one of the differential inputs of the analog ΔΣ modulator 2 is amplified and the differential input of the analog ΔΣ modulator 2 is unbalanced to obtain a gain effect, the analog section is set to a desired gain. If a shortage occurs in the analog ΔΣ modulator 2, it is possible to compensate for the shortage of the gain in the digital section and realize the input full-scale range in the analog ΔΣ modulator 2. Since it is a gain effect due to bit shift, it is possible to suppress an increase in circuit scale.

FIG. 2 is a block diagram showing the schematic arrangement of an analog ΔΣ modulator according to an embodiment of the present invention. In FIG. 2, the analog ΔΣ modulator 2 has
Switched capacitor filter circuits F1 to F4, feedback circuits B1 to B3, an integrator 8 and a quantizer 9 are provided.

The switched capacitor filter circuit F1 includes a capacitor C11 and a MOS switch M.
1a, M1b, M1c are provided. One end of the capacitor C11 is connected to the non-inverting input IN + via the MOS switch M1a and is connected to the inverting input IN- via the MOS switch M1b, and the other end of the capacitor C11 is connected to the MOS switch M1c. Is connected to the analog operating point voltage and is also connected to the inverting input of the integrator 8 via the MOS switch M5a.

The switched capacitor filter circuit F2 includes a capacitor C12 and a MOS switch M2.
a, M2b, and M2c are provided. Then, one end of the capacitor C12 is connected to the inverting input IN- through the MOS switch M2a, and the MOS switch M2 is connected.
2b is connected to the non-inverting input IN +, the other end of the capacitor C12 is connected to the analog operating point voltage via the MOS switch M2c and the MOS switch M2.
It is connected to the non-inverting input of the integrator 8 via 5b.

The switched capacitor filter circuit F3 includes a capacitor C13 and a MOS switch M3.
a, M3b, and M3c are provided. Then, one end of the capacitor C13 is connected to the reference signal input (+) via the MOS switch M3a and at the same time MO
It is connected to the analog operating point voltage through the S switch M3b, and the other end of the capacitor C13 has a MOS switch M3c.
It is connected to the analog operating point voltage via and is also connected to the feedback circuit B2.

The switched capacitor filter circuit F4 includes a capacitor C14 and a MOS switch M4.
a, M4b, and M4c are provided. Then, one end of the capacitor C14 is connected to the reference signal input (-) via the MOS switch M4a and at the same time MO
It is connected to the analog operating point voltage through the S switch M4b, and the other end of the capacitor C14 has a MOS switch M4c.
It is connected to the analog operating point voltage via and is also connected to the feedback circuit B3.

The capacitance values of the capacitors C11 and C12 are set to Cs, and the capacitance values of the capacitors C13 and C14 are set to Cr. Further, the feedback circuit B1 is provided with an inverter IV, and the feedback circuit B2
Are provided with MOS switches M6a and M6b, and the feedback circuit B3 is provided with MOS switches M7a and M7b. Then, the output from the quantizer 9 is input to the feedback circuit B1, and the feedback circuit B1 outputs the control signal RS1 in which the output from the quantizer 9 is inverted and the quantizer 9 Is directly output as the control signal RS2.

The MOS switch M6a is provided between the output of the switched capacitor filter circuit F1 and the output of the switched capacitor filter circuit F3, and has a control signal R
Based on S1, these parts are turned on / off. The MOS switch M6b is a switched capacitor filter circuit F.
2 and the output of the switched capacitor filter circuit F3, and turns them on / off based on the control signal RS2.

The MOS switch M7a is provided between the output of the switched capacitor filter circuit F1 and the output of the switched capacitor filter circuit F4, and has a control signal R
Based on S2, these are turned on / off. The MOS switch M7b is a switched capacitor filter circuit F.
2 and the output of the switched capacitor filter circuit F4, and turns them on / off based on the control signal RS1.

The integrator 8 is provided with an operational amplifier OP2 and capacitors C15 and C16. One output of the operational amplifier OP2 is connected to the inverting input terminal via the capacitor C15, and the operational amplifier OP2
The other output of 2 is connected to the non-inverting input terminal via the capacitor C16, and the output from the operational amplifier OP2 is input to the quantizer 9.

FIG. 3 is a timing chart showing an operation example of the analog ΔΣ modulator according to the embodiment of the present invention. In FIG. 3, MOS switches M1a and M1 of FIG.
c, M2a, M2c, M3a, M3c, M4a, M4c
Control signal S1 of FIG. 3 (a) is input to the MOS switch M1a, when the control signal S1 is at H level.
M1c, M2a, M2c, M3a, M3c, M4a, M
4c is turned on, and when the control signal S1 is at L level, these MOS switches M1a, M1c, M2a, M2c, M3.
a, M3c, M4a and M4c are turned off.

Further, the MOS switches M1b and M2 shown in FIG.
b, M3b, M4b, M5a, and M5b are shown in FIG.
Control signal S2 of the MOS switch M1b, M2b, M3b,
When M4b, M5a, M5b are turned on and the control signal S2 is at L level, these MOS switches M1b, M2b, M
3b, M4b, M5a and M5b are turned off.

Here, the non-inverting input signal V _{IN +} is input to the non-inverting input terminal IN + of the analog ΔΣ modulator, and the inverting input signal V _IN− is input to the inverting input terminal IN− of the analog ΔΣ modulator. . When the control signal S1 is at H level and the control signal S2 is at L level, in the switched capacitor filter circuit F1, the MOS switches M1a and M1c are turned on and the non-inverted input signal V _{IN +} is sampled. And, in the capacitor C11,
A charge corresponding to the non-inverted input signal V _{IN +} is accumulated.

When the control signal S1 is at H level and the control signal S2 is at L level, in the switched capacitor filter circuit F2, the MOS switches M2a and M2c are turned on and the inverted input signal V _IN- is sampled. Then, the charge corresponding to the inverted input signal V _IN− is accumulated in the capacitor C12. Next, when the control signal S1 becomes L level and the control signal S2 becomes H level, in the switched capacitor filter circuit F1, the MOS switch M1
a and M1c are turned off, and the MOS switch M1b is turned off.
Turns on, and the MOS switch M5a turns on.
Therefore, the charge Q1 accumulated in the capacitor C11 becomes
It is input to the inverting input terminal of the operational amplifier OP2.

Here, the electric charge Q1 accumulated in the capacitor C11 becomes Q1 = Cs · (V _{IN +} −V _IN− ). Further, the control signal S1 is at L level, and the control signal S2 is
Becomes H level, in the switched capacitor filter circuit F2, the MOS switches M2a and M2c are turned off, the MOS switch M2b is turned on, and the MOS switch M5b is turned on. Therefore, the charge Q2 accumulated in the capacitor C12 is
2 is input to the non-inverting input terminal.

Here, the charge Q2 accumulated in the capacitor C12 becomes Q2 = Cs · (V _IN− −V _{IN +} ). Then, the charge Q accumulated in the capacitor C11
When 1 is input to the inverting input terminal of the operational amplifier OP2 and the charge Q2 accumulated in the capacitor C12 is input to the non-inverting input terminal of the operational amplifier OP2, these charges Q1 and Q2 are integrated, and the charge Q1 and Q2 shown in FIG. ),
Signals corresponding to these charges Q1 and Q2 are output to the quantizer 9.

When the quantizer 9 receives the signal from the integrator 8, the quantizer 9 quantizes the signal output from the integrator 8 and, as shown in FIG. 3D, the rising timing of the control signal S1. Outputs the quantization results D1 to D4.
The quantization results D1 to D4 are output to the digital filter 3 and also input to the feedback circuit B1, and the feedback circuit B1 controls the control signal RS.
1, RS2 is generated.

Then, the control signal RS1 is supplied to the MOS switches M6a and M7b, and when the quantization result is at the L level, the MOS switches M6a and M7b are turned on. The capacitor C1 corresponding to the reference signal (+)
The charge accumulated in 3 is charged and added to the inverting input terminal of the operational amplifier OP2, and the charge accumulated in the capacitor C14 corresponding to the reference signal (−) is charged and added to the non-inverting input terminal of the operational amplifier OP2. It

The control signal RS2 is supplied to the MOS switches M6b and M7a, and when the quantization result is at H level, the MOS switches M6b and M7a are turned on. The capacitor C1 corresponding to the reference signal (+)
The charge accumulated in 3 is charged and added to the non-inverting input terminal of the operational amplifier OP2, and the charge accumulated in the capacitor C14 corresponding to the reference signal (-) is added to the inverting input terminal of the operational amplifier OP2. It

Next, a method of setting the gain of the A / D converter of FIG. 1 will be described. First, when setting the gain of the A / D converter to 0 dB, the resistance R of the inverting amplifier 1
The resistance values of R1 and R2 are R1: R2 = 1: 1 = 50 kΩ:
The gain value in the digital gain circuit 4 is set to 0 dB while being set to 50 kΩ. Assuming that the amplitude of the analog input signal VIN1 is 1.8 Vpp, a 1.8 Vpp signal is input to the non-inverting input terminal IN + of the analog ΔΣ modulator 2 and the inverting input terminal IN− of the analog ΔΣ modulator 2 is input. Is-(R2 / R
1) ・ VIN1 =-(50kΩ / 50kΩ) ・ VIN1
= -1.8 Vpp signal is input.

Therefore, the input full-scale range of the analog ΔΣ modulator 2 is (1.8 Vpp-(-1.
8Vpp)) = 3.6Vpp, and the digital output of the A / D converter becomes a full scale code. Next, when the amplitude of the analog input signal VIN1 becomes 0.32 Vpp, the amplitude of the analog input signal VIN1 is changed to the analog Δ.
Input full scale range of Σ modulator 2 = 3.6V
To correspond to pp, set the gain of A / D converter to 1
Set to 5 dB.

In this case, the resistors R1 and R2 of the inverting amplifier 1 are
The resistance value of R1: R2 = 1: 4.625 = 50 kΩ:
When set to 231.25 kΩ, a signal of 0.32 Vpp is input to the non-inverting input terminal IN + of the analog ΔΣ modulator 2, and − (R2 / R1) · VIN1 is input to the inverting input terminal IN− of the analog ΔΣ modulator 2. =-
(231.25kΩ / 50kΩ) ・ VIN1 = -1.4
A signal of 8Vpp is input.

As a result, the input amplitude of the analog ΔΣ modulator 2 is (0.32Vpp-(-1.48Vp
p)) = 1.8 Vpp, and in order to obtain the input full scale range of the analog ΔΣ modulator 2 = 3.6 Vpp, the gain is insufficient by −20 · log (1.8 / 3.6) = 6 dB. Therefore, the gain of the digital gain circuit 4 is set to 6 dB, and the shortage of the gain in the analog section is compensated by the digital gain circuit 4. As a result, a gain of 15 dB can be obtained in the entire A / D converter.

Here, 6 dB in the digital gain circuit 4
A minute gain effect is realized by a 1-bit shift to the upper bit side. As a result, the digital gain circuit 4 can compensate for the shortage of gain in the analog section while suppressing an increase in circuit scale. Further, the gain setting signal may be multi-valued, the taps of the variable resistor R2 may be divided into multiple stages to select various resistance values, and the number of bit shifts of the digital gain circuit 4 may be selectable.

As a result, it is possible to perform multistage gain setting while suppressing an increase in circuit scale. Figure 4
FIG. 4 is a diagram showing a multistage gain setting method for an A / D converter according to an embodiment of the present invention. In FIG. 4A, the resistance values of the resistors R1 and R2 of the inverting amplifier 1 are represented by R1:
With the R2 = 1: 4.625 = 50 kΩ: 231.25 kΩ fixed, the total gain of the A / D converter can be increased by 6 dB each time the bit shift number of the digital gain circuit 4 is increased by 1 bit.

Further, in FIG. 4B, the variable resistor R2
The total gain of the A / D converter can be controlled more finely by adjusting the resistance value of. Here, the total gain of the A / D converter when the resistance value of the variable resistor R2 and the bit shift number of the digital gain circuit 4 are changed can be obtained by the following formula.

6 × (number of bit shifts) + 20 × log
((1 + R2 / (50 kΩ)) / 2) Unit dB In the embodiment of FIG. 4, the method of performing amplification has been described. However, the resistance value of the variable resistor R2 and the number of bit shifts of the digital gain circuit 4 cause attenuation. It may be set to be performed.

FIG. 5 shows an A / D according to an embodiment of the present invention.
It is a figure which shows S / N of a converter in comparison with a prior art example.
5A shows the case where amplification is performed only in the digital section, FIG. 5B shows the case where amplification is performed by the conventional example of FIG. 6, and FIG. 5C shows the embodiment of FIG. Shows the case where amplification was performed by. In FIG. 5A, when 15 dB amplification is performed only in the digital section, both the signal component S and the noise component N are amplified, so that the signal component of the digital signal output is 5.62S and the noise component is It becomes 5.62N.

Further, in FIG. 5B, when 15 dB amplification is performed by the conventional example of FIG. 6, since the input signal VIN is amplified in the analog section, only the signal component S is amplified and the digital signal output The signal component becomes 5.62S and the noise component N remains unchanged. However, in the conventional example of FIG. 6, since the input signal VIN is amplified, it is necessary to provide two inverting amplifiers 11 and 12 in the preceding stage of the analog ΔΣ modulator 2.

Therefore, not only the power consumption increases, but also the chip layout area increases. On the other hand, FIG.
In (c), when 15 dB amplification is performed according to the embodiment of FIG. 1, amplification of 9 dB is performed in the analog section, the noise component N remains unchanged, and the signal component becomes 2.8S.

Next, the remaining 6 dB is amplified in the digital section, and the noise component becomes 2N and the signal component becomes 5.62S. Here, in the embodiment of FIG. 1, since the input signal VIN is amplified, it is only necessary to provide one inverting amplifier 1 in the preceding stage of the analog ΔΣ modulator 2, and it is possible to suppress an increase in power consumption. At the same time, an increase in chip layout area can be suppressed.

Further, in the digital section, only a part of the gain needs to be amplified, and it is possible to suppress the increase of the noise component and compensate the shortage of the gain due to the one-sided amplification of the differential input. It is possible to suppress the increase in the chip layout area by realizing the amplification in step 1 by bit shifting.

[0057]

As described above, according to the present invention,
The gain of the analog signal input to the A / D converter can be controlled only by providing the inverting amplifier on the inverting input side. Even when the gain control of the A / D converter is performed, the layout area and power consumption are reduced. It is possible to suppress an increase in noise while suppressing an increase in noise.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an A / D converter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an analog ΔΣ modulator according to an embodiment of the present invention.

FIG. 3 is a timing diagram showing an operation example of the analog ΔΣ modulator according to the embodiment of the present invention.

FIG. 4 is a diagram showing a multi-stage gain setting method for an A / D converter according to an embodiment of the present invention.

FIG. 5 is a diagram showing S / N of an A / D converter according to an embodiment of the present invention in comparison with a conventional example.

FIG. 6 is a block diagram showing a schematic configuration of a conventional A / D converter.

[Explanation of symbols]

1 Inverting Amplifier 2 Analog ΔΣ Modulator (Fully Differential Switched Capacitor Filter) 3 Digital Filter 4 Digital Gain Circuits OP1, OP2 Op Amp R1 Resistor R2 Variable Resistors C1, C11 to C16 Capacitors F1 to F4 Switched Capacitor Filter Circuits B1 to B3 Feedback Circuit 8 Integrator 9 Quantizer IV Inverter M1a, M1b, M1c, M2a, M2b, M2c, M
3a, M3b, M3c, M4a, M4b, M4c, M5
a, M5b, M6a, M6b, M7a, M7b MOS switch

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Wataru Tabuchi             3050 Okada, Atsugi City, Kanagawa Prefecture Asahi Kasei Mai             Kuro System Co., Ltd. F-term (reference) 5J022 AA01 BA02 BA06 BA08 CA07                       CB00 CF02 CF07 CG01                 5J064 AA01 BA03 BB12 BC06 BC16                       BC19 BD01

Claims (5)

[Claims] 1. An A / D converter capable of converting a single-ended analog input signal into a differential analog input signal, converting the differential analog input signal into a digital signal, and variably setting a gain of the input analog signal. An inverting amplifier configured to use the single-ended analog input signal as a non-inverting input of the differential analog input signal, invert the single-ended analog input signal, and change the gain based on a gain setting signal, the inverting amplifier Is an inverted input signal of the differential analog input signal. 2. The A / D converter according to claim 1, further comprising a digital gain circuit that changes a gain of a digital signal converted from the differential analog input signal based on the gain setting signal. . 3. A means for converting the differential analog input signal to a digital signal, a differential delta-sigma modulator having the differential analog input signal as an input, and digital processing of an output of the differential delta-sigma modulator. 3. A / D converter according to claim 1 or 2, further comprising a digital filter. 4. The A / D converter according to claim 1, wherein the digital gain circuit includes a shifter that bit-shifts the digital signal. 5. The A / D converter according to claim 4, wherein the digital gain circuit controls the number of bit shifts of the shifter based on the gain setting signal.