JP2003124807A - Information processor and method, recording medium, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a system including a PLL circuit entering a deadlock state speedily recover to its normal state without troubling a user. SOLUTION: In a step S1, it is decided whether a VCO input voltage is within a reference range. When so, it is decided in a step S2 whether the PLL circuit is locked. When the PLL circuit is locked, a VCO output signal is used as a clock. When the PLL circuit is not locked, a through clock is used. When a state in which the VCO input voltage is not within the reference ranges lasts for longer than a specific time, a deadlock state is decide in a step S5. If it is not decided in a step S6 that the deadlock state successively exceeds the number of times, the PLL circuit is made to recover in a step S7. When it is decided the deadlock state exceeds the specified number of times, the fault of the PLL circuit is reported to the user in a step S8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method, a recording medium, and a program, and more particularly to a PL.
The present invention relates to an information processing apparatus and method, a recording medium, and a program that detect when an L (Phase Locked Loop) circuit falls into an unrecoverable deadlock state and automatically recover.

[0002]

2. Description of the Related Art A frequency multiplication circuit using a PLL circuit controls a motor speed, digitally tunes a receiving device such as a radio or a television receiver, and a CPU (Central Processing Unit) that requires a high frequency. Clock and OSD (On S
It is also used for the dot clock of creen display).

The PLL circuit consists of a reference input signal and a multiplied VCO.
(Voltage Controlled Oscillator) The target frequency is generated by comparing the phase with the output signal and inputting the voltage corresponding to the phase difference to the VCO circuit. That is, the PLL circuit is designed to return to the target frequency even if the power supply noise or the reference input signal fluctuates.

Incidentally, the PLL circuit is provided with a measure for inserting a reactance (L) and a bypass capacitor (C) in the power supply line to suppress the power supply noise and a measure to prevent the reference input signal from being disturbed.

However, if a power supply voltage or a reference input signal outside the reference range is input to the PLL circuit, the PLL circuit
The limit of the circuit recovery operation may be exceeded, and in the worst case, the PLL circuit (especially the VCO circuit built in the PLL circuit)
However, the unrecoverable state (hereinafter, deadlock (Dead Loc
It has been clarified by environmental tests (power on / off test, electrostatic / discharge test, etc.) that it will fall into (k) state).

[0006]

When the PLL circuit falls into a deadlock state, in the past, the user has to manually reset the system including the PLL circuit or turn the system power on again. There was an issue for which there was no countermeasure.

Conventionally, the information that can be detected regarding the operating condition of the PLL circuit is a lock signal output from the phase comparator of the PLL circuit. The lock signal is whether or not the PLL circuit is locked, that is, It only indicates whether or not the target frequency can be output, and does not indicate whether or not the PLL circuit is in the deadlock state.

That is, even if the PLL circuit falls into a deadlock state, the user cannot immediately recognize that.

The present invention has been made in view of such a situation, and by detecting that the PLL circuit has fallen into a deadlock state and automatically recovering it, without bothering the user, The purpose is to be able to quickly restore the system to a normal state.

[0010]

An information processing apparatus according to the present invention has a determination means for determining whether a value of a predetermined signal supplied from a PLL circuit is within a reference range, and a determination result of the determination means. On the basis of the above, it is characterized by including a determining means for determining whether or not the PLL circuit has fallen into a deadlock state, and a recovery means for recovering the PLL circuit that has fallen into a deadlock state, corresponding to the determination result of the determining means. To do.

The determination means is a V supplied from the PLL circuit.
It may be possible to determine whether the CO input voltage is within the reference range.

The determination means is a V supplied from the PLL circuit.
It may be possible to determine whether the frequency of the CO output signal is within the reference range.

The determination means determines that the PLL circuit has entered a deadlock state when the state in which the determination signal determines that the value of the predetermined signal is not within the reference range continues for a predetermined time or longer. can do.

The information processing apparatus according to the present invention, when the PLL circuit continuously falls into a deadlock state a predetermined number of times or more,
Notification means may be further included to notify the user that the circuit is defective.

The restoration means can reset the PLL circuit or turn on the power to the PLL circuit again.

The notifying means can notify the user that the PLL circuit has fallen into a deadlock state.

According to the information processing method of the present invention, the PLL is determined based on the determination step of determining whether the value of the predetermined signal supplied from the PLL circuit is within the reference range and the determination result of the processing of the determination step. It is characterized by including a determination step of determining whether or not the circuit has fallen into a deadlock state, and a restoration step of restoring the PLL circuit that has fallen into a deadlock state, corresponding to the determination result in the processing of the determination step. To do.

The program of the recording medium of the present invention is based on the judgment step of judging whether the value of the predetermined signal supplied from the PLL circuit is within the reference range and the judgment result in the processing of the judgment step. It is characterized by including a determination step of determining whether or not the PLL circuit has fallen into a deadlock state, and a restoration step of restoring the PLL circuit that has fallen into a deadlock state, corresponding to the determination result of the processing of the determination step. And

According to the program of the present invention, the PLL circuit determines whether the value of the predetermined signal supplied from the PLL circuit is within the reference range and the result of the determination step. It is characterized by causing a computer to execute a determination step of determining whether or not a deadlock state has occurred, and a restoration step of recovering a PLL circuit that has fallen into a deadlock state, corresponding to the determination result in the processing of the determination step. And

In the information processing apparatus and method and the program of the present invention, it is determined whether or not the value of the predetermined signal supplied from the PLL circuit is within the reference range, and the PLL circuit is determined based on the determination result. Is determined to have entered a deadlock state. Further, the PLL circuit that has fallen into the deadlock state is restored according to the result of the determination.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A configuration example of a PLL circuit control device to which the present invention is applied will be described with reference to FIG. The control circuit 1 includes a magnetic disk, an optical disk, a magneto-optical disk,
Alternatively, the control program stored in the recording medium 2 such as a semiconductor memory is read, and the PLL circuit 3 is controlled based on the read control program. Specifically, the state of the PLL circuit 3 is determined based on the VCO input voltage input via the A / D converter 5 and the count value of the counter 7, and the determination result is displayed on the display circuit 8 and is also determined. The switching of the selector 4 is controlled according to the result. Further, the PLL circuit 3 is reset or the power is turned on again.

The PLL circuit 3 is constructed, for example, as shown in FIG. The phase comparator 11 compares the phase of the reference input signal that is input with the phase of the VCO output signal that is multiplied by the programmable frequency divider 15, and the phase difference is determined by the low-pass filter 1
Output to 2. Further, the phase comparator 11 generates a lock signal and outputs a lock signal when the phases of both signals match.
Output to.

The low-pass filter 12 removes the high frequency component of the phase difference and outputs it as a VCO input voltage to the VCO circuit 14. Since the low-pass filter 12 is an important element that determines the response characteristic (lock time, damping characteristic) of the PLL circuit 3, a low-pass filter such as a capacitor shown in FIG. An external circuit 13 composed of a resistor is connected to optimize the operation.

The VCO circuit 14 responds to the VCO input voltage from the low-pass filter 12, generates a VCO output signal, and outputs it to the programmable frequency divider 15, the selector 4, and the 1 / N frequency divider 6. The programmable frequency divider 15 multiplies the VCO output signal and outputs it to the phase comparator 11.

Returning to FIG. Under the control of the control circuit 1, the selector 4 outputs the reference input signal (through clock) input from the previous stage or the VCO output signal input from the PLL circuit 3 to the subsequent stage. The A / D converter 5 is a PLL
The VCO input voltage output from the low-pass filter 12 of the circuit 3 is digitized and output to the control circuit 1. The 1 / N frequency divider 6 divides the VCO output signal of the PLL circuit 3 into 1 / N and outputs it to the counter 7. The 1 / N frequency divider 6 is omitted,
The VCO output signal of the PLL circuit 3 may be output to the counter 7. However, providing the 1 / N divider 6
This is effective when the frequency of the VCO output signal is high or when the digit of the count number of the counter 7 is limited.

The counter 7 counts the frequency of the VCO output signal input via the 1 / N frequency divider 6 and outputs the count value to the control circuit 1. Under the control of the control circuit 1, the display circuit 8 displays the state of the PLL circuit 3 (whether locked, deadlocked, broken, etc.).

Next, the operation (control processing) of the PLL circuit controller will be described with reference to the flowchart of FIG. 4 and FIGS. 5 and 6. FIG. 5 shows changes in the VCO input voltage when the PLL circuit 3 is operating normally. In FIG. 5, since the frequency of the reference input signal (oscillation in the figure) is almost the desired value (66 MHz),
VCO input voltage is stable. In FIG. 6, the frequency doubled as desired (132 MHz) is intentionally used as the reference input signal for the PLL.
VCO when input to circuit 3 and deadlocked
The change in input voltage is shown. In FIG. 6, the VCO input voltage is no longer stable and has risen to the PLL power supply voltage and cannot recover.

This control processing is started when the power of the electronic device mounting the PLL circuit control device is turned on. In step S1, the control circuit 1 determines whether the VCO input voltage input from the A / D converter 5 is within the reference range. Regarding the criterion for determining whether or not the VCO input voltage is within the reference range, for example, see FIG.
In the case of, when the PLL circuit 3 is locked, the VCO input voltage is about 1.0 V, and the VCO input voltage when a frequency that is ½ the reference input signal is input is about 0.7 V. ,
The VCO input voltage when inputting twice the frequency of the reference input signal is about 1.3V, so considering the margin,
It is determined that 0.5 to 1.5 V is within the reference range.

If it is determined in step S1 that the VCO input voltage is within the reference range, as shown in FIG. 5, the process proceeds to step S2. In step S2, the control circuit 1 determines whether or not the PLL circuit 3 is locked based on whether or not the lock signal is input from the phase comparator 11 of the PLL circuit 3. When it is determined that the PLL circuit 3 is locked, the process proceeds to step S3.
In step S3, the control circuit 1 controls the selector 4 to output the VCO output signal from the PLL circuit 3 to the subsequent stage. As a result, the VCO output signal output from the PLL circuit 3 is used as the clock of the electronic device. The process returns to step S1, and the subsequent processes are repeated.

If it is determined in step S2 that the PLL circuit 3 is not locked, the process proceeds to step S4.
In step S4, the control circuit 1 controls the selector 4 to output the reference input signal (through clock) that has not passed through the PLL circuit 3 to the subsequent stage. As a result, the through clock is used as the clock of the electronic device. The process returns to step S1, and the subsequent processes are repeated.

When it is determined in step S1 that the VCO input voltage is not within the reference range, as shown in FIG. 6, the process proceeds to step S5. In step S5, the control circuit 1 activates the built-in timer (or counts by chattering), and in order to eliminate the possibility that the VCO input voltage is not within the reference range during the transient period, the state is changed. It is determined whether or not it continues for a predetermined time (for example, 10 ms), that is, whether or not it is in a deadlock state.

While the VCO input voltage is not within the reference range, it is determined in step S2 that the PLL circuit 3 is not locked in order to avoid stall of the electronic device. The reference input signal is used as a clock, as in the case where the input signal is processed and proceeds to step S4.
When it is determined that the state in which the VCO input voltage is not within the reference range does not continue for the predetermined time or longer, the state is determined to be a transient period, and the process proceeds to step S4.

In step S5, the state in which the VCO input voltage is not within the reference range continues for a predetermined time or more,
That is, when it is determined that the deadlock state,
The process proceeds to step S6. In step S6, the control circuit 1 determines whether or not the number of times that the process is continuously determined to be in the deadlock state in step S5 exceeds a predetermined number (for example, 5 times). When it is determined that the number of times of continuous determination of the deadlock state does not exceed the predetermined number of times, the process proceeds to step S7.

In step S7, the control circuit 1 sets the PL
Restore L circuit 3. That is, it is reset or the power is turned on again. At this time, the display circuit 3 may display a deadlock state. The process returns to step S1, and the subsequent processes are repeated.

If it is determined in step S6 that the number of times that the deadlock state has been continuously determined exceeds the predetermined number of times, it is considered that the PLL circuit 3 is defective (failure), and therefore the process is performed in step S8. Proceed to. Step S8
At, the control circuit 1 causes the display circuit 3 to display information notifying the user of the failure. The process returns to step S1, and the subsequent processes are repeated.

Instead of determining in step S1 whether the VCO input voltage is within the reference range, it is determined whether the frequency of the divided VCO output signal input from the counter 7 is within the reference range. You may judge whether. Alternatively,
Both the determination as to whether the VCO input voltage is within the reference range and the determination as to whether the frequency of the divided VCO output signal input from the counter 7 is within the reference range may be performed. . By doing so, the frequency of the VCO output signal can be directly counted, so that the frequency deviation can be detected more accurately based on the A / D converter measurement of the VCO input voltage.

Frequency-divided VCO input from the counter 7
The criterion for determining whether or not the frequency of the output signal is within the reference range is 100 ± 10, that is, 9 when the count value of the counter 7 when the PLL circuit 3 is locked is 100.
Although 0 to 110 may be within the reference range, in consideration of instability during the transition period, for example, 50 to 200 is set within the reference range. This is the end of the description of the operation of the PLL circuit control device.

As described above, the PLL circuit control device can automatically recover even if the PLL circuit 3 falls into the deadlock state. In addition, the malfunction of the PLL circuit 3 can be notified to the user.

In the present specification, the steps for writing the program recorded on the recording medium are not limited to the processing performed in time series according to the order described, but may be performed in parallel if they are not necessarily performed in time series. Alternatively, it also includes processes that are individually executed.

In the present specification, the system means
It represents the entire apparatus composed of a plurality of devices.

[0041]

As described above, according to the information processing apparatus and method and the program of the present invention, it is determined whether or not the value of the predetermined signal supplied from the PLL circuit is within the reference range, and Based on the result of the determination, it is determined whether or not the PLL circuit has fallen into the deadlock state, and the PLL circuit that has fallen into the deadlock state is restored according to the result of the determination, which bothers the user. Without this, the system can be promptly returned to the normal state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a PLL circuit control device to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a PLL circuit 3 in FIG.

FIG. 3 is a block diagram showing a configuration example of an external circuit 13.

FIG. 4 is a flowchart illustrating a control process.

FIG. 5 is a diagram showing changes in the VCO input voltage when the PLL circuit 3 is operating normally.

[FIG. 6] V when the PLL circuit 3 falls into a deadlock state
It is a figure which shows the change of CO input voltage.

[Explanation of symbols]

1 control circuit, 2 recording medium, 3 PLL circuit, 4
Selector, 5 A / D converter, 6 1 / N frequency divider, 7 counter, 8 display circuit, 11 phase comparator, 12 low pass filter, 13 external circuit, 14 VCO circuit, 15 programmable frequency divider

Claims (10)

[Claims] 1. An information processing device for controlling a PLL circuit, comprising: a determining unit that determines whether a value of a predetermined signal supplied from the PLL circuit is within a reference range; and a determination result of the determining unit. Based on the determination result of the determination means, the recovery means for recovering the PLL circuit that has fallen into the deadlock state is included, based on the determination result of the determination means. An information processing device characterized by the above. 2. The information processing apparatus according to claim 1, wherein the determination means determines whether or not the VCO input voltage supplied from the PLL circuit is within a reference range. 3. The information processing apparatus according to claim 1, wherein the determination means determines whether or not the frequency of the VCO output signal supplied from the PLL circuit is within a reference range. 4. The determining means comprises:
2. The information processing according to claim 1, wherein when the state in which the value of the predetermined signal is determined not to be within the reference range continues for a predetermined time or more, it is determined that the PLL circuit is in a deadlock state. apparatus. 5. The information processing apparatus according to claim 1, wherein the restoration means resets the PLL circuit or turns on the power to the PLL circuit again. 6. The device according to claim 1, further comprising a notifying unit for notifying a user that the PLL circuit is defective when the PLL circuit continuously falls into the deadlock state a predetermined number of times or more. The information processing device according to 1. 7. The information processing apparatus according to claim 6, wherein the notification unit also notifies a user that the PLL circuit has fallen into the deadlock state. 8. An information processing method of an information processing device for controlling a PLL circuit, comprising: a determining step of determining whether or not a value of a predetermined signal supplied from the PLL circuit is within a reference range; Based on the judgment result of the process
A determination step of determining whether or not the L circuit has fallen into a deadlock state, and a restoration step of recovering the PLL circuit that has fallen into the deadlock state, corresponding to the determination result in the processing of the determination step. An information processing method characterized by the above. 9. A program for controlling a PLL circuit, comprising: a determining step of determining whether a value of a predetermined signal supplied from the PLL circuit is within a reference range; and a process of the determining step. Based on the judgment result in
A determination step of determining whether or not the L circuit has fallen into a deadlock state, and a restoration step of recovering the PLL circuit that has fallen into the deadlock state, corresponding to the determination result in the processing of the determination step. A recording medium having a computer-readable program recorded thereon. 10. A determination step of determining, to a computer controlling a PLL circuit, whether or not a value of a predetermined signal supplied from the PLL circuit is within a reference range, and a determination result in the processing of the determination step. Based on the PL
A determination step of determining whether or not the L circuit has fallen into a deadlock state, and a restoration step of recovering the PLL circuit that has fallen into the deadlock state according to the determination result of the processing of the determination step are performed. Program to let.