JP2003124461A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing effectively the generation of a leak current even when a distance between a source and a drain is small. SOLUTION: This semiconductor device is provided with a source region 2 and a drain region 3 in a pair formed in a silicon substrate 1 and with a channel region 4 which is formed between the source region 2 and the drain region 3 and has a larger band gap than that of the silicon substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a field effect transistor (FE).
T) and semiconductor devices such as semiconductor memories.

[0002]

2. Description of the Related Art In recent years, EPROM (Erasable a) has been used as a semiconductor memory that can replace magnetic disks such as hard disks and floppy (registered trademark) disks.
nd Programmable Read Only
Memory) and EEPROM (Electrica)
ly Erasable and Program
Non-volatile semiconductor memories such as Able Read Only Memory) are receiving attention.

In an EPROM or EEPROM memory cell, carriers are stored in a floating gate electrode, data is stored depending on the presence or absence of carriers, and data is read by detecting a change in threshold voltage depending on the presence or absence of carriers. Is going. Especially, in the EEPROM, data is erased in the entire memory cell array, or
There is a flash EEPROM that divides a memory cell array into arbitrary blocks and erases data in each block. This flash EEPROM is also called a flash memory, and has features that it can have a large capacity, low power consumption, high speed, and excellent impact resistance. For this reason,
Flash EEPROMs are used in various portable devices. Further, the memory cell of the flash EEPROM has an advantage that it can be easily highly integrated as compared with the EEPROM.

Conventionally, a stacked gate type and a split gate type have been proposed as memory cells constituting a flash EEPROM.

In the stacked gate type memory cell,
In the write operation that accumulates electrons in the floating gate electrode,
The electrons in the channel of the semiconductor substrate are made into hot electrons and injected into the floating gate. At that time, it is necessary to apply a voltage of ten and several volts to the control gate electrode. In the stacked gate type memory cell, in the erase operation for extracting the electrons accumulated in the floating gate electrode, the Fowler-Nordheim Tunnel current (Fowler-Nordheim Tunnel C
current, hereinafter referred to as FN tunnel current). At that time, it is necessary to apply a voltage of ten and several volts to the source region.

In the split gate type memory cell,
In the write operation that accumulates electrons in the floating gate electrode,
Electrons in the channel of the semiconductor substrate are made into hot electrons and injected into the floating gate electrode. At that time, it is necessary to apply a voltage of ten and several volts to the source region. Further, in the split gate type memory cell, in the erase operation of drawing out electrons from the floating gate electrode, an FN tunnel current flows from the control gate electrode to the floating gate electrode. At that time, it is necessary to apply a voltage of ten and several volts to the control gate electrode.

As described above, in the conventional stacked gate type and split gate type memory cells, hot electrons are used to inject electrons into the floating gate electrode in the write operation, and accumulated in the floating gate electrode in the erase operation. The FN tunnel current is used to extract the electrons.

By the way, in order to retain the carriers accumulated in the floating gate electrode for a long period of time, it is necessary to increase the thickness of the insulating film surrounding the floating gate electrode. However, when injecting or extracting electrons into the floating gate electrode,
It utilizes hot electrons or FN tunnel current. Therefore, as the thickness of the insulating film surrounding the floating gate electrode is increased, the voltage applied to the control gate electrode or the source region in the write operation or the erase operation (hereinafter, referred to as
It is necessary to increase the operating voltage of the memory cell).

The operating voltage of the memory cell is generated by the booster circuit. In this case, the practical voltage is up to ten and several volts. On the other hand, when a silicon oxide film is used as the insulating film surrounding the floating gate electrode, the operating voltage of the memory cell is set to 1
When the voltage is 0 and several V, it is difficult to make the thickness of the silicon oxide film 10 nm or more. Therefore, conventionally,
When a silicon oxide film is used as an insulating film surrounding the floating gate electrode in order to suppress the operating voltage of the memory cell to ten and several volts, the film thickness of the silicon oxide film is set to ten and several nm or less. It is known that if the film thickness of the silicon oxide film is 8 nm or more, the electrons accumulated in the floating gate electrode can be retained for a practically satisfactory period.

In the case of accumulating holes in the floating gate electrode, as in the case of accumulating electrons as described above, the thickness of the silicon oxide film as the insulating film surrounding the floating gate electrode is set to 8 nm or more. The holes accumulated in the floating gate electrode are retained for a period that is practically satisfactory.

[0011]

In recent years, flash EE has been used.
Even in PROMs, the retention period of carriers accumulated in the floating gate electrode is sufficiently long (10 years or more), and further lower voltage, higher speed operation, lower power consumption, and higher integration than ever have been achieved. It is required to aim for realization.

As described above, when the silicon oxide film is conventionally used as the insulating film surrounding the floating gate electrode, 1
In order to secure a carrier retention period of 0 years or more, it is desirable to avoid making the thickness of the silicon oxide film thinner than 8 nm.

By reducing the operating voltage of the memory cell, it is possible to speed up the writing operation and the erasing operation and reduce the power consumption. Even in the read operation that has the largest number of operation opportunities, it is very advantageous for high-speed read that the read voltage is large and the read cell current is large.

Further, the booster circuit for generating the operating voltage of the memory cell has a larger circuit scale as the generated voltage becomes higher. As for the transistors forming the peripheral circuits (decoder, sensor unit, buffer, etc.) of the flash EEPROM, the occupied area (transistor size) on the substrate increases as the withstand voltage increases. Therefore, if the operating voltage of the memory cell is lowered, the circuit scale of the booster circuit is reduced and the size of the transistor forming the peripheral circuit is also reduced, so that high integration can be achieved.

Therefore, by lowering the operating voltage of the memory cell, the operation speed is increased and the power consumption is reduced.
High integration can be achieved at the same time.

However, in the conventional stack gate type and split gate type memory cells, hot electrons or FN tunnel currents are used when injecting or drawing out electrons from the floating gate. Therefore, when the silicon oxide film is used as the insulating film surrounding the floating gate, the film thickness is required to be maintained at 8 to 10 nm as before. As a result, it is difficult to lower the operating voltage of the memory cell from the present level. That is,
Unless the structures of the conventional stack gate type and split gate type memory cells are changed, it is difficult to reduce the operating voltage of the memory cell while maintaining the same level of life as the present.

By the way, in the conventional field effect transistor (FET), if the distance between the pair of source / drain regions is reduced, there is a problem that a leak current is generated due to a punch through phenomenon or the like. Therefore, conventionally, it has been difficult to shorten the length of the channel region located between the source / drain regions. Therefore, it is difficult to achieve further miniaturization, and as a result, there has been a limit to high integration. Note that this problem also occurs in a flash EEPROM that uses a field effect transistor (FET) as a memory cell transistor.

The present invention has been made to solve the above problems, and one object of the present invention is to:
It is an object of the present invention to provide a semiconductor device capable of effectively preventing a leak current from occurring even when the distance between the source / drain becomes small.

Another object of the present invention is to provide a semiconductor device which performs an erase operation by extracting electrons from a floating gate and which can perform the erase operation at a low voltage.

[0020]

According to another aspect of the present invention, there is provided a semiconductor device including a pair of source / drain regions formed in a semiconductor substrate and a material formed between the pair of source / drain regions, the material being more than the material forming the semiconductor substrate. And a channel region having a large band gap. The source / drain region in the present invention means a source region or a drain region. Further, the semiconductor substrate in the present invention is a broad concept including not only a normal semiconductor substrate but also a semiconductor layer formed on the substrate.

According to the present invention, as described above, the distance between the source / drain regions is provided by providing the channel region formed between the pair of source / drain regions and having a band gap larger than that of the material forming the semiconductor substrate. Even if is reduced, it is possible to effectively prevent a leak current from flowing between the source / drain regions. Thereby, the length of the channel region can be shortened. As a result, further miniaturization can be achieved, and higher integration can be achieved.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the channel region contains atoms whose band gap is larger than that of the element forming the semiconductor substrate by combining with the element forming the semiconductor substrate. Is formed by introducing into. According to this structure, it is possible to easily form the channel region having a band gap larger than that of the element forming the semiconductor substrate. Also, if oxygen is introduced by using an ion implantation method or the like, the channel region can be easily formed in a narrow range, so that the length of the channel can be easily shortened.

According to a third aspect of the present invention, in the structure of the second aspect, the semiconductor substrate includes a silicon substrate, and the atoms introduced into the silicon substrate include oxygen. According to this structure, it is possible to easily form the channel region having a band gap larger than that of silicon forming the silicon substrate.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the channel region includes a SiOx (0≤x≤2) region having a band gap larger than that of the silicon substrate, and one of the source / drain regions is included. , The conduction band of the channel region, and the conduction band of the other source / drain region are smoothly connected. According to this structure, even if the bandgap of the channel region has a region larger than that of the silicon substrate, the size of the bandgap changes smoothly, so that electrons do not tunnel through the barrier, From the conduction band of one source / drain region through the conduction band of the channel region to the other source / drain region
Reach the conduction band in the drain region. As a result, it can be used on the same principle as the conventional field effect transistor.

A semiconductor device according to claim 5 is the semiconductor device according to claim 1.
1 to 4, the pair of source / drain regions are formed at a predetermined distance in the depth direction of the semiconductor substrate, and the channel region is a region through which electrons pass between the pair of source / drain. Has been formed. According to this structure, a vertical field effect transistor can be easily formed. Also, by making it vertical,
Since the thickness direction of the channel region becomes the channel length, it is possible to form a field effect transistor having an extremely short channel length by reducing the thickness of the channel region. Further, since a channel region having a bandgap larger than that of silicon exists between the source / drain regions, even if the source / drain regions are very close to each other, a leak current is prevented from flowing between the source / drain regions. Can be prevented.

A semiconductor device according to a sixth aspect is the semiconductor device according to the first aspect.
In any one of the configurations 4), the pair of source / drain regions are formed at a predetermined interval in a direction along the surface of the semiconductor substrate, and the channel region is a region through which electrons between the pair of source / drain pass. Is formed in. With this structure, a lateral (planar) transistor can be easily formed. Further, between the source / drain regions, there is a channel region having a bandgap larger than that of silicon, or a region slightly below the channel region is a region having a large bandgap. Even if it becomes very close, it is possible to prevent a leak current from flowing between the source / drain regions.

A semiconductor device according to claim 7 is the semiconductor device according to claim 1.
In any one of the configurations 1 to 6, a gate electrode formed on the channel region via an insulating film having a bandgap larger than that of the channel region is further provided. According to this structure, it is possible to prevent charge transfer (leakage current) from occurring between the channel region and the gate electrode even when a voltage is applied to the gate electrode. Also,
By controlling the voltage applied to the gate electrode, the amount of electron current passing through the conduction band of the channel region can be easily controlled.

According to another aspect of the semiconductor device of the present invention, a pair of source / drain regions formed on the semiconductor substrate and atoms, which have a band gap larger than that of the element by combining with the elements forming the semiconductor substrate, are introduced into the semiconductor substrate. And a floating gate formed through an insulating film having a bandgap larger than that of the channel region with respect to the channel region.
The conduction band of the one source / drain region, the conduction band of the channel region, and the conduction band of the other source / drain region are smoothly connected.

In the eighth aspect, as described above, a channel formed by introducing into the semiconductor substrate atoms that have a band gap larger than that of the element forming the semiconductor substrate by combining with the element forming the semiconductor substrate. By providing the region, even if the distance between the source / drain regions of the memory cell transistor is reduced, it is possible to effectively prevent the generation of the leak current between the source / drain regions. As a result, the length of the channel region can be made extremely short. Further, by providing the floating gate to the channel region through an insulating film having a bandgap larger than that of the channel region, even when the potential of the floating gate is increased through electrostatic coupling during a read operation. It is possible to prevent charge transfer (leakage current) from occurring between the channel region and the floating gate.

Further, in the present invention, the bandgap of the channel region is formed by smoothly connecting the conduction band of one source / drain region, the conduction band of the channel region, and the conduction band of the other source / drain region. Even if there is a larger area than the silicon substrate in the same way as the memory cell transistor of the conventional flash memory,
It is possible to reach from the conduction band of one source / drain region to the conduction band of the other source / drain region through the conduction band of the channel region without tunneling through the barrier.

According to a ninth aspect of the semiconductor device, a pair of source / drain regions formed on the semiconductor substrate, a floating gate formed on a channel region located between the pair of source / drain regions, and a floating gate are provided. And a control gate formed so as to face each other with the tunnel insulating film interposed therebetween. Then, at the interface on the floating gate side between the floating gate and the control gate, by introducing an atom having a band gap larger than that of the element forming the floating gate by combining with the element forming the floating gate,
Control was performed so that the band gap smoothly increased from the floating gate to the control gate.

In the ninth aspect, as described above, by introducing the atoms having a large bandgap into the floating gate as described above, the bandgap smoothly increases from the floating gate to the control gate. By controlling, by applying a low voltage of about 3V to 5V between the floating gate and the control gate during the erase operation,
Electrons can be easily extracted from the floating gate toward the control gate. As a result, the erase operation can be performed at a low voltage.

According to a tenth aspect of the present invention, in the semiconductor device according to the ninth aspect, the floating gate and the control gate include silicon, and the floating gate and the control gate are bonded to silicon at the interface on the floating gate side. By introducing oxygen whose band gap is larger than that of silicon, the composition ratio of Si and O is set so that the band gap smoothly increases from the floating gate to the control gate. same state as Si, control gate side controls the state or substantially close to SiO ₂ in the same state as SiO ₂ in. According to this structure, it is possible to easily increase the band gap smoothly from the floating gate to the control gate.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a semiconductor device (lateral FET) according to a first embodiment of the present invention. Further, FIG. 2 is a schematic diagram for explaining the band gap in the horizontal direction in the semiconductor device of the first embodiment, and FIGS. 3 and 4 show the band gap in the vertical direction in the semiconductor device of the first embodiment. It is a schematic diagram for explaining.

The semiconductor device of the first embodiment will be described below with reference to FIGS. In the first embodiment, the source region 2 and the drain region 3 are formed on the surface of the silicon substrate 1 at a predetermined interval. Also,
A channel region 4 is formed between the source region 2 and the drain region 3. A gate electrode 6 made of a polysilicon film is formed on the channel region 4 via a gate insulating film 5. A sidewall insulating film 7 is formed on the side surface of the gate electrode 6. The silicon substrate 1 is an example of the “semiconductor substrate” in the present invention. Also,
The source region 2 and the drain region 3 are examples of the “source / drain region” in the present invention. In addition, the gate insulating film 5
Are examples of the "insulating film" of the present invention.

Here, in the first embodiment, oxygen (O) is implanted into the channel region 4, as described later. By implanting oxygen (O) into the silicon substrate 1 in this way, the oxygen (O) and silicon (Si) are bonded, so that the channel region 4 is formed from the source region 2 and the drain region 3 made of silicon. Also has a larger band gap. This state is shown in FIG. That is, in the channel region 4, a SiOx region (0 ≦ x ≦ 2) having a band gap larger than that of silicon (Si) forming the source region 2 and the drain region 3 is formed. In addition, the conduction band of the source region 2 and the channel region 4
And the conduction band of the drain region 3 are formed so as to be smoothly connected. That is, the interface between the source region 2 and the drain region 3 of the channel region 4 is in a state similar to that of Si, and the central portion of the channel region 4 is S
It is configured to be in a state close to iO ₂ , a state substantially similar to SiO ₂ , or a state in which the band gap is larger than Si.

Further, the silicon substrate 1, the channel region 4,
The band gaps in the vertical direction of the gate insulating film 5 and the gate electrode 6 are as shown in FIG. 3 or 4. That is, the conduction band of the silicon substrate 1 and the conduction band of the channel region 4 are smoothly connected. On the other hand, a gate insulating film 5 made of a SiO ₂ film having a high band gap is formed between the channel region 4 and the gate electrode 6.

In the first embodiment, as described above, by providing the channel region 4 having a bandgap larger than that of silicon between the source region 2 and the drain region 3 made of silicon, the source region 2 and the drain region 3 are separated from each other. Even if the distance is shortened, it is possible to effectively prevent a leak current from flowing between the source region 2 and the drain region 3. Thereby, the length of the channel region 4 can be shortened. Specifically, the channel region 4 has a patterning limit minimum dimension (currently 50 nm to
It can be formed with a thickness of about 100 nm. As a result, further miniaturization can be achieved, and higher integration can be achieved.

In the first embodiment, the conduction band of the source region 2, the conduction band of the channel region 4 and the conduction band of the drain region 3 are smoothly connected to each other, so that the channel region 4 can be formed smoothly.
Even if there is a region larger than the silicon substrate 1 in the band gap of, the electrons pass through the conduction band of the source region 2 and the conduction band of the drain region 3 without tunneling through the barrier. Can be reached. Thereby, it can be used in the same principle as the conventional FET.

Further, in the first embodiment, the channel region 4
By forming the gate electrode 6 on the gate insulating film 5 having a band gap larger than that of the channel region 4, even when voltage is applied to the gate electrode 6, the channel region 4 and the gate electrode 6 are separated from each other. It is possible to prevent charge transfer (leakage current) from occurring between them. Further, by controlling the voltage applied to the gate electrode 6, the amount of electron current passing through the conduction band of the channel region 4 can be easily controlled.

5 to 8 are sectional views for explaining the manufacturing process of the semiconductor device (lateral FET) of the first embodiment shown in FIG. Hereinafter, the method for manufacturing the semiconductor device of the first embodiment will be described with reference to FIGS. 1 and 5 to 8.

First, as shown in FIG. 5, the silicon substrate 1
To cover the region where the upper channel region 4 is not formed,
The SiN film 8 having a thickness of about 100 nm is formed. The width of the region where the SiN film 8 is not formed (width of the region where the channel region is formed) is about 100 nm.

Next, as shown in FIG. 6, oxygen (O) is ion-implanted into the surface of the silicon substrate 1 using the SiN film 8 as a mask. This oxygen ion implantation is performed under the conditions of implantation energy: about 2 keV and implantation amount: about 5 × 10 ¹⁶ cm ^-2 . As a result, the injected oxygen (O) and silicon (Si) forming the silicon substrate 1 are bonded to each other, so that SiO having a larger band gap than silicon is formed.
A channel region 4 including an x (0 ≦ x ≦ 2) region (see FIG. 2) is formed.

Next, as shown in FIG. 7, the channel region 4
Approximately 3 nm by oxidizing the exposed surface on
After forming the gate insulating film 5 made of a SiO ₂ film having a thickness of, a polysilicon film (not shown) having a thickness of about 200 nm is deposited on the entire surface. Then, CMP (Ch
mechanical Mechanical Polish
ng) method or etch back method is used to remove the portion of the polysilicon film located on the SiN film 8 to form the gate electrode 6 made of the polysilicon film as shown in FIG. After that, the SiN film 8 is removed to obtain a shape as shown in FIG.

Finally, as shown in FIG. 1, after the impurity is injected into the silicon substrate 1 at a low concentration, the sidewall insulating film 7 is formed, and then the impurity of high concentration is injected to form the LDD structure. Forming a source region 2 and a drain region 3. In this way, the semiconductor device (lateral FET) of the first embodiment is formed.

(Second Embodiment) FIG. 9 is a sectional view showing a semiconductor device (lateral FET) according to a second embodiment of the present invention. The semiconductor device according to the second embodiment will be described below with reference to FIG.

In the semiconductor device according to the second embodiment,
A source region 12 and a drain region 13 are formed on the surface of the convex portion of the silicon substrate 11. The silicon substrate 1
1 is an example of the "semiconductor substrate" of the present invention. The source region 12 and the drain region 13 are examples of the “source / drain region” in the present invention.

On the bottom surface of the concave portion of the silicon substrate 11,
SiOx (0 ≦, which has a larger bandgap than silicon)
A channel region 14 of x ≦ 2) is formed.
The concave portion of the silicon substrate 11 has a depth of about 100 nm from the upper surface of the convex portion of the silicon substrate 11. A gate electrode 16 made of a polysilicon film is formed on the channel region 14 via a gate insulating film 15 made of a silicon oxide film (SiO ₂ film) having a thickness of about 3 nm. The gate insulating film 15 is an example of the "insulating film" in the present invention. A SiN film 17 having a thickness of about 50 nm is formed on the source region 12 and the drain region 13.
Are formed. A side wall insulating film 18 having a maximum thickness of about 20 nm is formed between the gate electrode 16 and the source region 12 and the drain region 13.

Here, the channel region 14 in the second embodiment also has band gaps similar to the band gaps in the horizontal and vertical directions shown in FIGS. 2 and 3 (FIG. 4). That is, in the lateral band gap, the conduction band of the source region 12, the conduction band of the channel region 14, and the conduction band of the drain region 13 are smoothly connected. Further, in the vertical band gap, the conduction band of the silicon substrate 11 and the conduction band of the channel region 14 are smoothly connected. On the other hand, between the channel region 14 and the gate electrode 16, a rod-shaped gate insulating film 15 made of a SiO ₂ film having a high band gap is formed.

Also in the second embodiment, as in the above-described first embodiment, the source region 12 and the drain region 13 made of silicon are provided with the channel region 14 having a band gap larger than that of silicon, so that the source is formed. Even if the distance between the region 12 and the drain region 13 becomes small, the source region 12 and the drain region 13
It is possible to effectively prevent a leak current from flowing between and. Thereby, the length of the channel region 14 can be shortened. Specifically, the length of the channel region 14 is set to the minimum patterning pattern size (currently 50 nm).
To about 100 nm).
As a result, further miniaturization can be achieved, and higher integration can be achieved.

Further, in the second embodiment, similarly to the first embodiment, the conduction band of the source region 12, the conduction band of the channel region 14 and the conduction band of the drain region 13 are smoothly connected to each other, so that SiOx (0≤0.ltoreq. Even if there is a region larger than the silicon substrate 11 in the bandgap of the channel region 14 composed of x ≦ 2), the electrons do not tunnel through the barrier and the conduction band of the source region 12 to the conduction band of the channel region 14 does not pass. To reach the conduction band of the drain region 13. Thereby, it can be used in the same principle as the conventional FET.

Further, in the second embodiment, the channel region 1
4, the gate electrode 16 is formed via the gate insulating film 15 made of a SiO ₂ film having a band gap larger than that of the channel region 14, so that the channel region 14 can be formed even when a voltage is applied to the gate electrode 16. It is possible to prevent electric field movement (leakage current) between the gate electrode 16 and the gate electrode 16. Further, by controlling the voltage applied to the gate electrode 16, the amount of electron current passing through the conduction band of the channel region 14 can be easily controlled.

FIG. 10 and FIG. 11 are the second shown in FIG.
FIG. 6 is a cross-sectional view for illustrating the manufacturing process for the semiconductor device of the embodiment. Next, with reference to FIGS. 9 to 11, a method for manufacturing the semiconductor device of the second embodiment will be described.

First, as shown in FIG. 10, by implanting impurities into the entire surface of the silicon substrate 11,
Impurity regions 20 to be the source region 12 and the drain region 13 are formed. Then, the SiN film 17 is formed so as to cover regions of the impurity region 20 which will be the source region 12 and the drain region 13. The width of the opening of the SiN film 17 is the minimum dimension of patterning (50 nm to 10 nm).
0 nm).

Then, by using the SiN film 17 as a mask, the silicon substrate 11 is etched by about 100 nm to form a recess as shown in FIG. Then, oxygen (O) is ion-implanted into the bottom surface of the recess under the conditions of an implantation energy of about 2 keV and an implantation amount of about 5 × 10 ¹⁶ cm ⁻² , whereby silicon and oxygen are bonded to each other, and S with wider band gap
A channel region 14 including an iOx (0 ≦ x ≦ 2) region is formed.

After that, as shown in FIG. 9, a sidewall insulating film 18 is formed on the inner surface of the source region 12, the drain region 13 and the SiN film 17. Then, by oxidizing the surface of the silicon substrate 11, about 3n
A gate insulating film 15 having a thickness of m is formed. Then, a gate electrode 16 made of a polysilicon film is formed by embedding a polysilicon film in the opening. In this way, the semiconductor device (lateral FET) of the second embodiment is formed.

(Third Embodiment) FIG. 12 shows a third embodiment of the present invention.
3 is a cross-sectional view showing a memory cell of the semiconductor device (stacked gate type flash memory) according to the embodiment. FIG. FIG. 13 is a cross-sectional view for explaining the method of manufacturing the semiconductor device of the third embodiment shown in FIG. 14 is shown in FIG.
FIG. 7 is a schematic diagram showing a lateral band gap in the semiconductor device of the third embodiment shown in FIG. 15 and 16 are schematic diagrams showing the band gap in the vertical direction in the semiconductor device of the third embodiment.

First, the structure of the memory cell of the semiconductor device (flash memory) of the third embodiment will be described with reference to FIG. The third embodiment basically shows an example of manufacturing a memory cell of a stacked gate type flash memory by using the structure of the semiconductor device of the second embodiment shown in FIG. Specifically, the source region 22 and the drain region 2 are formed on the convex surface of the silicon substrate 21.
And 3 are formed. The silicon substrate 21 is an example of the “semiconductor substrate” in the present invention. The source region 22 and the drain region 23 are examples of the "source / drain region" in the present invention. On the bottom surface of the concave portion of the silicon substrate 21, SiOx (0 having a band gap larger than those of the source region 22 and the drain region 23 made of silicon is formed.
A channel region 24 formed of a region ≦ x ≦ 2) is formed.

On the channel region 24, about 8 nm
A floating gate 26 made of a polysilicon film is formed via a gate insulating film 25 made of a SiO ₂ film having a thickness of 1. The gate insulating film 25 is an example of the “insulating film” in the present invention. A SiN film 27 having a thickness of about 50 nm is formed on the source region 22 and the drain region 23.
Are formed. In addition, the floating gate 26 has about 6
control gate 3 made of a polysilicon film via an insulating film 29 made of a SiO ₂ film having a thickness of nm to about 8 nm.
0 is formed.

Also in the third embodiment, as shown in FIG. 14, the conduction band of the source region 22 and the channel region 24.
The band gap of the channel region 24 made of SiOx (0 ≦ x ≦ 2) is controlled so that the conduction band of the drain region 23 and the conduction band of the drain region 23 are smoothly connected.

Further, the silicon substrate 21 and the channel region 2
4, the vertical band gaps of the gate insulating film 25 and the floating gate 26 are as shown in FIG. 15 or FIG. That is, SiO having a high-height barrier between the channel region 24 and the floating gate 26.
_A gate insulating film 25 composed of _two films is formed.

As the manufacturing process of the third embodiment, the process up to forming the floating gate 26 is the same as the manufacturing process of the second embodiment except for the thickness (about 8 nm) of the gate insulating film 25. . Among these, in the oxygen implantation step, as shown in FIG. 13, oxygen (O) is implanted into the bottom surface of the concave portion of the silicon substrate 21 under the conditions of implantation energy: about 2 keV and implantation amount: about 5 × 10 ¹⁶ cm ⁻² . Ion implantation.
As a result, the channel region 24 made of SiOx (0 ≦ x ≦ 2) having a band gap as shown in FIGS. 14, 15 and 16 is formed.

In the third embodiment, as described above, the source region 22 of the memory cell transistor is provided by providing the channel region 24 having a larger band gap than the source region 22 and the drain region 23 made of silicon.
Even if the distance between the drain region 23 and
It is possible to effectively prevent a leak current from flowing between the source region 22 and the drain region 23. Thereby, the length of the channel region can be shortened. Specifically, the length of the channel region 24 can be reduced to the critical minimum dimension of patterning (currently about 50 nm to 100 nm). As a result, further miniaturization can be achieved, and higher integration can be achieved.

A gate insulating film 25 having a band gap larger than that of the channel region 24 is formed on the channel region 24.
Even if the potential of the floating gate 26 is increased from the control gate 30 via the electrostatic coupling during the read operation by forming the floating gate 26 via
It is possible to prevent charge transfer (leakage current) from occurring between the channel region 24 and the floating gate 26.

Further, in the third embodiment, the source region 22
Conduction band and channel region 24 conduction band and drain region 2
Even if the band gap of the channel region 24 is larger than that of the silicon substrate 21, electrons are tunneled through the barrier like the memory cell transistor of the conventional flash memory by smoothly connecting the conduction band of No. 3 to the conduction band of No. 3. Without passing through, the conduction band of the source region 22 can reach the conduction band of the drain region 23 through the conduction band of the channel region 24.

(Fourth Embodiment) FIG. 17 shows a fourth embodiment of the present invention.
3 is a cross-sectional view showing a memory cell of the semiconductor device (split gate type flash memory) according to the embodiment. FIG. The fourth embodiment shows an example in which oxygen is injected into the interface on the floating gate side between the floating gate electrode and the control gate electrode in the split gate type flash memory. The details will be described below.

First, in the memory cell of the semiconductor device (flash memory) of the fourth embodiment, the source region 42 and the drain region 43 are formed on the surface of the silicon substrate 41 with a predetermined space therebetween. The silicon substrate 41
Are examples of the "semiconductor substrate" of the present invention. The source region 42 and the drain region 43 are examples of the “source / drain region” in the present invention. On the silicon substrate 41 on the source region 42 side between the source region 42 and the drain region 43, a floating gate 46 made of a polysilicon film is formed via a gate insulating film 45 made of a SiO ₂ film. In a predetermined area on the upper surface of the floating gate 46, S
An iO ₂ film 50 is formed. In addition, the floating gate 46
A control gate 48 made of a polysilicon film is arranged so as to face the right end portion of the via a tunnel insulating film 49. The gate insulating film 4 is formed under the control gate 48.
7 are formed.

A source electrode 51 is formed on the source region 42. S is formed on the upper surface of the source electrode 51.
An iO ₂ film 52 is formed. In addition, the source electrode 51
An insulating film 53 made of a SiO ₂ film is formed between the floating gate 46 and the floating gate 46.

Here, in the semiconductor device according to the fourth embodiment, the oxygen implantation region 46a is formed at the end of the floating gate 46 on the side facing the control gate 48. The oxygen implantation region 46a is provided in the floating gate 46 and the control gate 4.
It is made of SiOx (0 ≦ x ≦ 2) whose bandgap is larger than that of silicon (polysilicon) which forms No. 8. The band gap of the oxygen implantation region 46a is in a state as shown in FIG. 18, for example. That is, from the floating gate 46 made of polysilicon (Si) to the control gate 48 made of polysilicon, an oxygen implantation region 46a having a large band gap is formed.
The end of the oxygen implantation region 46a where the band gap is increased is connected to the tunnel insulating film 49 made of a SiO ₂ film.

When a positive voltage is applied to the control gate 48 in the state shown in FIG. 18, electrons are easily transferred from the floating gate 46 to the control gate 48 by the state shown in FIG.
Can be moved to.

In addition to the bandgap state shown in FIG. 18, the bandgap shown in FIG. 20 or the bandgap shown in FIG. 22 may be used. In this case, when a positive voltage is applied to the control gate 48, the state shown in FIG. 20 becomes the state shown in FIG. 21, and the state shown in FIG. 22 makes the state shown in FIG. become. In either case, electrons are transferred from the floating gate 46 to the control gate 48.
Can be easily moved to. Here, the structure of the band gap of the comparative example (conventional) as shown in FIG. 24,
The structure is compared with the bandgap structure of the fourth embodiment shown in FIG. If the distances D are the same, then FIG.
In the bandgap state of the fourth embodiment shown in FIG. 25, electrons are moved from the floating gate to the control gate at a lower voltage than in the bandgap state of the comparative example (conventional) shown in FIG. be able to.

In the fourth embodiment, as described above, by providing the oxygen-implanted region 46a such that the band gap smoothly increases from the floating gate 46 to the control gate 48, the floating gate 46 and Electrons can be easily extracted from the floating gate 46 toward the control gate 48 by simply applying a low voltage of about 3 V to 5 V between the control gate 48 and the control gate 48. As a result, the erase operation can be performed at a low voltage.

26 and 27 are cross-sectional views for explaining the manufacturing process of the semiconductor device of the fourth embodiment shown in FIG. Next, with reference to FIGS. 17, 26 and 27, a manufacturing process of the semiconductor device of the fourth embodiment will be described.

First, as shown in FIG. 26, the source region 42 is formed on the surface of the silicon substrate 41. Further, a polysilicon film 46b is formed in a predetermined region on the silicon substrate 41 with a gate insulating film 45 made of a SiO ₂ film interposed therebetween. After forming a SiN film (not shown) on the polysilicon film 46b, the SiN film and the polysilicon film 46b are formed.
A side wall insulating film 53 is formed on the side surface of the. Then, after forming the source electrode 51 so as to be connected to the source region 42, a silicon oxide film (SiO ₂ film) 52 is formed on the upper surface of the source electrode 51.

After removing the SiN film (not shown) on the polysilicon film 46b, a SiO ₂ film 50 is formed on a predetermined region of the polysilicon film 46b. Using the SiO ₂ film 50 as a mask, oxygen (O) is added to the polysilicon film 46b.
Ion implantation is performed with a low energy of 2 keV or less and an implantation dose of 5 × 10 ¹⁶ cm ⁻² . As a result, the polysilicon film 46
An oxygen implantation region 46a is formed on the surface of b. In the oxygen-implanted region 46a, the implanted oxygen (O) is combined with the silicon (Si) of the polysilicon film 46b, so that the oxygen-implanted region 46a has a band gap larger than that of silicon. Specifically, the closer to the surface of the polysilicon film 46b, the larger the band gap.

Next, as shown in FIG. 27, the SiO ₂ film 5 is formed.
Sidewall spacer 54 made of SiN on the side surface of 0
And the sidewall spacer 54 is used as a mask to etch the lower polysilicon film 46b to form the floating gate 46 made of a polysilicon film having a shape as shown in FIG. Of the upper surface of the floating gate 46, the sidewall spacer 54
An oxygen implantation region 46a is formed in the region located below.

Then, after removing the sidewall spacers 54, a SiO ₂ film (not shown) and a polysilicon film (not shown) are formed, and then the polysilicon film and the SiO ₂ film are anisotropically etched. As a result, the control gate 48 made of a polysilicon film, the tunnel insulating film 49 and the gate insulating film 47 made of a SiO ₂ film are formed as shown in FIG. As a result, the semiconductor device (split gate type flash memory) of the fourth embodiment is formed.

(Fifth Embodiment) FIG. 28 shows a fifth embodiment of the present invention.
29 is a plan view showing the semiconductor device (vertical FET) according to the embodiment, FIG. 29 is a cross-sectional view taken along line 100-100 of FIG. 28, and FIG. 30 is taken along line 200-200 of FIG. FIG. 28 to 30, the fifth embodiment shows an example in which the present invention is applied to a vertical FET.

That is, in the fifth embodiment, the source / drain regions 62 are formed in the region of a predetermined depth from the surface of the silicon substrate 61 so as to extend in the lateral direction. Further, the surface of the silicon substrate 61 is formed in an uneven shape. On the surface of the convex portion of the silicon substrate 61, SiOx (0 ≦ x) having a band gap larger than that of silicon by being injected with oxygen and bonded to silicon.
A channel region 63 including a region of ≦ 2) is formed. The channel region 63 is the source / drain region 6
It is formed so as to extend in a direction orthogonal to 2. A source / polysilicon film is formed on the channel region 63.
The drain region 64 is formed so as to extend in the same direction as the channel region. The source / drain region 64
A silicide film 65 is formed on the surface of the.

The silicon substrate 61 is an example of the "semiconductor substrate" in the present invention. The source / drain regions 62 and 64 are examples of the “source / drain region” in the present invention.

In the recess of the silicon substrate 61, a channel region 63 and a source / drain region 64 are formed as S.
A gate electrode 67 made of a polysilicon film is formed so as to surround the gate insulating film 66 made of an iO ₂ film. The silicide film 6 is formed on the upper surface of the gate electrode 67.
8 is formed. Further, as shown in FIG. 30, an insulating film 69 made of a SiN film is formed on a part of the upper surface of the source / drain region 64. And the gate electrode 6
A contact plug 70 is formed so as to connect to 7. Further, source / drain contact portions 72 (see FIG. 28) are provided so as to be connected to the source / drain regions 62.

The relationship between the oxygen (O) concentration and the depth in the channel region 63 is shown in FIG. A channel region 63 having such an oxygen concentration distribution, a source / drain region 62, and a source / drain region 64.
The bandgap in the vertical direction is similar to the bandgap between the source / drain regions in the horizontal direction of the first embodiment shown in FIG. That is, the source / drain region 62
So that the conduction band of the channel region 63, the conduction band of the channel region 63, and the conduction band of the source / drain region 64 are smoothly connected.
The value of x in the channel region 63 made of iOx is controlled.

In the fifth embodiment, as described above, between the pair of source / drain regions 62 and 64, the channel region 63 having a larger band gap than the silicon substrate 61 is formed.
By providing, even if the distance between the source / drain regions 62 and 64 becomes small, it is possible to effectively prevent a leak current from flowing between the source / drain regions 62 and 64. Thereby, the length of the channel region 63 can be shortened. Moreover, since the channel length in the thickness direction of the channel region 63 becomes the channel length by making it vertical, the FET having an extremely short channel length can be formed by reducing the thickness of the channel region 63. That is, if the oxygen implantation conditions are controlled, a short channel region 63 of about 10 nm can be formed.

Further, in the fifth embodiment, the conduction band of the source / drain region 62, the conduction band of the channel region 63 and the conduction band of the source / drain region 64 are smoothly connected to each other, so that the conduction band of the channel region 63 is reduced. Even if the bandgap has a region larger than that of the silicon substrate 61, the electrons do not tunnel through the barrier but pass through the conduction band of the source / drain region 62 and the conduction band of the channel region 63 to cause the source / drain region 64. Can reach the conduction band of. Thereby, it can be used in the same principle as the conventional FET.

(Sixth Embodiment) FIG. 32 shows a sixth embodiment of the present invention.
33 is a plan view showing a semiconductor device (vertical FET) according to an embodiment, FIG. 33 is a cross-sectional view taken along the line 300-300 of FIG. 32, and FIG. 34 is taken along the line 400-400 of FIG. FIG. 32 to 34, in the sixth embodiment, in the fifth embodiment described above,
An example in which the gate electrode is omitted is shown.

That is, in the sixth embodiment, the source / drain regions 82 extending in the lateral direction are formed on the silicon substrate 81. Moreover, the surface of the silicon substrate 81 is formed in an uneven shape. On the surface of the convex portion of the silicon substrate 81, SiOx (0
A channel region 83 of ≦ x ≦ 2) is formed so as to extend in a direction orthogonal to the source / drain regions 82. Source / drain regions 84 are formed on channel region 83 so as to extend in the same direction as channel region 83. A silicide film 85 is formed on the source / drain regions 84. An insulating film 86 is embedded between the adjacent source / drain regions 84.

The silicon substrate 81 is an example of the "semiconductor substrate" in the present invention. The source / drain regions 82 and 84 are examples of the “source / drain region” in the present invention.

Further, as shown in FIG. 34, to connect to the silicide film 85 on the source / drain regions 84,
A contact plug 87 is formed. In addition, FIG.
As shown in FIG.
Source / drain contact portion 8 so as to be connected to
8 is formed.

Also in the sixth embodiment, as in the fifth embodiment, the source / drain regions 8 are arranged in the vertical direction.
The channel region 83 located between 2 and 84 has a bandgap similar to the bandgap of the first embodiment shown in FIG. That is, S is such that the conduction band of the source / drain region 82, the conduction band of the channel region 83 and the conduction band of the source / drain region 84 are smoothly connected.
The value of x in the channel region 83 composed of iOx (0 ≦ x ≦ 2) is controlled.

Here, unlike the fifth embodiment, the sixth embodiment does not have a gate electrode. In this case, the source / source connected to the source / drain region 82
By selecting the drain line and the source / drain line connected to the source / drain region 84 to give a potential difference, a current flows between the source / drain regions 82 and 84 at the intersection of the two lines. . In this case, since the entire area of the intersection of the source / drain regions 82 and 84 functions as a current passage region, a large current can be easily passed. As a result, it is possible to easily increase the speed of the device.

It should be understood that the embodiments disclosed this time are exemplifications in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and includes meaning equivalent to the scope of claims for patent and all modifications within the scope.

For example, in the above-described embodiment, an example of forming a channel region having a bandgap larger than that of silicon by implanting oxygen into the silicon substrate has been described, but the present invention is not limited to this, and nitrogen is not formed in the silicon substrate. Can also be implanted to form a channel region having a bandgap larger than that of silicon. Further, if a semiconductor substrate made of a material other than silicon is introduced with an atom having a band gap larger than that of the material constituting the semiconductor substrate by combining with an element constituting the semiconductor substrate, the same effect can be obtained. Obtainable.

Further, in the fourth embodiment, oxygen is implanted into the surface of the floating gate 46 made of a polysilicon film to form an oxygen implantation region 46a having a larger band gap from the floating gate 46 toward the control gate 48. However, the present invention is not limited to this, and a floating gate made of a material other than silicon (polysilicon) is combined with an element of the constituent material of the floating gate so that the band gap becomes larger than that of the constituent material of the floating gate. You may make it implant such an atom.

Further, in the above embodiment, oxygen was implanted by using a normal ion implantation method, but the present invention is not limited to this, and a cluster ion beam or the like may be used. Further, instead of implanting oxygen directly, to form the SiO ₂ film, by implanting ions from above the SiO ₂ film, it may be injected recoil atoms from SiO ₂ film.

[0096]

As described above, according to the present invention, even if the distance between the source / drain regions becomes small, it is possible to effectively prevent the generation of the leak current. The length can be shortened.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device (lateral FET) according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a lateral band gap in the semiconductor device of the first embodiment shown in FIG.

FIG. 3 is a schematic diagram showing a vertical band gap in the semiconductor device of the first embodiment shown in FIG.

FIG. 4 is a schematic diagram showing a band gap in a vertical direction in the semiconductor device of the first embodiment shown in FIG.

FIG. 5 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

6A and 6B are cross-sectional views for explaining the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

FIG. 7 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the first embodiment shown in FIG.

FIG. 8 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the first embodiment shown in FIG.

FIG. 9 is a sectional view showing a semiconductor device (lateral FET) according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the second embodiment shown in FIG.

FIG. 11 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the second embodiment shown in FIG.

FIG. 12 is a sectional view showing a semiconductor device (flash memory) according to a third embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the third embodiment shown in FIG.

FIG. 14 is a schematic diagram showing a lateral band gap in the semiconductor device of the third embodiment shown in FIG.

FIG. 15 is a schematic diagram showing a vertical band gap in the semiconductor device of the third embodiment shown in FIG.

16 is a schematic diagram showing a band gap in the vertical direction in the semiconductor device of the third embodiment shown in FIG.

FIG. 17 is a sectional view showing a semiconductor device (flash memory) according to a fourth embodiment of the present invention.

FIG. 18 is a schematic diagram showing an example of a bandgap between a floating gate and a control gate of the semiconductor device according to the fourth embodiment shown in FIG.

19 is a schematic diagram showing the state of the band gap when a voltage is applied between the floating gate and the control gate from the state of the band gap shown in FIG.

20 is a schematic diagram showing another example of the band gap between the floating gate and the control gate of the semiconductor device according to the fourth embodiment shown in FIG.

21 is a schematic diagram showing the state of the band gap when a voltage is applied between the floating gate and the control gate from the state of the band gap shown in FIG.

22 is a schematic diagram showing still another example of the band gap between the floating gate and the control gate of the semiconductor device according to the fourth embodiment shown in FIG. 17. FIG.

23 is a schematic diagram showing the state of the band gap when a voltage is applied between the floating gate and the control gate from the state of the band gap shown in FIG.

FIG. 24 is a schematic diagram showing a bandgap according to a comparative example of the fourth embodiment of the present invention.

FIG. 25 is a schematic diagram showing a bandgap according to a fourth embodiment of the present invention.

FIG. 26 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the fourth embodiment shown in FIG.

FIG. 27 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the fourth embodiment shown in FIG.

FIG. 28 is a plan view showing a semiconductor device (vertical FET) according to a fifth embodiment of the present invention.

29 is a sectional view taken along the line 100-100 of the semiconductor device of the fifth embodiment shown in FIG.

30 is a sectional view taken along the line 200-200 of the semiconductor device according to the fifth embodiment shown in FIG.

FIG. 31 is a characteristic diagram showing the relationship between oxygen concentration and depth in the channel region of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 32 is a plan view showing a semiconductor device (vertical FET) according to a sixth embodiment of the present invention.

FIG. 33 is a sectional view taken along the line 300-300 of the semiconductor device of the sixth embodiment shown in FIG. 32.

34 is a sectional view taken along the line 400-400 of the semiconductor device according to the sixth embodiment shown in FIG. 32.

[Explanation of symbols]

1, 11, 21, 41, 61, 81 Silicon substrate (semiconductor substrate) 2, 12, 22, 42 Source region (source / drain region) 3, 13, 23, 43 Drain region (source / drain region) 4, 14 , 24, 63, 83 Channel regions 5, 15, 25 Gate insulating film (insulating film) 6, 16, 67 Gate electrodes 26, 46 Floating gates 30, 48 Control gates 62, 64, 82, 84 Source / drain regions

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/792 F term (reference) 5F083 EP03 EP15 EP22 EP24 EP25 EP27 ER17 ER22 GA05 GA06 PR10 PR29 PR36 PR40 5F101 BA03 BA12 BA13 BA19 BB02 BB04 BB08 BD12 BE07 BF09 BH09 BH19 5F140 AA18 AA24 AC23 AC32 BA01 BB04 BB13 BB16 BC06 BE07 BF01 BF04 BF43 BF44 BG08 BG36 BG40 BH02 BH05 BH07 BH15 BJ01 BJ08 BK02BK02

Claims (10)

[Claims] 1. A pair of sources / formed on a semiconductor substrate
A semiconductor device comprising: a drain region; and a channel region formed between the pair of source / drain regions and having a band gap larger than that of a material forming the semiconductor substrate. 2. The channel region is formed by introducing into the semiconductor substrate, an atom having a band gap larger than that of an element forming the semiconductor substrate by being combined with an element forming the semiconductor substrate. ,
The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein the semiconductor substrate includes a silicon substrate, and the atoms introduced into the silicon substrate include oxygen. 4. The channel region is made of SiOx (0 ≦ x) having a band gap larger than that of the silicon substrate.
≦ 2) region, wherein the conduction band of the one source / drain region, the conduction band of the channel region, and the conduction band of the other source / drain region are smoothly connected. Semiconductor device. 5. The pair of source / drain regions are formed at a predetermined distance in the depth direction of the semiconductor substrate, and the channel region is a region through which electrons pass between the pair of source / drains. The semiconductor device according to claim 1, which is formed. 6. The pair of source / drain regions are formed at a predetermined interval in a direction along a surface of the semiconductor substrate, and the channel region allows electrons between the pair of source / drain to pass therethrough. The semiconductor device according to claim 1, which is formed in the region. 7. The semiconductor device according to claim 1, further comprising a gate electrode formed on the channel region via an insulating film having a band gap larger than that of the channel region. . 8. A pair of sources / formed on a semiconductor substrate
A drain region; a channel region formed by introducing into the semiconductor substrate atoms that have a bandgap larger than that of an element forming the semiconductor substrate by combining with an element forming the semiconductor substrate; A floating gate formed via an insulating film having a bandgap larger than that of the channel region, the conduction band of the source / drain region on one side, the conduction band of the channel region, and the conduction band on the other side. A semiconductor device in which the conduction bands of the source / drain regions are smoothly connected. 9. A pair of sources / formed on a semiconductor substrate.
A drain region, a floating gate formed on a channel region located between the pair of source / drain regions, and a control gate formed to face the floating gate via a tunnel insulating film. At the interface between the floating gate and the control gate on the side of the floating gate, an atom having a band gap larger than that of the element forming the floating gate is introduced by combining with an element forming the floating gate. By
A semiconductor device in which control is performed so that the band gap smoothly increases from the floating gate toward the control gate. 10. The floating gate and the control gate include silicon, and an interface between the floating gate and the control gate on the side of the floating gate has a band gap larger than that of the silicon by being bonded to the silicon. Is introduced so that the band gap smoothly increases from the floating gate to the control gate, the composition ratio of Si and O is set to be substantially Si on the floating gate side. In the same state, the control gate side is SiO ₂
10. The semiconductor device according to claim 9, wherein the semiconductor device is controlled to a state close to the above or a state substantially similar to SiO ₂ .