JP2003115813A - Fft circuit/ifft circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit, in which an expensive FFT (Fast Fourier transform) circuit/IFFT (inverse Fast Fourier transform) circuit with a high point number can be configured by using a more inexpensive FFT/IFFT circuit with a low point number. SOLUTION: When configuring the IFFT circuit of a point number 2k, after 2k carrier signals to be transformed are divided into two signal streams of even-numbered 1k carriers and odd-numbered 1k carriers, the signals are transformed in order for each signal stream by one IFFT circuit of a point number 1k. In the transformed even-numbered signal stream, the same signal is repeated twice and made into a first 2k point signal and in the transformed odd-numbered signal stream, the same signal is repeated twice and made into a second 2k point signal, in which modulation to once rotate the signal at 2k points on a complex space is applied. These first and second 2k point signals are added and outputted as a signal stream executing the IFFT of the point number 2k. This circuit can be composed of only the more inexpensive IFFT circuit of the point number 1k, a simple modulation circuit, a memory and an adder circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to configurations of an FFT circuit (Fourier transform circuit) and an IFFT circuit (inverse Fourier transform circuit).

[0002]

2. Description of the Related Art In recent years, in the field of wireless devices, an OFDM method (Ort method) has been used as a modulation method that is resistant to multipath fading.
Hogonal Frequency Division Multiplexing) has been attracting attention, and many applied researches are being made in fields such as next-generation television broadcasting, FPU, and wireless LAN in countries such as Europe and Japan. Of this, U
The HF band terrestrial digital broadcasting system is described in the Institute of Image Information and Television Engineers, 1998 Vol. 52, No. 1
1 is described in detail. In this OFDM type transmission apparatus, an IFFT (inverse Fourier transform) circuit is indispensable in the transmission apparatus, and an FFT (Fourier transform) circuit is indispensable in the reception apparatus. This FFT circuit is a complex number signal sequence with the number of points N defined on the time axis, zin (0), zin
(1), ..., Zin (N-1) are Fourier-transformed, and the calculated signal sequence Zou on the frequency axis is calculated.
This is a circuit that outputs t. Zout (k) = Σ [zin (n) · exp (−j · 2π · k · n / N)] (where n = 0 to N−1) (1) Further, the IFFT circuit is Conversely, a complex number signal sequence Zin (0), Zin (1), with N points defined on the frequency axis,
.., Zin (N-1) is inverse Fourier transformed,
This is a circuit that outputs a calculated signal sequence zout of a complex number on the time axis. zout (n) = Σ [Zin (k) · exp (+ j · 2π · k · n / N)] (however, k = 0 to N−1) (2) Here, on the frequency axis A defined complex number signal sequence is represented by an uppercase Z as an initial letter, and a complex number signal sequence defined on the time axis is represented by a lowercase z as an initial letter. All signals used in the following description are complex signals.
Generally, FFT and IFFT are used as a calculation method capable of performing these calculations at high speed. Regarding this calculation method, for example, Sagawa et al., "Fast Fourier Transform and Its Application"
Shokodo, Arimoto "Digital processing of signals and images" As explained in many general textbooks including industrial books,
The description is omitted.

Next-generation television broadcasting, FPU, wireless LAN
In many cases, the number of points is 1k (1024) or 2k in an OFDM wireless device under development in the field of
(2048), depending on the case, 4k (4096),
An 8K (8192) FFT circuit and an IFFT circuit are required. In these devices, a commercially available dedicated IC is usually used as the FFT / IFFT circuit, or an IC such as a gate array is independently developed and used. When developing an IC using a gate array or the like, the development cost is high, so it is necessary to reduce the number of types of development.
On the other hand, the same function as that of the FFT / IFFT circuit having a small number of points can be realized by thinning out the signal input to and output from the FFT / IFFT circuit having a large number of points. Alternatively, an FFT / IFFT circuit having a small number of points can be configured and realized by using only a part of the FFT / IFFT circuit having a large number of points. Therefore, conventionally, an FFT / IFFT circuit having a large number of points has been developed, and an FFT / IFFT circuit having a smaller number of points is realized by the above method using the developed FFT / IFFT circuit having a larger number of points. .

[0004]

By the way, FFT / I
The gate scale of the FFT circuit increases almost in proportion to the number N of points. When the gate scale increases, not only the development cost increases sharply, but also the chip area increases and the production yield decreases. Therefore, FF with a large number of points
The T / IFFT circuit has a problem that the unit price of the developed IC becomes high. In addition, when applied to a plurality of products manufactured in small quantities, the number of points required for each product often differs. A FFT / IFFT circuit with a large number of points has been developed, and an FFT / IFT circuit with a small number of points has been developed.
When an FFT circuit is configured and used, there is a problem that the number of points required is small and the price of a product that should be originally low becomes expensive. Especially when it is not necessary to reduce the area of the board to the limit, if an FFT / IFFT circuit with a large number of points can be configured by simply adding a simple multiplication circuit or memory circuit to an FFT / IFFT circuit with a small number of points and a low price Since the product price can be reduced, it is preferable even if the circuit scale increases a little. in this way,
The price of a product requiring a small number of points in the FFT / IFFT circuit can be reduced to a price commensurate with the product. An object of the present invention is to provide a large number of FFT / Is that result in high development costs and unit costs.
An object of the present invention is to provide a circuit that can be configured using an FFT / IFFT circuit having a low number of points, which is cheaper, although the number of points is small.

[0005]

To achieve the above object, the present invention provides an IFFT circuit (inverse Fourier transform circuit) / FFT circuit (Fourier transform circuit) having 2N points, which has 2N points. The even-numbered signal sequence E1 of the number N of points, which is the first signal sequence obtained by separating the input signal sequence of the number 2N of points input to the IFFT circuit / FFT circuit, and the separation Second obtained
An IFFT circuit / FFT circuit with one point N for inputting the odd number signal sequence O1 of the number N of points, which is an input signal of the odd number point which is a signal sequence of, and sequentially outputting IFFT / FFT for each signal sequence And the IFF of the number of points N
Number of points N converted and output by the T circuit / FFT circuit
After conversion, the even-numbered signal train E2 is repeated twice, and the converted even-numbered signal train E4 having the number of points 2N is obtained.
The odd numbered signal sequence O2 after conversion of the number of points N converted by the IFFT circuit / FFT circuit of the number of points N and output is 2
The odd-numbered signal sequence O3 having the number of points 2N obtained by repeating the number of times is added to the signal sequence O4 which is modulated by further rotating the complex space by ± 1 rotation at 2N points, that is, the n-th signal sequence.
The signal at the point is ± 2π × n / (2N) (However, IFFT
The circuit is +, and the FFT circuit is-). The modulated odd-numbered signal sequence O4 having the number of points 2N, which has been subjected to modulation for radian rotation, is input, and the converted even-numbered signal sequence E4 having the number of points 2N and the number of the point number 2N are converted. After modulation, the odd-numbered signal sequence O4 is added for each signal of each point to obtain an IFFT / FF having a number of points of 2N.
An IFFT circuit / FFT circuit having 2N points and an apparatus having the IFFT circuit / FFT circuit, which has an addition circuit for outputting a signal sequence after T.

Further, the present invention is an FFT with 2N points.
Circuit / IFFT circuit, FF having the number of points of 2N
From the 0th point to the (N-1) th point signal sequence F of the input signal sequence of 2N points input to the T circuit / IFFT circuit, and the Nth point of the latter half portion A first adder circuit for adding a signal train B of the number N of points composed of the (2N-1) th point signal for each signal of each point, and a signal train F of the first half portion.
And a signal string -B obtained by inverting the polarity of the signal string B in the latter half portion.
A second adder circuit for adding for each signal of each point,
A signal sequence E2 having the number of points N output from the first adder circuit and a number of points N output from the second adder circuit
Signal train O2 ′ of 2N points is subjected to half rotation modulation at a rate of ± 1 rotation in the complex space (however, − in the FFT circuit, + in the IFFT circuit), that is, the signal of the nth point. Is input to the signal train O2 of the number of points N which is modulated by rotating ± 2π × n / (2N) radians,
A point consisting of an even numbered point signal of the signal train after the FFT / IFFT with the number of points 2N by sequentially FFT / IFFT the input signal train E2 with the number of points N and the signal train O2 with the number of points N for each signal train An odd number signal sequence O1 having a number N of signal trains E1 and an odd number point signal of the signal train after the FFT / IFFT having a number 2N of points
FFT circuit with one point N
Number of points 2N characterized by having an IFFT circuit
FFT circuit / IFFT circuit and FFT circuit / IFFF
A device having a T circuit. The principle of the IFFT circuit of the present invention will be described in the first embodiment of the present invention, and the principle of the FFT circuit of the present invention will be described in the fifth embodiment.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION According to a first embodiment of the present invention, an IFFT circuit with a number of points N is used, and an I with a number of points of 2N is used.
An example of configuring the FFT circuit is shown in FIG. The principle of the IFFT circuit according to the first means of the present invention will be described with reference to the circuit of FIG. FIG. 3A schematically shows the waveform of the complex input signal Zin for performing the IFFT with the number of points 2N. The IFFT is for converting a signal of a frequency component into a signal of a time waveform, and 2N signals Zin
, (0), Zin (1), ..., Zin (2N-1) are the 0th carrier signal, the 1st carrier signal ,.
(2N-1) represents a carrier signal. Therefore, FIG.
It can be seen that the waveform of (a) represents the frequency distribution of the time waveform obtained by IFFT as it is, by imagining the horizontal axis as the frequency axis as shown in FIG. 3 (b). In FIG. 3, signals of even-numbered carriers are represented by ordinary arrows, and signals of odd-numbered carriers are represented by triangular arrows. Further, there is a portion without an arrow between the 0th carrier to the (2N-1) th carrier, which means that the signal level is 0. Generally, it is considered that all carriers have a signal. good.

In FIG. 2, the input signal Z of FIG.
in is input to the even-odd number division circuit 1 and the even-numbered carrier signals Zin (0), Zin (2), ... Shown in FIG.
.., an even number signal sequence E1 consisting of Zin (2N-2), and FIG.
Odd numbered carrier signals Zin (1) and Zin in (d)
(3), ..., Zin (2N-1) composed of odd number signal sequence O
It is separated into two signal sequences of 1. Then, as shown in FIG. 3E, the signal sequences are sequentially rearranged and output from the even-odd number division circuit 1. Among the signal trains output from the even-odd number division circuit 1, the even-numbered signal train E1 of N carriers output first is output.
Are first taken out, sequentially input to the IFFT circuit 2 having N points, and subjected to inverse Fourier transform. The even-numbered signal sequence E2 output by the inverse Fourier transform is input to the first 2N point conversion circuit 4 through the switch 3. on the other hand,
The N-carrier odd-numbered signal sequence O1 output from the even-odd number division circuit 1 after the even-numbered signal sequence E1 is subjected to inverse Fourier transform in the same IFFT circuit 2. The odd-numbered signal sequence O2 that has been subjected to the inverse Fourier transform and is output through the switch 3
Is input to the 2N point conversion circuit 5.

By the way, the time waveform output from the IFFT having the number of points of 2N can be generally represented as a set of 2N sine waves shown in FIG. It is assumed that each sine wave is modulated by each of 2N signals Zin input to the IFFT having 2N points. The time waveform of the 0th carrier is a direct current and becomes a straight line of a constant level. The time waveform of the first carrier is a sine wave with one peak and one valley in the 2N point period, the time waveform of the second carrier is a sine wave with two peaks and valleys, and so on. The time waveform of n carriers is a sine wave having n peaks and valleys. On the other hand, since the even numbered signal sequence E2 and the odd numbered signal sequence O2 converted by the IFFT circuit 2 are signals converted by the IFFT having the number of points N, the time waveform thereof is N as shown in FIG. We only get a set of sinusoids with an integer number of peaks and valleys in the point period. Therefore, not only the number of points of the signal waveform is smaller than that of the signal waveform of FIG. 4, but only a signal without a broken sine wave is obtained as shown in the upper part of FIG. In addition, the odd number signal sequence O
No. 2 not only has a small number of signal waveform points, but also FIG.
Although the signal should enter the position of the sine wave indicated by the broken line in the upper part of FIG. 5, only the sine wave at the position shifted by one is obtained as shown in the lower part of FIG.

The first 2N point conversion circuit 4 and the second 2N
The point conversion circuit 5 is a circuit for increasing the number of points having only N points of the even-numbered signal sequence E2 and the odd-numbered signal sequence O2 to 2N points. Specifically, it is a circuit that simply outputs the same signal twice in succession. As shown in the upper part of FIG. 6, each circuit outputs an even number signal sequence E3 and an odd number signal sequence O3 each having a point number of 2N. To be done. However, the position of the sine wave of the odd-numbered signal sequence O3 is still shifted by one. The modulation circuit 6 in FIG. 2 is a circuit provided to eliminate this deviation. The odd number signal sequence O3 having the number of points 2N output from the second 2N point conversion circuit 5
Is input to the modulation circuit 6 and is modulated by rotating the complex space by +1 at 2N points. That is, the signal of the nth point is modulated by rotating 2π × n / (2N) radians, and is output as an odd number signal sequence O4 having 2N points. The lower part of FIG. 6 shows the signal waveform of the odd-numbered signal sequence O4 after this modulation. When the waveform of FIG. 6 is compared with the time waveform output from the IFFT having the number of points 2N of FIG. 4, the waveform of the upper solid line in FIG. 6 matches the even-numbered waveform of FIG. The waveform of is in agreement with the odd-numbered waveform of FIG. Therefore, by adding the signals in the upper stage and the signals in the lower stage of FIG.
The signal to be output from the FFT can be obtained. The adder circuit 7 in FIG. 2 is a circuit for performing this addition, and from this circuit, the signal sequence zo after the IFFT with the number of points 2N is executed.
ut is output.

In the FIFO 8 of FIG. 2, the odd-numbered signal sequence O2 is delayed by N points from the even-numbered signal sequence E2 and IFF.
This is a circuit for adjusting the delay time output from the T circuit 2 so that the even-numbered signal sequence E4 and the odd-numbered signal sequence O4 after time adjustment are sequentially input to the adding circuit 7 at the same timing. The above processing is expressed by the following equation. That is, the even-numbered signal sequence E2 output from the IFFT circuit 2 is as follows: E2 (n) = Σ [Zin (2 · k) · exp (+ j · 2π · k · n / N)] (3) (However, n = 0 to N-1, k = 0 to N-1) The even-numbered signal sequence E3 output from the first 2N point conversion circuit 4 is the even-numbered signal sequence E2 of the above equation. It is a signal that repeats times, and when n = 0 to N−1, E3 (n) = E2 (n) = Σ [Zin (2 · k) · exp (+ j · 2π · (2 · k) · n / (2N))] (4) (however, k = 0 to N-1). Then, when n = N to 2N−1, E3 (n) = E2 (n−N) (5), and n of the formula (4) is satisfied. Is replaced by n−N, but the relationship of exp (+ j · 2π · (2 · k) · (−N) / (2N)) = 1 holds, so the same formula as formula (4) holds. Can be represented.

Even-numbered signal sequence E output from the FIFO 8
4 is a signal obtained by simply delaying the even-numbered signal sequence E3, and E4 (n) = E3 (n) = Σ [Zin (2 · k) · exp (+ j · 2π · (2 · k) · n / ( 2N))] (6) (where, n = 0 to 2N-1, k = 0 to N-1). Similarly, the odd-numbered signal sequence O3 output from the second 2N point conversion circuit 5 is O3 (n) = Σ [Zin (2 · k + 1) · exp (+ j · 2π · (2 · k) · n / (2N))] (7) (where n = 0 to 2N-1, k = 0 to N-1), and the odd-numbered signal sequence O4 after modulation is O4 (n) = Σ [Zin (2 ・ k + 1) ・ exp (+ j ・ 2π ・ (2 ・ k) ・ n / (2N))] × exp (+ j ・ 2π ・ n / (2N)) = Σ [Zin (2 ・ k + 1) ・ exp ( + J · 2π · (2 · k + 1) · n / (2N))] (8) (where n = 0 to 2N−1, k = 0 to N−1). Therefore, the signal sequence z output from the adder circuit 7
out is zout (n) = E4 (n) + O4 (n) = Σ [Zin (k) · exp (+ j · 2π · k · n / (2N))] (9) (however, , N = 0 to 2N−1, k = 0 to 2N−1), and it can be seen that a value to be calculated by the IFFT with the number of points 2N is obtained by the expression in which N in Expression (2) is replaced by 2N. . As described above, when the circuit according to the present embodiment is used, an IFFT circuit having a number of points of 2N can be realized by using an IFFT circuit having a number of points N which is smaller than that, a simple modulation circuit and a memory circuit (FIFO). You can

FIG. 7 shows an example in which an IFFT circuit having a number of points N is used to configure an IFFT circuit having a number of points of 2N according to the second embodiment of the present invention. This circuit is a combination of the FIFOs included in the first 2N point conversion circuit 4 and the second 2N point conversion circuit 5 shown in FIG. Circuits having the same or similar functions as those of the circuit in FIG. 2 are designated by the same reference numerals. Since the principle of implementing the IFFT is the same as that of the first embodiment, the description thereof is omitted.
Only the concept of combining FOs into one will be described with reference to FIG. FIG. 8A shows the timing of the signal sequence output from the IFFT 2 having the number of points N, and FIG. 8B shows the FIFO of the first 2N point conversion circuit 4 and the second 2N point conversion circuit 4. The timing of the signal train output from the newly provided FIFO 9 instead of the FIFO of the point conversion circuit 5 is shown. The two signal trains are the same signal train E2
Although it is a column of O2, the signals are shifted by N samples from each other. Therefore, by selecting the signal train E2 of FIG. 8A and the signal train E2 of FIG. 8B with the switch 4 ″,
As shown in FIG. 8C, a signal train E3 in which the same signal train E2 is repeated twice can be obtained. That is, it can be seen that the switch 4 ″ performs the same function as the first 2N point conversion circuit 4. Similarly, the switch 5 ″ uses the signal train O2 of FIG. 8A and the signal train O2 of FIG. 8B. By selecting, it is possible to obtain a signal train O3 in which the same signal train O2 is repeated twice as shown in FIG. Ie switch 5 "
Performs the same function as the second 2N point conversion circuit 5. After that, the signal train O3 is modulated by the modulation circuit 6, while the timing of the signal train E3 is adjusted by the FIFO 8, and the even-numbered signal train E4 with the number of points 2N after time adjustment and the odd-numbered signal E2 with the number of points after modulation 2N are adjusted. By adding the column O4 by the adder circuit 7, it is possible to obtain the signal sequence zout after the IFFT with the number of points 2N. In this way, also in the circuit according to the present embodiment, as in the first embodiment, the IFFT circuit with the number of points 2N can be configured by the IFFT circuit with the number of points N and other simple circuits, and the necessary FIFO The number can be reduced, and the circuit scale can be reduced.

FIG. 9 shows an example in which an IFFT circuit having a number of points N is used to configure an IFFT circuit having a number of points of 2N according to the third embodiment of the present invention. Circuit blocks having the same functions as those of the circuit block of FIG. 2 are shown with the same numbers as in FIG. However, circuit blocks having substantially the same function but different internal circuit configurations are numbered with commas. In the circuit of FIG. 9, the order of the second 2N point conversion circuit 5 ′ and the modulation circuit 6 ′ is changed from that of the circuit of FIG.
The difference from the first embodiment is that the circuits inside them are changed. The reason why the order of the second 2N point conversion circuit 5 and the modulation circuit 6 in FIG. 2 can be exchanged is as follows. That is, the left half (0 to N-1) sine wave and the right half of the lower half of FIG.
Comparing (N to 2N-1) sine waves, the right half sine wave is simply the polarity of the left half sine wave inverted,
It is not necessary to actually calculate.

The circuit of the present embodiment utilizes this fact, and before repeating the odd numbered signal sequence O2 in the lower stage of FIG. 5 twice, first, only the modulation corresponding to the first half portion of FIG. Modulate to column O2 'and repeat twice. However, for the second signal train, an odd numbered signal train O2 ″ whose polarity is inverted is output. Therefore, in the circuit of FIG. 9, the second 2N point conversion circuit 5 ′ and the modulation circuit 6 ′ are used.
In addition to exchanging the order of the above, in the circuit inside the second 2N point conversion circuit 5 ′, a polarity inversion circuit 5′-1 is added after the FIFO for outputting the second signal train. Thereafter, similarly to the first embodiment, the modulation including the even-numbered signal sequence E4 output from the FIFO 8 and O2 'and O2 "sequentially output from the second 2N point conversion circuit 5'. By adding the subsequent odd-numbered signal sequence O4 by the adder circuit 7, the signal sequence z after the IFFT with the number of points 2N
out can be obtained. As described above, also in the circuit according to the present embodiment, the IFFT circuit having the number of points of 2N can be realized by using the IFFT circuit of the number of points N having a smaller number of points, the simple modulation circuit and the memory circuit (FIFO). it can. Further, when the present embodiment is used, the number of calculations performed by the modulation circuit can be greatly reduced to 1/2, and
It is possible to obtain the effect of reducing power consumption as compared with the above embodiment. Further, the calculation of the modulation to be performed only needs to be the modulation that makes a half turn in the complex space. Therefore, the amount of data stored in the ROM 6′-1 is half that of the modulation circuit 6 of FIG. 2, and the required memory amount can be significantly reduced.

The number of points N according to the fourth embodiment of the present invention.
FIG. 1 shows an example in which an IFFT circuit having 2N points is configured using the IFFT circuit of FIG. This circuit corresponds to the first 2 in FIG.
The FIFOs included in the N-point conversion circuit 4 and the second 2N-point conversion circuit 5'are combined into one. Circuits that perform the same or similar functions as in FIG. 9 are assigned the same numbers. The basic idea is the same as the idea of replacing the circuit of FIG. 2 with the circuit of FIG. IFF
Since the principle of realizing T is the same as that of the first embodiment, its explanation is omitted and only the concept of combining the FIFOs will be explained.
FIG. 10A shows the timing of the signal train output from the IFFT 2 with N points. IFFT2
The output signals E2 and O2 of 2 are branched into two, and one of them is directly input to the switch 3 ′. The other is a modulation which is inputted to the same modulation circuit 6 ′ as in FIG. 9 and which makes a half rotation at a rate of +1 rotation in the complex space at 2N points in the respective portions of the signal stream E2 and the signal stream O2 which are continuously input. After carrying out
It is input to the same switch 3 '. The timing of this modulated signal train E2 ′, O2 ′ is shown in FIG.
As shown in FIG. 10C, the switch 3 ′ is selected from two input signal sequences E2, O2 and signal sequences E2 ′, O2 ′.
Extract the E2 and O2 'parts. Then, the output signal is branched into two again, and one of them is directly input to the switch 4 ″ and the switch 5 ″. On the other hand, a new FIFO 9 is provided instead of the FIFOs of the first 2N point conversion circuit 4 and the second 2N point conversion circuit 5 ', and this signal string is directly input to the switch 4 ". 10 (d) shows the timing of the signal sequence E in which the polarity is inverted by the polarity inversion circuit 5'-1 in the switch 5 ".
Input 2 "and O2". The timing of the signal train is shown in FIG. This FIFO 9 is the FIFO 9 of FIG.
Since they play the same role as, they are numbered the same. By the way, FIG. 10 (c) and FIG.
The two signal trains of 0 (d) are the same signal trains E2 and O2 ′, but the signals are shifted from each other by N samples. Therefore, with the switch 4 ″, the signal train E2 of FIG.
By selecting the signal sequence E2 of 0 (d),
A signal train E3 in which the same signal train E2 is repeated twice as in (f)
Can be obtained. That is, it can be seen that the switch 4 ″ performs the same function as the first 2N point conversion circuit 4.

Similarly, by selecting the signal train O2 'of FIG. 10C and the signal train O2 "of FIG. 10E with the switch 5", the modulated signal as shown in FIG. 10G is obtained. Row O
It is possible to obtain a signal train O4 composed of 2 ′ and a signal train O2 ″ whose polarity is further inverted. That is, the switch 5 ″.
Performs the same function as the second 2N point conversion circuit 5 '. After this, the timing of the signal train E3 is set to FIFO8.
And the odd-numbered signal sequence E4 after the time adjustment and the odd-numbered signal sequence O4 are added by the adder circuit 7 to obtain the signal sequence zout after the IFFT with the number of points 2N. As described above, when the circuit according to the present embodiment is used, the IFFT circuit with the number of points 2N can be configured by the IFFT circuit with the number of points N and other simple circuits as in the first embodiment, and it is necessary. The number of FIFOs can be reduced, and the circuit scale can be reduced. Also,
In the above description, the modulation circuit 6 ′ has explained that the even-numbered signal sequence E2 is also subjected to the modulation calculation, but the modulated signal sequence E2 ′ is not used in the end. Therefore, the calculation amount can be reduced by not performing the modulation calculation on the signal sequence E2. Then, by stopping the circuit during this period, an effect of reducing power consumption can be obtained.

FIG. 11 shows an example in which an FFT circuit having a number of points N is used to form an FFT circuit having a number of points of 2N according to the fifth embodiment of the present invention. The principle of the FFT circuit according to the second means of the present invention will be described with reference to the circuit of FIG. FIG. 11 basically performs the operation performed in the IFFT circuit of FIG. 9 in the opposite direction. The signal zin input to FIG. 11 is the same signal as the signal zout output from FIG. 9, and is composed of a set of 2N sine waves as shown in FIG. By the way, the signal F in the first half of the signal in FIG.
Then, when the signal B of the latter half is overlapped, it becomes as shown in FIG.
Here, the broken line represents the signal waveform of the signal B in the latter half part. The even-numbered carrier does not have the waveform of the broken line representing the signal waveform of the signal B in the latter half portion, but this is because it overlaps the waveform of the solid line representing the signal of the signal F in the first half portion. The waveforms of the broken line and the solid line of the odd-numbered carriers have exactly opposite polarities, and when added, they cancel each other and become 0. Therefore, when the sum of the signal F of the first half and the signal B of the second half is taken, only the signal of the even number carrier remains, and the signal train E2 having the same configuration as the first half of the upper part of FIG. 6 is obtained. On the other hand, when the signal F of the first half of the signal of FIG. 4 and the signal -B of the latter half of which the polarity is inverted are overlapped, the result is as shown in FIG. This time, on the contrary, the signal waveforms of the odd-numbered carriers overlap and the polarities of the signal waveforms of the even-numbered carriers are inverted. Therefore, when the sum of the signal F of the first half portion and the signal B of the latter half portion whose polarity is inverted, only the signal of the odd number carrier remains, and the signal train O2 ′ having the same configuration as the first half portion in the lower part of FIG. 6 is obtained.

The first N-point converting circuit 24 and the second N-point converting circuit 25 'shown in FIG. 11 are circuits for performing the addition and subtraction, respectively. The signal train E2 in the first half of the upper part of FIG. 6 calculated by the first N-point conversion circuit 24 is the same signal as the signal in the upper part of FIG. 5, and has the same structure as the signal obtained by the IFFT with the number of points N. It has become. Therefore, conversely, the FFT operation with the number of points N can be performed as it is. Therefore, the signal train E2 with the number of points N output from the first N-point conversion circuit 24 of FIG.
Is directly input to the FFT circuit 22 with N points, and the converted signal train E1 with N points is temporarily stored in one FIFO of the even / odd combination circuit 21. by the way,
Signal sequence O output from the second N-point conversion circuit 25 '
In 2 ′, like the signal in the first half of the lower part of FIG. 6, each carrier position is deviated from the carrier position of the signal obtained by the IFFT with the number of points N by half. Therefore, the modulation circuit 2
6 ″, the signal train O2 ′ having the number of points N is subjected to half-rotation modulation similar to that of the modulation circuit 6 ′ of FIG. 9, but modulation in the reverse direction is added, and the signal of the number N of points having the same structure as the lower stage of FIG. Row O2
Then, it is input to the FFT circuit 22 having N points. More specifically, the modulation performed by the modulation circuit 26 "is
This is a modulation in which a half rotation is performed at a rate of -1 rotation in the complex space at 2N points, and the signal at the n-th point is -2π × n /
(2N) Radian rotation modulation is applied. Signal train O2 of the number of points N output from the modulation circuit 26 "
Is input to the FFT circuit 22 having N points. The converted and output signal train O1 having the number of points N is temporarily stored in the other FIFO of the even-odd combination circuit 21. After this,
By alternately and sequentially reading out the signals of the even-numbered carrier signal train E1 and the odd-numbered carrier signal train O1 from the even-odd number combination circuit 21, it is possible to obtain the signal train zout after the FFT with the number of points 2N.

In the FIFO 28 of FIG. 11, the even-numbered signal sequence E2 and the odd-numbered signal sequence O2 are simultaneously transferred to the FFT circuit 2
It is a circuit that adjusts the timing so that it is not input to the input terminal 2. Therefore, the insertion point is the first N-point conversion circuit 2
4 and the position may be exchanged. Further, it may be inserted at any position of the line on the side of the second N-point converting circuit 25 '. The above processing is expressed by the following equation. That is, the signal sequence of the input time waveform is zin (n) = Σ [Zout (k) · exp (+ j · 2π · k · n / (2N))] (10) (However, n = 0 to N−1, k = 0 to 2N−1) The first half of the input time waveform is F (n) = Σ [Zout (k) · exp (+ j · 2π · k · n / (2N ))] (11) (where n = 0 to N-1, k = 0 to 2N-1) The second half of the input time waveform is as follows: B (n) = Σ [Zout (k ) ・ Exp (+ j ・ 2π ・ k ・ (n + N) / (2N))] = Σ [(-1) ^k・ Zout (k) ・ exp (+ j ・ 2π ・ k ・ n / (2N))] ・ ・(12) (where n = 0 to N-1, k = 0 to 2N-1) Therefore, when the signal F in the first half and the signal B in the second half are arithmetically averaged, E2 (n) = ( F (n) + B (n)) / 2 = Σ [Zout (2k) · exp (+ j · 2π · k · n / N)] ..... (13) (where, n = 0~N-1, k = 0~N) become. This equation converts Zin (k) in equation (2) to Zout
(2k), which is an equation in which the signal sequence Zout (2k) of the even number carrier with the number of points N is added to the IFF with the number of points N.
It agrees with the result of applying T. Therefore, conversely, the signal sequence E2 is Fourier-transformed by the FFT circuit 22 having the number of points N to obtain the signal sequence Zout (2
k) can be demodulated.

On the other hand, by taking 1/2 the difference between the signal F in the first half and the signal B in the second half, O2 '(n) = (F (n) -B (n)) / 2 = Σ [ Zout (2k + 1) · exp (+ j · 2π · k · n / N)] xexp (+ j · 2π · n / (2N)) ··· (14) (However, n = 0 to N− 1, k = 0 to N). The formula in Σ of this formula is Zin (k) of formula (2)
It matches the expression replaced with Zout (2k + 1). However, its value is 2 by exp (+ j · 2π · n / (2N))
At N points, it is half-turned at a rate of +1 turn on the complex space. Therefore, conversely, in the modulation circuit 26 ", exp
Multiply (-j · 2π · n / (2N)) and rotate in the opposite direction. The signal sequence O2 (n) obtained as a result is Z of the equation (2).
In this expression, in (k) is replaced with Zout (2k + 1). O2 (n) = Σ [Zout (2k + 1) · exp (+ j · 2π · k · n / N)] ··· (15) (However, n = 0 to N−1, k = 0 to 0 N) Therefore, on the contrary, the signal Zout (2k + 1) of the odd number carrier with the number of points N can be demodulated by Fourier-transforming the signal sequence O2 by the FFT circuit 22 with the number of points N. After that, the signal sequence Zout (2
k) and the odd-numbered carrier signal Zout (2k + 1) are alternately read one by one, so that the FF with the number of points is 2N.
The signal sequence Zout after T can be obtained. Like this
When the circuit according to the present embodiment is used, an FF having 2N points is used.
The T circuit can be realized by using an FFT circuit having a smaller number of points N and a simple modulation circuit and memory circuit (FIFO).

FIG. 14 shows an example in which an FFT circuit having 2N points is configured by using an FFT circuit having N points according to the sixth embodiment of the present invention. This circuit corresponds to the first N point conversion circuit 24 and the second N point conversion circuit 2 of FIG.
The FIFOs included in each of the 5'are grouped together. Circuits having the same or similar functions to those in FIG. 11 are designated by the same reference numerals. The basic idea is similar to the idea of replacing the circuit of FIG. 2 with the circuit of FIG. Since the principle of realizing the FFT is the same as that of the fifth embodiment, its explanation is omitted and only the concept of combining the FIFOs will be explained. FIG. 15A shows a signal sequence zin (first half = F, second half =
It shows the timing of B). This signal sequence zi
n is branched into two, one of which is delayed by a newly provided FIFO 29 instead of the FIFOs of the first N-point conversion circuit 24 and the second N-point conversion circuit 25 ′, and then added to the addition circuit 24 ″. It is input to the adder circuit 25 ″. The timing of the signal trains F and B is shown in FIG. The other of the branched signal sequence zin is further branched into two, one of which is directly input to the adder circuit 24 ″ and the other of which is the polarity inverting circuit 2
After passing through 5′-1, it is input to the adder circuit 25 ″. Among these, the timing of the signal trains F and B input to the adder circuit 24 ″ is as shown in FIG. After adding with the signal sequence of FIG. 15 (b), the FIFO 28 outputs about N
After the sample period is delayed, the signal train E2 having the number N of points in FIG. 15D is obtained.

On the other hand, the timing of the signal trains -F and -B input to the adder circuit 25 "through the polarity inversion circuit 25'-1 is as shown in FIG. 15 (e).
After being added to the signal train of (b), it is modulated by the modulation circuit 26 ″ to obtain the signal train O2 of the number N of points of FIG. 15 (f). The switch 23 uses the number N of points of FIG. 15 (d).
Signal train E2 of FIG. 15 and the signal train O of the number of points N of FIG.
2 are sequentially selected and input to the FFT circuit 22 having N points. The converted signal trains E1 and O1 are temporarily stored in the two FIFOs of the even-odd number coupling circuit 21. Thereafter, the signals of the even-numbered carrier signal train E1 and the odd-numbered carrier signal train O1 are alternately read one by one from the even-odd number combination circuit 21 to obtain the signal train zout after the FFT with the number of points 2N. be able to. As described above, also in the circuit according to the present embodiment, the FFT circuit with the number of points 2N can be configured by the FFT circuit with the number of points N and other simple circuits as in the fifth embodiment, and the necessary FIF
The number of O can be reduced, and the circuit scale can be reduced.

An FFT circuit with N points is used,
As an example of the configuration of the FFT circuit having the number of points of 2N, as shown in FIG. 16, it is also possible to configure a circuit for performing the calculation performed by the IFFT circuit of FIG. 2 in the opposite direction. In each embodiment, the signal train E input to the IFFT circuit 2 having N points is used.
The interval between 1 and O1 may be opened, but this is not preferable because the necessary capacity of the FIFO 8 for adjusting the delay time becomes large. The same applies to the case of the FFT circuit 22 having N points. Further, the insertion position of the FIFO 8 for adjusting the delay time is the first 2N point conversion circuit 4 in the circuit of FIG.
Needless to say, it may be moved to any position as long as the timing relationship can be maintained, such as moving before. The same applies to the FIFO 28 for adjusting the delay time. Further, in the above embodiment, for convenience of explanation of the operating principle,
IFFT circuit with 2N points and FF with 2N points
The T circuit has been described separately. However, as can be seen from the comparison between the FFT calculation formula (1) and the IFFT calculation formula (2), the difference between the two formulas is only the opposite direction in which the input signal sequence zin or Zin is rotated. Therefore, any 2N-point IFFT circuit can be used as a 2N-point FFT circuit by reversing the rotation direction of the modulation circuit 8. Similarly, F of any number of points 2N
Also in the FT circuit, if the rotation direction of the modulation circuit 26 'is reversed,
It can be used as an IFFT circuit with 2N points. In the circuits of the first to sixth embodiments, N
A 4N point IFFT circuit / FFT circuit can be configured by replacing the point IFFT circuit / FFT circuit with the circuit of each embodiment. In this case,
2N point I by the first means represented by the circuit of
The N-point IFFT circuit in the FFT circuit is shown in FIG.
2N point IFFT by the second means typified by
When replaced by a circuit, the circuit shown in FIG. 17 has the circuit shown in FIG. 16 in the first half and the circuit shown in FIG. 2 in the latter half with the N-point IFFT circuit 2 interposed therebetween. The signal train to be input to the N-point IFFT circuit 2 and the signal train to be output are both even-numbered signal trains E2, O2 and E1,
It becomes O1, and the even-odd number division circuit 1 and the even-odd number combination circuit 21 are not necessary. Therefore, with this configuration, the effect of reducing the scale of the 4N-point IFFT circuit can be obtained.
The same applies to a 4N point FFT circuit.

[0025]

As described above, when the circuit according to the present invention is used, an IFFT circuit / FFT circuit having a number of points of 2N can be converted into an IFFT circuit / FF having a number of points of less than N.
It can be realized by using a T circuit, a simple modulation circuit, and a memory circuit (FIFO). Therefore, FFT to be developed
/ The gate scale of the IFFT circuit can be reduced,
Not only can the development cost be reduced, but the developed IC
The effect is that the unit price can be lowered. In addition, when applied to multiple types of products that are produced in small quantities, the product price can be reduced by using an IC with a low development cost and a low unit price for products that require an FFT circuit / IFFT circuit with a small number of points. The effect that can be suppressed is obtained. In addition, an FFT circuit that requires a large number of points /
Even in products requiring an IFFT circuit, an FFT circuit / IF with the required number of points can be obtained by simply adding a relatively low-priced memory and a multiplication circuit to an IC with a small gate size and a low price.
Since the FT circuit can be constructed at low cost, the area of the circuit is slightly increased, but the effect of reducing the product price can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an IFFT circuit according to a fourth embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an IFFT circuit according to a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of an IFFT circuit driving method according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of an OFDM modulation signal waveform.

FIG. 5 is a diagram for explaining processing of the IFFT circuit according to the first embodiment of the present invention.

FIG. 6 is a diagram for explaining processing of the IFFT circuit according to the first embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an IFFT circuit according to a second embodiment of the present invention.

FIG. 8 is an explanatory diagram of signal timing of the IFFT circuit according to the second embodiment of the present invention.

FIG. 9 is a block diagram showing the configuration of an IFFT circuit according to a third embodiment of the present invention.

FIG. 10 is an explanatory diagram of signal timing of the IFFT circuit according to the fourth embodiment of the present invention.

FIG. 11 is a block diagram showing the configuration of an FFT circuit according to a fifth embodiment of the present invention.

FIG. 12 is a diagram for explaining the processing of the FFT circuit according to the fifth embodiment of the present invention.

FIG. 13 is a diagram for explaining the processing of the FFT circuit according to the fifth embodiment of the present invention.

FIG. 14 is a block diagram showing the configuration of an FFT circuit according to a sixth embodiment of the present invention.

FIG. 15 is an explanatory diagram of signal timing of the FFT circuit according to the sixth embodiment of the present invention.

FIG. 16 is a block diagram showing the configuration of another FFT circuit according to the present invention.

FIG. 17 is a block diagram showing the configuration of a 4N-point IFFT circuit according to the present invention.

[Explanation of symbols]

1: Even-odd number division circuit, 2: IFFT circuit, 3: Switch, 4: First 2N point conversion circuit, 4 ″, 5 ″: Switch, 5, 5 ′: Second 2N point conversion circuit, 5′−
1: polarity inversion circuit, 6, 6 ': modulation circuit, 6'-1: R
OM, 7: adder circuit, 8, 9: FIFO, 24: first N-point conversion circuit, 25 ': second N-point conversion circuit,
26 ': Modulation circuit, 23: Switch, 2 points 2N
FFT, 21: Even-odd number combination circuit, 28, 29: FIF
O, 24 ″, 25 ″: adder circuit.

Claims (2)

[Claims] 1. An inverse Fourier transform (IF) having 2N points
(FT) circuit / Fourier (FFT) conversion circuit, the even numbered points which are the first signal sequence obtained by separating the input signal sequence of 2N points input to the IFFT circuit / FFT circuit of 2N points Of the even numbered signal sequence E1 having the number N of points and the odd numbered signal sequence O1 having the number of points N of the input signal of the odd numbered point which is the second signal sequence obtained by the separation, IF for each signal sequence
IFF of 1 point number N output by FT / FFT
The T circuit / FFT circuit and the even numbered signal sequence E2 after conversion of the number of points N converted and output by the IFFT circuit / FFT circuit of the number of points N are 2
The converted even numbered signal sequence E4 having the number of points 2N obtained by repeating the number of times and the odd numbered signal sequence O2 having the number of points N converted and output by the IFFT circuit / FFT circuit of the number of points N are 2
The odd-numbered signal sequence O3 having the number of points 2N obtained by repeating the number of times is added to the signal sequence O4 which is modulated by further rotating the complex space by ± 1 rotation at 2N points, that is, the n-th signal sequence.
The signal at the point is ± 2π × n / (2N) (However, IFFT
In the circuit, it is +, and in the FFT circuit, the modulated odd numbered signal sequence O4 with the number of points 2N that has undergone radian rotation is input, and the converted even numbered signal sequence E4 with the number of points 2N and the number of the number 2N of the converted points are input. 2. An IFFT circuit / FFT circuit with 2N points, comprising an adder circuit that adds the odd-numbered signal sequence O4 after modulation for each signal of each point and outputs it as a signal sequence after IFFT / FFT with 2N points. 2. An FFT circuit / IFFT having 2N points
A circuit, the number of points N consisting of signals from the 0th point to the (N-1) th point in the first half of the input signal sequence of 2N points input to the FFT circuit / IFFT circuit of 2N points
Signal sequence F and the Nth point (2N−
1) A signal train B of N points consisting of signals of points
Is added for each signal of each point, the signal train F of the first half part and the signal train -B in which the polarities of the signal train B of the latter half part are inverted are added for each signal of each point. A second adder circuit for adding, a signal sequence E2 of the number of points N output from the first adder circuit, and a number of points N output from the second adder circuit
Signal train O2 ′ of 2N points is subjected to half rotation modulation at a rate of ± 1 rotation in the complex space (however, − in the FFT circuit, + in the IFFT circuit), that is, the signal of the nth point. Is input to the signal train O2 of the number of points N which is modulated by rotating ± 2π × n / (2N) radians,
A point consisting of an even numbered point signal of the signal train after the FFT / IFFT with the number of points 2N by sequentially FFT / IFFT the input signal train E2 with the number of points N and the signal train O2 with the number of points N for each signal train An odd number signal sequence O1 having a number N of signal trains E1 and an odd number point signal of the signal train after the FFT / IFFT having a number 2N of points
FFT circuit with one point N
Number of points 2N characterized by having an IFFT circuit
FFT circuit / IFFT circuit.