JP2003115593A5 - - Google Patents
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- JP2003115593A5 JP2003115593A5 JP2001309107A JP2001309107A JP2003115593A5 JP 2003115593 A5 JP2003115593 A5 JP 2003115593A5 JP 2001309107 A JP2001309107 A JP 2001309107A JP 2001309107 A JP2001309107 A JP 2001309107A JP 2003115593 A5 JP2003115593 A5 JP 2003115593A5
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- Prior art keywords
- channel region
- scanning line
- electro
- optical device
- gate electrode
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Claims (11)
該画素電極に電気的に接続される半導体層と、該半導体層のチャネル領域に対応して、該半導体層の上方に第 1 の絶縁膜を介して配置される島状のゲート電極と、
該半導体層の下方に第２の絶縁膜を介して配置される走査線と、
前記ゲート電極と前記走査線とを電気的に接続する接続部と、
を備える電気光学装置であって、
前記チャネル領域は、その長さ方向に交わる断面内で高低差を有し、
前記ゲート電極は、前記断面内で前記チャネル領域の高低差に対応する高低差を有することを特徴とする電気光学装置。 A pixel electrode on the substrate;
A semiconductor layer electrically connected to the pixel electrode, an island-shaped gate electrode disposed above the semiconductor layer via a first insulating film corresponding to a channel region of the semiconductor layer ,
A scanning line disposed below the semiconductor layer via a second insulating film;
A connection part for electrically connecting the gate electrode and the scanning line;
An electro-optical device comprising:
The channel region has a height difference in a cross section intersecting in the length direction thereof,
The electro-optical device, wherein the gate electrode has a height difference corresponding to a height difference of the channel region in the cross section.
前記薄膜トランジスタは、
その長さ方向に交わる断面内で高低差を有するチャネル領域を含む半導体層と、
前記チャネル領域にゲート絶縁膜を介して対向配置されるとともに前記走査線の一部からなり又は前記走査線に電気的に接続されており、前記断面内で前記チャネル領域の高低差に対応する高低差を有するゲート電極と
を備え、
前記薄膜トランジスタは、前記チャネル領域の下側に他のゲート絶縁膜を介して、前記ゲート電極と電気的に接続された予備ゲート電極を更に備えており、
該予備ゲート電極も、前記断面内で前記半導体層の高低差に対応する高低差を有することを特徴とする電気光学装置。An electro-optical device comprising a pixel electrode, a thin film transistor electrically connected to the pixel electrode, and a scanning line electrically connected to the thin film transistor on a substrate,
The thin film transistor
A semiconductor layer including a channel region having a height difference in a cross section intersecting the length direction;
The channel region is opposed to the channel region through a gate insulating film and is formed of a part of the scanning line or electrically connected to the scanning line, and corresponds to the height difference of the channel region in the cross section. A gate electrode having a difference,
The thin film transistor further includes a preliminary gate electrode electrically connected to the gate electrode via another gate insulating film below the channel region,
The electro-optical device , wherein the preliminary gate electrode also has a height difference corresponding to a height difference of the semiconductor layer in the cross section .
前記薄膜トランジスタは、
その長さ方向に交わる断面内で高低差を有するチャネル領域を含む半導体層と、
前記チャネル領域にゲート絶縁膜を介して対向配置されるとともに前記走査線の一部からなり又は前記走査線に電気的に接続されており、前記断面内で前記チャネル領域の高低差に対応する高低差を有するゲート電極と
を備え、
前記走査線に並行して設けられる予備走査線と、該予備走査線の一部からなり又は該予備走査線に接続されているとともに前記チャネル領域の下側に他のゲート絶縁膜を介した予備ゲート電極とを更に備え、
該予備ゲート電極も、前記断面内で前記半導体層の高低差に対応する高低差を有することを特徴とする電気光学装置。An electro-optical device comprising a pixel electrode, a thin film transistor electrically connected to the pixel electrode, and a scanning line electrically connected to the thin film transistor on a substrate,
The thin film transistor
A semiconductor layer including a channel region having a height difference in a cross section intersecting the length direction;
The channel region is opposed to the channel region through a gate insulating film and is formed of a part of the scanning line or electrically connected to the scanning line, and corresponds to the height difference of the channel region in the cross section. A gate electrode having a difference,
A preliminary scanning line provided in parallel with the scanning line, and a preliminary scanning line which is formed of a part of the preliminary scanning line or connected to the preliminary scanning line and has another gate insulating film below the channel region A gate electrode;
The electro-optical device , wherein the preliminary gate electrode also has a height difference corresponding to a height difference of the semiconductor layer in the cross section .
該画素電極に電気的に接続される半導体層と、該半導体層のチャネル領域に対応して該半導体層の上方に第 1 の絶縁膜を介して配置される島状のゲート電極と、
該半導体層の下方に第２の絶縁膜を介して配置される走査線と、
前記ゲート電極と前記走査線とを電気的に接続する接続部と、
を備えることを特徴とする電気光学装置。 A pixel electrode on the substrate;
A semiconductor layer electrically connected to the pixel electrode; an island-shaped gate electrode disposed above the semiconductor layer via a first insulating film corresponding to a channel region of the semiconductor layer ;
A scanning line disposed below the semiconductor layer via a second insulating film;
A connection part for electrically connecting the gate electrode and the scanning line;
An electro-optical device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001309107A JP2003115593A (en) | 2001-10-04 | 2001-10-04 | Electro-optic device, manufacturing method, electronic device, and thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001309107A JP2003115593A (en) | 2001-10-04 | 2001-10-04 | Electro-optic device, manufacturing method, electronic device, and thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003115593A JP2003115593A (en) | 2003-04-18 |
| JP2003115593A5 true JP2003115593A5 (en) | 2005-06-23 |
Family
ID=19128308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001309107A Pending JP2003115593A (en) | 2001-10-04 | 2001-10-04 | Electro-optic device, manufacturing method, electronic device, and thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003115593A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012069842A (en) * | 2010-09-27 | 2012-04-05 | Hitachi Displays Ltd | Display device |
| US8878288B2 (en) * | 2011-04-22 | 2014-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN102956649A (en) * | 2012-11-26 | 2013-03-06 | 京东方科技集团股份有限公司 | Array baseplate, manufacturing method of array baseplate and display device |
| US20140374744A1 (en) * | 2013-06-19 | 2014-12-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN103411101A (en) * | 2013-07-31 | 2013-11-27 | 昆山维金五金制品有限公司 | Liquid crystal display screen support |
| JP2015119175A (en) * | 2013-11-15 | 2015-06-25 | 株式会社半導体エネルギー研究所 | Semiconductor device and display device |
| TWI695513B (en) * | 2015-03-27 | 2020-06-01 | 日商半導體能源研究所股份有限公司 | Semiconductor device and electronic device |
| JP6920785B2 (en) * | 2015-08-19 | 2021-08-18 | 株式会社ジャパンディスプレイ | Display device |
-
2001
- 2001-10-04 JP JP2001309107A patent/JP2003115593A/en active Pending
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