JP2003115546A - Semiconductor integrated circuit and bridge circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bridge circuit where a circuit scale and the number of pins are balanced with each other. SOLUTION: The bridge circuit comprises a plurality of chip devices 2, 4, 6, and 8 that perform specific treatments, a plurality of bus wires 3, 5, 7, and 9 that are connected to each chip device and transmit a signal that is outputted from the chip device, and a plurality of bit slice type circuit blocks 1a to 1d and convert the signal that is outputted from the chip device via the bus wires into a form that is suitable for the bus wires of a specified output destination for outputting. In the configuration of the bridge circuit, the circuit scale and the number of pins are balanced without generating pad necks since the bridge circuit is divided in bit slice units.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridge circuit in a semiconductor integrated circuit having a plurality of chip devices connected via bus wiring, which converts a signal transmitted through the bus wiring and relays the bus wiring.

[0002]

2. Description of the Related Art Generally, chip devices in a semiconductor integrated circuit are connected to each other via a bus wire. However, the data transfer protocol and the bus width of this bus wire are different depending on the electrical characteristics of the bus wire. to differ greatly. Therefore, when connecting bus lines, it is usually necessary to convert signals between the bus lines.

From such a technical background, a bridge circuit such as a north bridge is arranged between bus lines of a general semiconductor integrated circuit, and a signal transmitted through the bus line is converted by the bridge circuit. It enables communication between different bus lines.

[0004]

By the way, since the function of the bridge circuit is simpler than that of the chip device in the semiconductor integrated circuit, the logic portion of the bridge circuit has been advanced with the recent progress of semiconductor manufacturing technology. Is becoming smaller.

However, in the peripheral part of the bridge circuit,
Normally, a large amount of pin wiring to connect to the bus wiring is required, so even if the logic part can be downsized, the entire circuit cannot be downsized, and there is an empty area in the circuit. A so-called pad neck occurs. Recently, for example, BGA (Ball Grid Arra)
y) It is becoming possible to increase the number of pin wires per unit area of the circuit by using technology etc. to reduce the circuit size to some extent, but it is necessary to make the bus wires for high-speed wiring uniform length wires. Due to circuit design restrictions such as the fact that the bridge circuit must be placed at the end close to the chip device to be connected, it is very difficult to balance the circuit scale and the number of pins of the bridge circuit.

As described above, in the conventional bridge circuit, it is very difficult to balance the circuit scale and the number of pins without generating a pad neck, more chip devices are integrated, and higher performance is achieved. It is one of the major issues that must be solved immediately in designing and manufacturing semiconductor integrated circuits.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a semiconductor integrated circuit equipped with a bridge circuit in which the circuit scale and the number of pins are balanced without generating a pad neck. To provide a circuit.

[0008]

A bridge circuit according to the present invention has a bit slice structure. Since the bridge circuit according to the present invention is divided into bit slice units, it is possible to easily design and manufacture a bridge circuit in which the circuit scale and the number of pins are balanced without generating a pad neck. be able to. Further, it becomes possible to disperse risks such as failure.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The bridge circuit according to the present invention can be applied to and implemented in a semiconductor integrated circuit having a plurality of chip devices. Hereinafter, the configuration of the bridge circuit according to the embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a schematic diagram showing the structure of a bridge circuit according to an embodiment of the present invention.

As shown in FIG. 1, the bridge circuit of this embodiment has a plurality of bit slice type bridge circuits 1.
a to 1d, each bridge circuit 1a to 1d
Is an FSB (Front Side Bus) wiring 3 connected to the CPU 2, a memory bus wiring 5 connected to a plurality of bit slice type memories 4, an AGP (Accelerated Graphics Port) wiring 7 connected to the graphics processor 6, and input / output. PCI (Peripheral Component I) connected to the device 8
nterconnect) connected to the bus line 9.

The FSB wiring 3, the memory bus wiring 5, A
The GP wiring 7 and the PCI bus wiring 9 are divided (bit slice) with a predetermined bit width to connect each chip device and each bridge circuit 1a to 1d.

The bridge circuits 1a-1d are respectively
HOST-PCI (host-PC eye) bridge,
In addition, a memory controller such as a cache or a main memory is built in, and signals input from the FSB wiring 3, the memory bus wiring 5, the AGP wiring 7, and the PCI bus wiring 9 are converted into a form corresponding to the output destination bus wiring. Output.

As shown in FIG. 2, the bridge circuits 1a to 1d have the same distance between the bridge circuit 1 and the CPU 2, the memory 4, the graphics processor 6 and the input / output device 8. It is desirable to place it in a position. According to such an arranging method, it is possible to make the bus wiring, which is speeded up, equal in length.

As described above, according to the bridge circuit of this embodiment, since the bridge circuit is composed of a plurality of bit slice type circuit groups, generation of a pad neck is suppressed, and the circuit scale and the number of pins are reduced. A balanced bridge circuit can be easily manufactured. Further, it becomes possible to disperse risks such as failure. Furthermore, DRAM
It becomes possible to divide and configure in a scalable manner like the above.

Lastly, the embodiments to which the invention made by the present inventors has been applied have been described above, but the present invention is limited by the discussion and the drawings which form part of the disclosure of the present invention according to the embodiments. There is no such thing. Other embodiments made by those skilled in the art based on this embodiment,
It should be added that all examples and operational techniques are included in the scope of the present invention.

[0017]

According to the present invention, it is possible to manufacture a bridge circuit in which the circuit scale and the number of pins are balanced without generating a pad neck.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of a bridge circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a configuration of a bridge circuit according to another embodiment of the present invention.

[Explanation of symbols]

1a to 1d ... Bridge circuit, 2 ... CPU, 3 ... FSB wiring, 4 ... Memory, 5 ... Memory bus wiring, 6 ... Graphics processor, 7 ... AGP wiring, 8 ... Input / output device, 9
... PCI bus wiring

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoshi Hiroi             7-1, Akasaka, Minato-ku, Tokyo Co., Ltd.             Sony Computer Entertainment             Within (72) Inventor Akio Oba             7-1, Akasaka, Minato-ku, Tokyo Co., Ltd.             Sony Computer Entertainment             Within F term (reference) 5F038 AV13 CD07 DF01 DF04 DF05                       DF11 DF16 EZ20

Claims (6)

[Claims] 1. A plurality of chip devices that perform a predetermined process, a plurality of bus lines that are connected to each chip device and that transmit a signal output from the chip device, and a plurality of bit slice type circuit blocks. A semiconductor integrated circuit comprising a bridge circuit configured to convert a signal output from the chip device via the bus wiring into a form suitable for a designated output destination bus wiring and output the converted signal. 2. The semiconductor integrated circuit according to claim 1, wherein the plurality of circuit blocks are arranged at positions having the same bus wiring length with the chip device. 3. The semiconductor integrated circuit according to claim 1, wherein the plurality of bus lines are of a bit slice type. 4. The semiconductor integrated circuit according to claim 1, wherein each of the circuit blocks includes a host-PC eye bridge. 5. A bridge circuit composed of a plurality of bit slice type circuit blocks, which converts an input signal into a form suitable for an output destination bus line and outputs the converted signal. 6. The bridge circuit according to claim 5, wherein each circuit block comprises a host-PC eye bridge.