JP2003115198A - Defect analyzer for memory lsi and defect analysis method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a defect analyzer for a memory LSI which can efficiently detect regularity of defect caused partially, and a defect analysis method. SOLUTION: A memory LSI is tested, the number of defect bits are counted for bit map data for each address coordinate, a histogram of the number of defect is made, and wavelet analysis making harl function a base function is performed by assuming the made histogram of the number of defect as a discrete signal. Shading is specified in accordance with magnitude of obtained wavelet spectrum. The shading is colored on a two dimensional graph in which an address is set to a X axis and gradation of wavelet is set to a Y axis, and a shading graph is made.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory LSI (large scale integrated circuit) which is a semiconductor application device.
The present invention relates to a failure analysis device and a failure analysis method for a large-scale integrated circuit).

[0002]

2. Description of the Related Art A failure occurrence tendency of a memory LSI is analyzed,
Elucidation of the cause of the defect is extremely important for improving the yield of the memory LSI. Conventional memory L
An example of the SI failure analysis device is Japanese Patent Laid-Open No. 11-3067.
There is a device disclosed in Japanese Patent Publication No. 93. According to this device, it is possible to inspect the memory for good or bad, create a bad bitmap, perform a two-dimensional wavelet transform on the bad bitmap, and automatically create a histogram of the number of bads for each address range. Is described. However, the function of this device is only to automatically count the number of defects in each address range, and it is not possible to analyze the cause of defects. Therefore, the cause of failure is analyzed by a person based on the data of the number of failures. However, since the capacity of the memory LSI is extremely large, there is a problem that a large amount of time is required for a person to analyze the defective data and specify the cause of the defective.

Therefore, conventionally, a device for automatically analyzing defective data has been developed. Such a memory LSI failure analysis device is disclosed in, for example, Japanese Patent Laid-Open No. 07-
There is a device disclosed in Japanese Patent Publication No. 072206. This device is an expert system in which the know-how of a process engineer, a circuit engineer, and a layout engineer are programmed and stored in a personal computer. This memory L
The SI failure analysis device can automatically analyze the cause of the failure while interacting with the memory tester. In addition, Japanese Patent Laid-Open No.
Japanese Patent Application Laid-Open No. 000-200814 discloses a technique of determining whether the distribution of defects includes a regular distribution or an irregular distribution by analyzing the type of the divisor of the interval of each defective bit and its frequency. Has been done. As a result, it is possible to determine whether the generated defect is due to the design of the memory LSI.

However, in these technologies,
There is a problem that the speed of failure analysis is slow and it cannot be applied to a memory LSI having a large capacity and a high density. In recent years, the speed of increasing the capacity and the density of memory LSIs has been increasing more and more. In the future, it is necessary to deal with the failure analysis of dynamic random access memory (DRAM) of 256 megabits or 1 gigabit or more. is there. Further, it is certain that the wafer size will be increased in the future, and for example, a wafer having a diameter of 300 mm will be handled. In this case, the number of chips to be analyzed and the number of defective bits detected by the analysis increase dramatically compared to the conventional case.

As a technique for solving this problem, Japanese Unexamined Patent Publication No. 20
Japanese Patent Laid-Open No. 00-21195 discloses a technique of performing a failure analysis by dispersing inspection data into a plurality of pieces. This allows
The failure analysis speed can be improved, and even if part of the distributed failure analysis processing is stopped for some reason, the overall failure analysis processing is not significantly delayed, and as a result, the time required for failure analysis is shortened. can do.

Further, in Japanese Patent Laid-Open No. 2000-321333, the address difference of defective data is calculated, a histogram is created based on this address difference, an expected value function with respect to a factor is obtained from this histogram, and the regularity of the defect distribution is calculated. A method of determining is disclosed. As a result, the factor check process can be performed once, so that the failure analysis algorithm can be speeded up and the failure analysis speed can be improved.

Further, Japanese Unexamined Patent Publication No. 2000-187062 discloses a technique for speeding up failure analysis by designating an analysis target area in which failure analysis is performed in advance.

[0008]

However, the above-mentioned conventional technique has the following problems. JP 2
000-21195 and JP 2000-3213.
In the technique disclosed in Japanese Patent No. 33, only periodicity over the entire analysis region can be determined. For this reason, there is a problem that it is not possible to accurately detect a partially generated regularity defect, and even if it can be detected, it is not possible to specify in which part of the analysis region the regularity defect of that period exists. .

Further, in the technique disclosed in Japanese Patent Laid-Open No. 2000-187062, although a partially generated defect can be analyzed, the analysis accuracy is not sufficient,
In addition, there is a problem that the whole cannot be analyzed. If the analysis is performed for all the small areas divided to analyze the whole, the analysis efficiency decreases.

The present invention has been made in view of the above problems, and analyzes the distribution of defective bits on a wafer and a chip of a memory LSI by analyzing local defects in each area without dividing the area to be tested. An object of the present invention is to provide a failure analysis apparatus and a failure analysis method for a memory LSI, which can perform analysis at high speed and calculate the periodicity distribution and the strength of the regularity of partially generated failures.

[0011]

Means for Solving the Problems Memory LS according to the present invention
The I failure analysis device performs an electrical test on the memory LSI to determine whether each bit is good or bad, and stores the judgment result and the coordinate data of the bit, and a test means for the judgment result and the coordinate data. Based on the defect number histogram creation means for creating the histogram data of the defective bit number for each coordinate based on the histogram data by calculating the wavelet spectrum by wavelet analysis of the histogram data to determine the strength of the periodicity of the defective bit and its period. And a spectrum calculating means for obtaining the spectrum.

In the present invention, the number of defective bits is obtained for each coordinate of the memory LSI, histogram data is created, and wavelet analysis is performed on this histogram data to calculate a wavelet spectrum. Since the wavelet spectrum shows the regularity in each coordinate area, the regularity of the defective bit can be obtained for each local coordinate area in the entire area of the memory LSI. Moreover, since the wavelet analysis can be performed by a relatively simple calculation, the failure analysis can be performed at high speed.

Further, the memory LSI failure analysis apparatus is
The wavelet spectrum is classified into a plurality of groups based on the magnitude of the absolute value thereof, and a shade correspondence means for making different shades or colors correspond to each other, and the coordinate of the bit on one axis. The axis of the wavelet spectrum is taken on another axis that intersects with this axis, and the shading or color corresponding to the coordinates and the wavelet spectrum corresponding to the hierarchy is drawn in the region indicated by the coordinates and the hierarchy of the wavelet spectrum. And a gradation graph creating means for creating a graph.

This makes it possible to create a two-dimensional graph of the wavelet spectrum, and visually display the period of regularity failure and the regularity strength that partially occur in each area of the memory LSI. . In this way, since the region having a high defect regularity and its cycle can be visually confirmed, the regular defect can be recognized quickly and reliably.

Further, the memory LSI failure analysis device is
It is preferable to have threshold setting means for setting a threshold of the wavelet spectrum and threshold determining means for determining whether or not the magnitude of the wavelet spectrum exceeds the threshold. Furthermore, it is preferable to further include a spectrum color arrangement means for coloring a region corresponding to the wavelet spectrum in the graph when the magnitude of the wavelet spectrum exceeds the threshold value. Thereby, when the magnitude of the wavelet spectrum exceeds the threshold value, it can be displayed by coloring.

The memory LSI failure analysis method according to the present invention comprises a step of electrically testing the memory LSI to determine whether each bit is good or bad, and storing the result of the determination and the coordinate data of the bit. Creating a histogram data of the number of defective bits for each coordinate based on the determination result and coordinate data, and calculating the wavelet spectrum by wavelet analysis of the histogram data to calculate the strength of the periodicity of the defective bits and And a step of obtaining the period.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. This embodiment is an embodiment of the invention described in claims 1 and 5 above. FIG. 1 is a block diagram showing a memory LSI failure analysis apparatus according to this embodiment, and FIG. 2 is a flow chart showing a memory LSI failure analysis method according to this embodiment. The memory L
For SI, for example, DRAM (dynamic random access memo)
ry).

As shown in FIG. 1, the memory LS of the present embodiment.
The I-defect analysis apparatus 1 is provided with a test means 11. The test means 11 includes a storage device (not shown), and performs an electrical test on a memory LSI (not shown) to be analyzed. As a result, that is, good / bad data of each bit and The coordinate data is stored in the storage device as bitmap data.

Further, the memory LSI failure analysis device 1 includes
Data reading means 12 is provided and connected to the testing means 11. The data reading means 12 includes an analytical computer (not shown), reads the bitmap data from the testing means 11, and holds the coordinate data of each defective bit in the memory of the analytical computer.

Further, the memory LSI failure analysis apparatus 1 is provided with a failure number histogram creating means 13 and is connected to the data reading means 12. The defective number histogram creating means 13 checks the coordinates of the defective bit stored in the data reading means 12, and, for example, adds 1 to the histogram H (i) when the coordinate of the defective bit is i. As a result, the number of defective bits is counted for each coordinate.

Furthermore, the memory LSI failure analysis apparatus 1 is provided with a wavelet spectrum calculation means 14,
It is connected to the defect count histogram creating means 13. The wavelet spectrum calculation means 14 regards the bitmap data as a discrete signal, and regards the defect count histogram H.
Discrete wavelet analysis is performed on (i) to calculate the wavelet spectrum of the defect count histogram H (i). This represents a local portion of the defect count histogram H (i), and in particular, the regularity of the power of 2 cycle is analyzed.

Next, the above-mentioned memory LSI failure analysis device 1
A method of analyzing a failure of a memory LSI that uses will be described. First, the memory LSI whose test means 11 is an analysis target
An electrical test is performed to evaluate whether each bit is good or bad. Then, the evaluation result and the coordinate data are stored in the storage device as bitmap data. Next, as shown in step S41 of FIG. 2, the data reading means 12 (see FIG. 1) reads the bitmap data from the storage device of the testing means 11 and stores the coordinate data of each defective bit in the memory of the analytical computer. Hold.

Next, as shown in step S42, the defect number histogram creating means 13 checks the coordinates of the defective bits held in the analysis computer of the data reading means 12. Next, as shown in step S43, if the coordinate of the defective bit is i, for example, 1 is added to the histogram H (i). As a result, the number of defective bits at the coordinate i is counted. This process is performed for each defective bit.

Next, as shown in step S44, it is checked whether or not the counting process has been performed for all defective bits. If there is an uncounted defective bit, the process returns to step S42. If the counting process has been completed for all defective bits, the process proceeds to step S45. Thus, steps S42 and S43
By performing the process shown in (1) for all defective bits, the defective number histogram H (i) is obtained.

In step S45, the above-mentioned bitmap data is regarded as a discrete signal, and discrete wavelet analysis is performed on the defect number histogram H (i). Hereinafter, the method of this wavelet analysis will be described in more detail. In the present embodiment, the wavelet analysis is performed using the Haar function ψ (x) shown in Equation 1 below as a basis function. By enlarging, reducing, and translating this Haar function, a local part of the defect number histogram H (i) is represented, and in particular, the regularity of the power of 2 cycle is analyzed. Note that FIG. 3 is a graph showing the relationship between the Haar function ψ (x) and the variable x shown in Formula 1 below, with the horizontal axis representing the variable x and the vertical axis representing the Haar function ψ (x).

[0026]

[Equation 1]

The address size of the inspection area is 32, for example.
When (= 2 ⁵ ), first, the defect count histogram H
From (i), the wavelet smooth coefficient C _{4, k} of the fourth layer is _obtained . When the basis function is the Haar function ψ (x) shown in Formula 1, the wavelet smooth coefficient C _{4, k} of the fourth layer is given by Formula 2 below.

[0028]

[Equation 2]

Next, the wavelet sm of the fourth hierarchy
Based on the oooth coefficient C _{4, k} , by the following mathematical formula 3,
The wavelet smooth coefficient C _{3, k} of the third layer is _obtained .

[0030]

[Equation 3]

In the same manner, the wavelet smooth coefficients C _{2, k} , C _{1, k} and C of the _{second to} 0th layers are similarly processed.
_Ask for ₀ . Wavelet smoot of layer j-1
A general formula of the h coefficient C _{j−1, k} is given by the following formula 4.

[0032]

[Equation 4]

Similarly, the defect count histogram H
(I) to 4th to 0th wavelet data
Calculate the il coefficient. 4th layer wavelet data
An equation for obtaining the il coefficient D _{4, k} is shown in Equation 5, an equation for obtaining the third layer wavelet detail D _{3, k} is shown in Equation 6, and the wavelet d for the j−1th layer is shown.
Equation 7 shows an equation for obtaining the tail coefficient D _{j−1, k} .

[0034]

[Equation 5]

[0035]

[Equation 6]

[0036]

[Equation 7]

In order to execute the above procedure, the range of i in the defect count histogram H (i) should be 2, but the address size of the DRAM should be 2. The conditions are met.

The wavelet analysis method will be described below with reference to specific numerical examples. In Figure 4, the horizontal axis is the X coordinate x
A graph showing an example of a defect count histogram H (x) with the X coordinate x created on the basis of defect data of a certain DRAM as a variable by taking the defect count histogram H (x) on the vertical axis. Is. As shown in FIG. 4, this DRA
The address size of M is 32, and the number of defects is 64. The histogram H (x) shown in FIG. 4 is given by Equation 8 below.

[0039]

[Equation 8]

When the wavelet smooth coefficient C _4,0 of the fourth layer is calculated by the above equation 2 based on the histogram H (x) shown by the above equation 8, the following equation 9 is obtained.

[0041]

[Equation 9]

Similarly, when the wavelet smooth coefficient C ₄ of the fourth layer is calculated based on the above equation 2,
It becomes like the following formula 10.

[0043]

(Formula 10) C ₄ = {6.363961041,1.414213565,0,0.70710678
2,6.363961041,0,0,2.121320347,6.363961041,0,7.0710
67824,0.707106782,6.363961041,0,6.363961041,1.4142
13565}

Next, based on the above expression 10, the wavelet smooth coefficient C of the third layer is calculated according to the above expression 3.
By calculating ₃ , the following formula 11 is obtained.

[0045]

[Equation 11]

Similarly, the wavelet smoth coefficient C _{2 of} the second layer and the wavelet sm of the first layer are sequentially arranged.
ooth coefficient C ₁ and wavelet smo of the 0th layer
When the oth coefficient C ₀ is obtained, the following equations 12 to 14 are obtained, respectively.
The formula shown in is obtained.

[0047]

[Equation 12]

[0048]

[Equation 13]

[0049]

[Equation 14]

Next, the wavelet detail coefficient is obtained. According to the above expression 5, the wavelet detail coefficient D ₄ of the fourth layer becomes as shown in the following expression 15.

[0051]

(Equation 15) D ₄ = {-6.363961041,1.414213565,0, -0.707106
782, -6.363961041,0,0, -0.707106782, -6.363961041,0,
-5.656854259,0.707106782, -6.363961041,0, -6.3639610
41, -1.414213565}

Further, based on this equation 15, the wavelet detail coefficient D of the third layer is calculated by the above equation 6.
_{When 3} is obtained, the following formula 16 is obtained.

[0053]

[Equation 16]

Similarly, when the wavelet detail coefficients of the second to 0th layers are sequentially obtained in the same manner, the following equations 17 to 19 are obtained.

[0055]

[Equation 17]

[0056]

[Equation 18]

[0057]

[Formula 19]

As described above, the wavelet smooth
The coefficient and the wavelet detail coefficient have a hierarchy of 1
The number of coefficients decreases in half as the hierarchy gets lower, and 1
The address range indicated by each coefficient is doubled. For example,
Since the address size of the DRAM in this embodiment is 32, the address x is an integer of 0 to 31. For this reason, the number of coefficients of the histogram H (x) is 32 as shown in Expression 8 above. However, as shown in the above Expression 15, there are 16 wavelet detail coefficients D _{4, k} of the fourth layer, and each coefficient D _{4, k} corresponds to two addresses x adjacent to each other. Similarly, Equation 1 above
As shown in FIG. 6, the wavelet detail of the third layer
The number of l-coefficients D _{3, k} is eight, and each coefficient D _{3, k} corresponds to four addresses x. In addition, as shown in Equation 17, the wavelet detail coefficient D of the second layer
_{2, k} is 4, and each coefficient D _{2, k} corresponds to 8 addresses x. Furthermore, as shown in Equation 18 above, the first
The number of hierarchy wavelet detail coefficients D _{1, k} is two, and each coefficient D _{1, k} corresponds to 16 addresses x, and as shown in the above equation 19, one wavelet detail coefficient D ₀ of the 0th hierarchy is one. And the coefficient D ₀ is 3
It corresponds to two addresses x, that is, all addresses.

Next, the magnitude | D of the wavelet spectrum, which is the absolute value of the wavelet detail coefficient.
The distribution tendency of defective bits in the bitmap is analyzed based on _{j, k} |. As shown in the equations 15 to 19, in the numerical example of this embodiment, addresses 0 to 1
5, the absolute value of the wavelet detail coefficient D _{2, k} of the second layer is large, and the address 16 to 31 has the wavelet detail coefficient D of the third layer D.
_It can be seen that the absolute value of _{3, k} is large. If the address size is 2 ^N and the hierarchy in Haar wavelet is R,
Since the hierarchy R represents the cycle 2 ^N−R , the DR whose address size analyzed in this embodiment is 32 (= 2 ⁵ ).
AM has a cycle of 2 ^{N−R at} addresses 0 to 15.
= 2 ^5-2 = 8, there are many regularity defects, and in the addresses 16 to 31, there are many regularity defects with a period of 2 ^5-3 = 4.

As described above, in this embodiment, the defect distribution can be analyzed for all the analysis target regions without performing the region division of the memory LSI in advance, and the defect regularity and the portion having a strong regularity can be obtained. The period can be calculated. Therefore, it is possible to detect the regularity defect even when the regularity defect only partially occurs. Further, in this embodiment, since the analysis can be performed by a relatively simple calculation, the failure analysis can be performed at high speed.

The memory LSI failure analysis apparatus and the failure analysis method of this embodiment can be applied to the failure analysis of the memory LSI other than the DRAM, and the memory-embedded L
It can also be applied to SI.

Next, a second embodiment of the present invention will be described. The present embodiment is an embodiment of the invention described in claims 2 and 6 described above. FIG. 5 shows a memory LSI according to this embodiment.
It is a block diagram showing a failure analysis device. As shown in FIG. 5, the memory LSI failure analysis apparatus 2 according to the present embodiment includes
Testing means 11, data reading means 12, defective number histogram creating means 13, spectrum calculating means 14, light and shade (color)
A designating means 21 and a shade (color) graph creating means 22 are provided. Testing means 11, data reading means 12, defect count histogram creating means 13, and spectrum calculating means 1
The configuration of No. 4 is the same as that of the first embodiment described above.

The shade (color) designating means 21 is connected to the spectrum calculating means 14, and is classified into a plurality of groups based on the magnitude of the wavelet spectrum D of the defect count histogram H (i) calculated by the spectrum calculating means 14. , Specify different shades or colors for each group.

The shading (color) graph creating means 22 is connected to the shading (color) designating means 21, and the shading (color) designating means 2 is connected.
Based on the shade or color designated by 1, a two-dimensional graph is created in which the X axis is the bit address and the Y axis is the wavelet hierarchy.

Next, a memory LSI failure analysis method according to this embodiment will be described. First, the processes of steps S41 to S45 (see FIG. 2) in the above-described first embodiment are performed. Next, as shown in FIG. 5, the spectrum calculating means 1
The wavelet spectra of the defect count histogram H (i) calculated by 4 are classified into a plurality of groups according to their sizes, and the shade (color) designating means 21 designates the shade representing each group.

FIG. 6 is a diagram showing the relationship between the spectrum size and the density. As shown in FIG. 6, in the present embodiment, the wavelet spectrum is set to 0.
0 or more and less than 1.0, 1.0 or more and less than 2.0, 2.0 or more and less than 3.0, 3.0 or more and less than 4.0, 4.0 or more 5.0
Less than, 5.0 or more and less than 6.0, and 6.0 or more, divided into 7 groups (classes), the wavelet spectrum having a magnitude of 0.0 or more and less than 1.0 is associated with white, Grays having different shades are associated with a wavelet spectrum of 1.0 or more. In the wavelet spectrum of 1.0 or more, the larger the size of the wavelet spectrum (class), the darker the gray level (closer to black) is associated.

Next, the gradation (color) graph creating means 22
A two-dimensional graph as shown in FIG. 7 is created based on the calculation result of the wavelet spectrum of the defect count histogram H (i). In FIG. 7, the horizontal axis is the bit address x,
FIG. 7 is a graph diagram in which the vertical axis represents the hierarchy of wavelet spectra, and the shades shown in FIG. 6 are drawn in regions corresponding to each bit address and the hierarchy of wavelet spectra.

As shown in FIG. 7, as a result of analyzing the numerical example of the present embodiment, it is found that the addresses 0 to 15 are dark in the second layer and the addresses 16 to 31 are dark in the third layer. Recognize. Assuming that the address size is 2 ^N and the hierarchy in the Haar wavelet is R, the hierarchy R represents a cycle of 2 ^N−R , so that a DRAM with an address size of 32 (= 2 ⁵ ) analyzed in this embodiment is , Addresses 0 to 15 have a cycle of 2 ^N−R = 2 ^5-2 = 8
It can be seen that there are many ^{irregularities} of regularity, and in the addresses 16 to 31, there are many regularity of periodicity of ^25-3 .
Note that this analysis result is the same as the analysis result of the first embodiment described above, but this embodiment compares the analysis result with the first embodiment by using the two-dimensional gray-scale graph shown in FIG. It is easier to recognize because it is displayed on the screen.

As described above, in the present embodiment, the two-dimensional gray-scale graph of the wavelet spectrum is created, so that the periodicity of regularity defects locally generated in regions of various sizes and the strength of regularity can be determined. Can be visually recognized. As described above, since the region having a strong regularity of defects and the period thereof can be confirmed at a glance, it is possible to recognize the regularity defects promptly and surely as compared with the memory LSI defect analysis apparatus and method of the first embodiment. You can

In this embodiment, the shade (color) designating means 21 designates the shade according to the size of the wavelet spectrum of the defect number histogram H (i), but the shade (color) designating means 21 The colors may be different from each other, depending on the magnitude of the spectrum, instead of the shade.

Next, a third embodiment of the present invention will be described. This embodiment is an embodiment of the invention described in claims 4 and 8 above. FIG. 8 shows a memory LSI according to this embodiment.
It is a block diagram showing a failure analysis device 3. As shown in FIG. 8, the memory LSI failure analysis apparatus 3 according to the present embodiment includes a testing unit 11, a data reading unit 12, a defect count histogram creating unit 13, a spectrum calculating unit 14, a shade (color) designating unit 21, Shading (color) graph creating means 22,
Threshold setting means 31, threshold determination means 32 and spectrum coloration means 33 are provided. Test means 11,
Data reading means 12 and defect count histogram creating means 1
3, spectrum calculation means 14, shade (color) designation means 21
And the configuration of the grayscale (color) graph creating means 22 is the above-mentioned second
It is similar to the embodiment of.

The threshold value setting means 31 is connected to the shading (color) graph creating means 22 and sets the threshold value of the magnitude of the spectrum | D _{j, k} |
The threshold value determination means 32 receives the output signal of the threshold value setting means 31, and based on the threshold value set by the threshold value setting means 31, the magnitude of each spectrum exceeds the threshold value. It is determined whether or not there is, and the determination result is output. The spectrum color arrangement means 33 is the threshold value determination means 32.
The output signal of is input, and the displayed portion of the spectrum whose magnitude exceeds the threshold value is colored. The type of color is not particularly limited, but a color that is easily visually discernable is preferable, and may be red, for example. Also, record the size of the spectrum | D _{j, k} |, the wavelet hierarchy to which this spectrum belongs, and the address range.

Next, the memory LSI failure analysis method according to this embodiment will be described. First, a two-dimensional gray scale graph as shown in FIG. 7 is created by the same method as in the second embodiment. And the data of this two-dimensional graph, that is,
The spectrum size | D _{j, k} |, the wavelet hierarchy to which this spectrum value belongs, and the address range are output to the threshold value judging means 32 via the threshold value setting means 31.

Next, the threshold value setting means 31 sets a threshold value of the magnitude of the spectrum | D _{j, k} | that can be judged to be defective in regularity, and the information of this threshold value is used as the threshold value judging means 3
Output to 2.

Next, the threshold value judging means 32 judges whether or not the magnitude of the inputted spectrum exceeds the threshold value, and the judgment result is the spectrum color arrangement means 33.
Output to.

Next, the spectrum color arrangement means 33 adds a color (for example, red) to the display portion of the spectrum whose size in FIG. 7 exceeds the threshold value. Also, record the size of the spectrum | D _{j, k} |, the wavelet hierarchy to which this spectrum belongs, and the address range. And
The result is output as a colored two-dimensional graph.

In this embodiment, as compared with the above-mentioned second embodiment, in the two-dimensional graph as shown in FIG.
Since the region corresponding to the spectrum indicating the presence of the regularity defect is colored, the regularity defect can be more easily visually recognized.

In this embodiment, the gray scale graph is further colored, but the horizontal axis indicates the address and the vertical axis indicates the wavelet hierarchy. It is also possible to create a two-dimensional graph in which only the areas exceeding the threshold value are colored. Further, the spectrum size | D _{j, k} | whose magnitude exceeds the threshold value, the wavelet hierarchy to which this spectrum belongs, and the address range may be output as numerical values without creating a two-dimensional graph.

[0079]

As described above in detail, according to the present invention, the distribution of defective bits on the wafer and chip of the memory LSI can be analyzed by local defect analysis for each area without dividing the area to be tested. It is possible to obtain a failure analysis apparatus and a failure analysis method for a memory LSI, which can be performed at high speed and can calculate the periodicity distribution and the strength of the regularity of partially generated failures. This makes it possible to prevent the yield of the memory LSI from decreasing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory LSI failure analysis apparatus according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a failure analysis method of the memory LSI according to the present embodiment.

FIG. 3 shows a variable x on the horizontal axis and a Haar function ψ on the vertical axis.
FIG. 6 is a graph chart showing the relationship between the Haar function ψ (x) shown in Expression 1 and the variable x by taking (x).

FIG. 4 is a histogram H of the number of defects in which the horizontal axis is the X coordinate x and the vertical axis is the histogram H (x) of the number of defects.
It is a graph which shows an example of (x).

FIG. 5 is a block diagram showing a memory LSI failure analysis device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between spectrum size and light and shade.

7 is a graph diagram in which the horizontal axis represents bit address x and the vertical axis represents the wavelet spectrum hierarchy, and the shades shown in FIG. 6 are drawn in the regions corresponding to each bit address and the wavelet spectrum hierarchy. .

FIG. 8 is a block diagram showing a memory LSI failure analysis apparatus according to a third embodiment of the present invention.

[Explanation of symbols]

1, 2, 3; Memory LSI failure analysis device 11; Testing means 12; data reading means 13: Defect count histogram creating means 14: spectrum calculating means 21: Shade (color) designation means 22; means for creating a shade (color) graph 31; Threshold setting means 32; Threshold value judging means 33; spectrum coloring means S41: Bitmap data reading process S42: Bad bit coordinate acquisition process S43: Histogram addition process S44: Addition end confirmation processing S45: Spectrum calculation processing

Claims (8)

[Claims] 1. A test means for conducting an electrical test on a memory LSI to determine whether each bit is good or defective, and storing the determination result and the coordinate data of the bit, and based on the determination result and the coordinate data. Defect count histogram creating means for creating histogram data of defective bit number for each coordinate, and wavelet analysis of the histogram data to calculate a wavelet spectrum to obtain strength of the periodicity of the defective bit and its period. A memory LSI failure analysis apparatus comprising: a spectrum calculation unit. 2. The wavelet spectrum is classified into a plurality of groups based on the magnitude of the absolute value thereof, and a shade correspondence means for making the shades or colors different from each other correspond to each other, and one axis is the axis The coordinate of the bit is taken and the axis of the wavelet spectrum is taken on the other axis intersecting this axis, and the shade or color corresponding to the coordinate and the wavelet spectrum corresponding to the hierarchy is shown by the coordinate and the hierarchy of the wavelet spectrum. 2. The memory LSI failure analysis device according to claim 1, further comprising: a grayscale graph creating unit that draws in a region to create a graph. 3. A threshold value setting means for setting a threshold value of the wavelet spectrum, and a threshold value judging means for judging whether or not the magnitude of the wavelet spectrum exceeds the threshold value. The memory LSI failure analysis apparatus according to claim 2, wherein 4. A spectrum color arrangement means for coloring a region corresponding to the wavelet spectrum in the graph when the magnitude of the wavelet spectrum exceeds the threshold value. Item 5. A memory LSI failure analysis device according to item 3. 5. A step of conducting an electrical test on a memory LSI to determine whether each bit is good or defective, and storing the determination result and the coordinate data of the bit, based on the determination result and the coordinate data. A step of creating histogram data of the number of defective bits for each coordinate, and a step of calculating a wavelet spectrum by performing a wavelet analysis of the histogram data to obtain the strength of the periodicity of the defective bits and the period thereof. A memory LSI failure analysis method characterized by the above. 6. A step of classifying the wavelet spectrum into a plurality of groups based on the magnitude of the absolute value thereof and associating different shades or colors with each other, and the coordinate of the bit on one axis. Take the layer of the wavelet spectrum on the other axis intersecting this axis and draw the shade or color corresponding to the coordinate and the wavelet spectrum corresponding to the layer in the region indicated by the coordinate and layer of the wavelet spectrum. 6. The method of analyzing a memory LSI failure according to claim 5, further comprising: 7. The method according to claim 5, further comprising the steps of setting a threshold value of the wavelet spectrum and determining whether the magnitude of the wavelet spectrum exceeds the threshold value. Alternatively, the memory LSI failure analysis method according to item 6. 8. If the magnitude of the wavelet spectrum exceeds the threshold value, the step of coloring a region corresponding to the wavelet spectrum in the graph is colored. The memory LSI failure analysis method described in 1.