JP2003110631A - Apparatus and method for transmission/reception - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically make transmission/reception conditions proper according to a voltage change in a signal sent/received via a transmission line. SOLUTION: An analog and digital converter 102 converts a clock signal received via a transmission line into a digital signal and outputs it with amplitude information of the clock signal. A clock signal shaper 103 recovers the clock signal from the digital signal. A decision voltage variable buffer 105 discriminates a level of a data signal received via the transmission line according to a decision voltage decided by the amplitude information of the clock signal. An output waveform variable buffer 107 applies waveform conversion to a logic signal generated from the recovered clock signal on the basis of the decision result according to conditions decided by a voltage generated from the frequency of the recovered clock signal and a power supply voltage applied from a power supply voltage supply device 109 to generate a data signal to be sent via the transmission line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting / receiving apparatus and a transmitting / receiving method for transmitting / receiving a signal via a transmission path connecting two or more electronic devices.

[0002]

2. Description of the Related Art Conventionally, as a transmission / reception device for transmitting / receiving a signal via a transmission line connecting two or more electronic devices, for example, one described in Japanese Utility Model Laid-Open No. 6-5242 (waveform shaping device) is known. Are known.

FIG. 15 is a block diagram showing the structure of a conventional transmitting / receiving apparatus. In FIG. 15, 1501 and 15
02 is a unidirectional transmission path, 1503 is a control means, 1504 is a waveform shaping means, 1505 is a bus line, 1506 and 1
Reference numeral 507 is an electronic device, 1510 and 1520 are OR gates, 1511 and 1521 are buffers, 1530 is a D-type flip-flop (hereinafter referred to as D-FF), 1531 is a NAND gate, 1532 is an AND gate, and 1533 is an inverter.

The conventional transmitter / receiver includes a plurality of electronic devices 150 via two unidirectional transmission lines 1501 and 1502.
A data signal is transmitted and received between 6 and 1507. The control means 1503 includes a D-FF 1530 and a NAND gate 15.
31, an AND gate 1532, and an inverter 1533.

The control means 1503 detects that the input terminal of one of the electronic devices 1506 and 1507 is at a low level and judges the start of communication, and the unidirectional transmission line 1
The data signal is transmitted to either 501 or 1502, and the output of the other transmission line is fixed at a high level so that the data signal is not passed.

The waveform shaping means 1504 includes an OR gate 15.
It is composed of 10 and 1520 and buffers 1511 and 1521, and performs waveform shaping when passing a data signal.

[0007]

However, since the conventional transmitting / receiving device only shapes the waveform of the data signal in the middle of the transmission path, it cannot cope with the voltage change of the data signal. Therefore, there is a problem that a different transmitter / receiver is required for each level of the data signal transmitted / received via the transmission path.

The present invention has been made in view of the above points, and a transmission / reception apparatus and a transmission / reception method capable of automatically optimizing transmission / reception conditions in accordance with a voltage change of a signal input via a transmission path. The purpose is to provide.

[0009]

The transmitting / receiving apparatus of the present invention comprises:
A receiving amplifier that amplifies a clock signal input via a transmission path with a gain of 1, and an A / that converts the clock signal output by the receiving amplifier into a digital signal and outputs the digital signal together with amplitude information of the clock signal. A D converter, a first power supply voltage supplier that determines a power supply voltage to be supplied to the receiving amplifier from amplitude information of the clock signal, a clock signal shaper that reproduces a clock signal from the digital signal, and a transmission line. A logic signal generator that performs high-level / low-level determination of the received data signal with a determination voltage determined based on amplitude information of the clock signal, and generates a logic signal based on the determination result and the reproduced clock signal, A frequency / voltage converter for converting the frequency of the regenerated clock signal into a voltage; and the logic signal. Is an output waveform converter that performs waveform conversion under conditions determined based on a power supply voltage and an output voltage of the frequency / voltage converter to generate a data signal to be transmitted via a transmission line, and the amplitude information of the clock signal from the output waveform converter. Second for determining the power supply voltage supplied to the output waveform converter
And a power supply voltage supply device.

According to this structure, the voltage condition of the judgment voltage used for judging the high level / low level of the received data and the judgment result are determined based on the amplitude information and the frequency of the clock signal input through the transmission line. By adding control to the waveform condition that manipulates the waveform of the logic signal to generate output data from the generated logic signal, it is possible to automatically optimize the transmission / reception condition according to the voltage change of the received signal. .

The transmitter / receiver of the present invention employs a configuration in which the determination voltage determined by the logic signal generator has a hysteresis characteristic.

According to this structure, since the judgment voltage can have a hysteresis characteristic, the influence of noise of the data signal received via the transmission line is reduced.

In the transmitter / receiver of the present invention, the output waveform converter has a configuration in which the voltage of the data signal to be transmitted is substantially equal to the voltage of the clock signal.

According to this structure, the voltage of the data signal transmitted by the variable output waveform buffer can be made substantially equal to the voltage of the clock signal, so that the voltage of the data signal of the entire system can be made uniform. .

In the transmitting / receiving apparatus of the present invention, the output waveform converter has a configuration in which the waveform of the data signal to be transmitted is variable according to the frequency of the reproduction clock signal.

According to this structure, the waveform of the data signal to be transmitted can be made variable according to the clock frequency, so that the current can be saved and the high frequency component of the signal can be reduced.

In the transmitting / receiving apparatus of the present invention, the output waveform converter has a structure in which the rising / falling transition time of the data signal to be transmitted is lengthened when the frequency of the reproduction clock signal is low.

According to this structure, the waveform of the data signal to be transmitted can be made variable according to the clock frequency, so that the current can be saved and the high frequency component of the signal can be reduced.

The transmission / reception method of the present invention comprises the steps of setting the voltage condition of the first power supply voltage supplier based on the amplitude information of the clock signal from the transmission line and setting the frequency condition in the frequency / voltage converter, and from the transmission line. Of setting the power supply voltage of the receiving amplifier for amplifying the clock signal of 1 with a gain of 1 in the first power supply voltage supplier, and converting the clock signal output from the receiving amplifier into a digital signal, and converting the converted digital signal to the clock signal of the clock signal. Outputting with amplitude information,
A step of reproducing a clock signal from the digital signal; a step of judging whether or not the voltage is within the range of the voltage condition based on amplitude information of the clock signal; and a frequency of the reproduced clock signal within the range of the frequency condition. And a high level / low level determination of the data signal received through the transmission line when the clock signal is within the voltage condition and the frequency condition, based on the amplitude information of the clock signal. Under the condition that is determined based on the power supply voltage and the voltage converted from the frequency of the reproduction clock signal in the frequency / voltage converter, the logic signal is generated from the judgment result and the reproduction clock signal by the determined judgment voltage. Converting the waveform of the logic signal,
Generating a data signal to be transmitted over the transmission line,
Setting the power supply voltage determined based on the amplitude information of the clock signal in the second power supply voltage supplier.

According to this method, the voltage condition of the judgment voltage used for judging the high level / low level of the received data and the judgment result are determined based on the amplitude information and frequency of the clock signal input through the transmission line. By adding control to the waveform condition that manipulates the waveform of the logic signal to generate output data from the generated logic signal, it is possible to automatically optimize the transmission / reception condition according to the voltage change of the received signal. .

In the transmitting / receiving method of the present invention, when the clock signal is out of the range of the voltage condition and the frequency condition, the voltage condition and the frequency condition and the power supply voltage of the receiving amplifier are set to the first condition.
A step of resetting the power supply voltage supply device is provided.

According to this method, the voltage condition and the frequency condition and the power supply voltage of the receiving amplifier can be reset based on the amplitude information and the frequency of the clock signal input through the transmission line, and the power consumption of the receiving amplifier can be reset. Can be reduced.

In the transmitting / receiving method of the present invention, when the voltage of the clock signal is out of the hardware control range, the first
The power supply voltage supply device is set to notify that the power supply is out of the control range.

According to this method, it is possible to know that the voltage of the clock signal input via the transmission path has exceeded the hardware limit of the transceiver.

In the transmission / reception method of the present invention, when the frequency of the reproduced clock signal is out of the hardware control range, the frequency / voltage converter notifies the outside of the control range.

According to this method, it is possible to know that the frequency of the clock signal input via the transmission path has exceeded the hardware limit of the transceiver.

In the information processing apparatus according to the present invention, a plurality of functional units and a clock signal generator are connected via an inter-functional unit bus line, and an input / output unit of each functional unit receives data via the inter-functional unit bus line. In the information processing device that transmits and receives, the plurality of functional units are
As the input / output unit, a configuration including the transmitting / receiving device of the present invention is adopted.

According to this structure, the transmission / reception device of the present invention, which operates as an input / output unit, sets the high level / low level of the received data based on the amplitude information and the frequency of the clock signal input via the transmission path. Since control can be added to the voltage condition of the judgment voltage used for the judgment and the waveform condition for operating the waveform of the logic signal to generate the output data from the logic signal generated based on the judgment result, the voltage change of the reception signal It is possible to obtain an information processing apparatus capable of automatically optimizing transmission / reception conditions in accordance with the above.

In the information communication system of the present invention, a plurality of information processing devices and a clock signal generator are connected via an inter-device transmission line, and an external interface section of each information processing device transmits data via the inter-device transmission line. In the information communication system for transmitting and receiving the information, the plurality of information processing devices have a configuration including the transmitting and receiving device of the present invention as the external interface unit.

According to this structure, the transmission / reception device of the present invention, which operates as an external interface section, sets the high level / low level of the received data based on the amplitude information and the frequency of the clock signal input via the transmission path. Since control can be added to the voltage condition of the judgment voltage used for the judgment and the waveform condition for operating the waveform of the logic signal to generate the output data from the logic signal generated based on the judgment result, the voltage change of the reception signal It is possible to obtain an information communication system capable of automatically optimizing transmission / reception conditions in accordance with the above. Furthermore, when the waveform of the data signal cannot be optimized, it can be determined that the system configuration is inappropriate.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION The gist of the present invention is generated based on the voltage condition of a judgment voltage for judging the level of received data and the judgment result based on the amplitude and frequency of a clock signal input via a transmission line. By adding control to the waveform condition of the output data, the transmission / reception condition is automatically optimized according to the voltage change of the received signal.

Embodiments of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a transmitting / receiving apparatus according to Embodiment 1 of the present invention. In FIG. 1, this transmitter / receiver includes a clock signal receiving amplifier 101, an A / D converter 102, a clock signal shaper 103, a power supply voltage supplier 104, a judgment voltage variable buffer 105, a logic circuit 106, an output waveform variable buffer 107, and a frequency. A voltage converter 108 and a power supply voltage supplier 109 are provided.

The clock signal receiving amplifier 101 is an analog buffer having a high impedance input, a low impedance output, and a gain of 1, and as shown in FIG. 2, operates with two operating power supplies, a high potential power supply and a low potential power supply.
The received clock signal input from the transmission line is, for example, as shown in FIG.
It is an analog signal that takes an amplitude (potential) between Va1 and Va8 as shown in 1 (a). The clock signal reception amplifier 101 outputs this reception clock signal as it is to the A / D converter 102. Here, the high-potential power source is a power source having a maximum potential of the reception clock signal or higher, and the low potential power source is a power source having a minimum potential of the reception clock or lower. These are supplied from the power supply voltage supplier 104 according to the potential of the reception clock signal.

The A / D converter 102 operates by receiving the operating power supply from the power supply voltage supplier 104, and outputs a digital signal corresponding to the level of the reception clock signal which is an analog signal input from the clock signal reception amplifier 101. , With the amplitude of the clock signal. The A / D converter 102 is configured as shown in FIG. 3, for example.
FIG. 3 is a configuration example of an 8-bit A / D converter.

In FIG. 3, the A / D converter 102
Are diodes D1 and D2 and smoothing capacitors C1 and C2.
And resistors R1 to R7 forming a voltage dividing circuit and comparators 301 to 308.

In the A / D converter 102, the clock signal V input from the clock signal receiving amplifier 101 is input.
The clock is applied to the + input terminals of the comparators 301 to 308. Further, the clock signal Vclock is rectified by the diodes D1 and D2 and the smoothing capacitors C1 and C2, and is resistance-divided by the voltage dividing circuit to become voltages Va1 to Va8, which are applied to the negative input terminals of the comparators 301 to 308. In the comparators 301 to 308, the clock signal V
The clock and the divided voltage (Va1 to Va8) are compared, and FIG.
As shown in (b), 8-bit digital signal Vd1 ~
Vd8 is output. In addition, the number of bits A other than 8 bits
The / D converter can be similarly configured and can be used similarly.

The clock signal shaper 103 is, for example, as shown in FIG.
The clock signal is regenerated by detecting the rising / falling edge of the digital signal input from the A / D converter 102. In FIG. 4, the clock signal shaper 103 includes a D-FF 401 and an inverter 402. In the D-FF401, the D input has a high level Hi.
It is fixed to. The first bit Vd1 of the digital signal input from the A / D converter 102 is applied to the clock input terminal CK, and the eighth bit Vd8 is applied to the inverter 402.
It is inverted by and is applied to the clear input terminal CLR. With this configuration, the clock signal is reproduced in synchronization with the digital signal output from the A / D converter 102 (FIG. 11 (c)).

The power supply voltage supplier 104 is configured, for example, as shown in FIG. 5, and the clock signal receiving amplifier 1 is based on the output (amplitude of the clock signal) of the A / D converter 102.
01 and A / D converter 102 generates and supplies necessary power. In FIG. 5, the power supply voltage supply unit 104 includes output voltage variable DC / DC converters 501 and 503 and voltage controllers 502 and 504.

The voltage controller 502 is the A / D converter 1
Output voltage variable DC / DC converter 5 based on the maximum potential Va1 of the reception clock input from
Output to 01. Variable output voltage DC / DC converter 5
01 generates and outputs a high potential power supply from the power supply 1 based on the control voltage from the voltage controller 502.

The voltage controller 504 is the A / D converter 1
The output voltage variable DC / DC converter 5 outputs a predetermined control voltage based on the lowest potential Va8 of the reception clock input from 02.
Output to 03. Variable output voltage DC / DC converter 5
03 generates and outputs a low potential power supply from the power supply 2 based on the control voltage from the voltage controller 504.

Here, the high potential power supply is controlled to be higher than the maximum potential Va1 of the reception clock so that the clock signal reception amplifier 101 and the A / D converter 102 are not saturated, and the low potential power supply is controlled to the minimum of the reception clock. It is controlled to be lower than the potential Va8. Of course, it is possible to fix the power supply potential to the maximum / minimum value that can always be set, but it is possible to reduce power consumption by controlling it to a value as close as possible to Va1 / Va8 as much as possible. It should be noted that when the value is out of the set range, the fact is notified.

Next, the judgment voltage variable buffer 105 is constructed, for example, as shown in FIG. 6 or 7, and judges the magnitude relation between the judgment signal and the data signal received via the transmission line, and the first logic. Generates a signal and outputs the logic circuit 106
Output to. In FIG. 6, the judgment voltage variable buffer 10
5 includes an amplifier 601 and a comparator 602.

The amplifier 601 includes an A / D converter 10
From 2, the highest potential Va1 of the reception clock and the lowest potential Va8 of the reception clock are input. Of the comparator 602
The signal of (Va1 + Va8) / 2 from the amplifier 701 is supplied to the input terminal as a determination voltage, and the data signal (FIG. 11D) received via the transmission line is supplied to the + input terminal. The first logic signal which is the determination result is output from the comparator 602.

Further, in FIG. 7, the judgment voltage variable buffer 105 includes a voltage dividing circuit composed of a series circuit of resistors R1, R2 and R3, comparators 701 and 702 and a D-FF7.
03 and.

The voltage dividing circuit has an A / D converter 1 at both ends.
From 02, the potential Va2 of the reception clock and the potential Va7 of the reception clock are applied to generate the determination voltages Vh and Vl.

The comparator 701 is supplied with the reception data signal (FIG. 11 (d)) at the + input terminal, the determination voltage Vh at the − input terminal, and the output (FIG. 11 (e1)) at DF.
It is input to the clock input terminal CK of F703.

In the comparator 702, the + input terminal is supplied with the received data signal (FIG. 11 (d)), the − input terminal is supplied with the judgment voltage Vl, and the output (FIG. 11 (e2)) is DF.
It is input to the clear input terminal CLR of F703.

The data input terminal D of the D-FF 703 is fixed to the high level Hi. Therefore, D-FF703
Takes in the D input signal (Hi) at the rising edge of the CK input and sets the output terminal Q to a high level. When the CLR input becomes high level, the output terminal Q is made low level.

With this configuration, the D-FF 703 receives the data signal received at the output terminal Q via the transmission line (see FIG. 11).
The first logic signal (FIG. 11 (e) synchronized with (d)).
3)) is output. Variable judgment voltage buffer 1 shown in FIG.
By adopting No. 05, the judgment voltage can be made to have a hysteresis characteristic, and the influence of noise of the data signal can be reduced. In FIG. 7, the amplitudes Va2 and Va7 of the reception clock are used to generate the determination voltages Vh and Vl.
It is also possible to use the power supply voltage of the output waveform variable buffer 107 or the like.

Next, the logic circuit 106 receives the clock signal regenerated by the clock signal shaper 103 and the first logic signal, performs necessary processing, and outputs the second logic signal (FIG. 11 (f)). ) Output variable buffer 1
It outputs to 07.

Next, the frequency / voltage converter 108
For example, it is configured as shown in FIG. 9 and outputs a voltage that changes according to the frequency of the clock signal reproduced by the clock signal shaper 103. The output of the frequency / voltage converter 108 is input to the output waveform variable buffer 107 as a control signal. In FIG. 9, the frequency / voltage converter 1
08 is a detection diode D and resistors R1, R2, R3
And capacitors C1, C2, and C3, and function as a low-pass filter and a high-frequency signal level detector. With this configuration, the output voltage can be reduced as the frequency of the reproduction clock increases. When the output voltage is outside the allowable range of the reproduction clock frequency, a device for notifying the fact may be added.

Next, the output waveform variable buffer 107 is configured, for example, as shown in FIG. 8, receives the outputs of the frequency / voltage converter 108 and the power supply voltage supplier 109, and converts the waveform of the second logic signal. The data signal thus obtained is transmitted via the transmission path. In FIG. 8, the output waveform variable buffer 107 includes a variable resistor 801, a resistance value control signal generator 802, and an amplifier (operational amplifier) 803.

The resistance control signal generator 802 has a frequency / frequency
The variable resistor 8 according to the output voltage of the voltage converter 108
Control the resistance value of 01. That is, the logic circuit 106
The second logic signal input from (FIG. 11 (f))
Is limited by the variable resistor 801 according to the output voltage of the frequency / voltage converter 108, and is input to the + input terminal of the amplifier 803. At the-input terminal of the amplifier 803,
The intermediate voltage of the output signal of the logic circuit 106 is input. Power supply for amplifier 803 (high potential power supply, low potential power supply)
Are supplied from the power supply voltage supplier 109.

The output signal of the amplifier 803 is shown in FIG.
The waveform becomes as shown in (1), and the rising / falling transition time is inversely proportional to the resistance value of the variable resistor 801. By adopting the variable output waveform buffer 107, the waveform of the data signal transmitted via the transmission line can be made variable according to the clock frequency. Rise of the data signal /
By controlling the fall transition time to be long when the clock frequency is low, the output current can be saved and the high frequency component of the data signal can be reduced.

Next, the power supply voltage supplier 109 is constructed, for example, as shown in FIG. 10, and the power supply required for the output waveform variable buffer 107 is based on the output (digital value and clock amplitude value) of the A / D converter 102. Generate and supply.

In FIG. 10, switches 1001-10
04, switches 1013 to 1016, switch 1021
1024 and the switches 1033 to 1036 perform the operation of closing only when the control signal is at a high level.

The buffers 1005 to 1008 are Schmitt trigger buffers. Inverter 1025-1
Reference numeral 028 is a Schmitt trigger inverter. Amplifiers 1010 to 1012, amplifier 1017, amplifier 10
30 to 1032 and the amplifier 1037 are gain 1 analog buffers.

The operation will be described. Switches 1001 to 1004, resistors, capacitors, buffers 1005
In the rectifier circuit constituted by ˜1008, when the input digital signals (Vd1, Vd2, Vd3, Vd4) are at the high level of the clock signal, the ratio of the high level is determined. The buffers 1005 to 1008 close the switches 1013 to 1016, respectively, when the high level rate is equal to or higher than the determination voltage. As a result, the high potential power source is output from the amplifier 1017.

Similarly, in the rectifier circuit composed of the switches 1021 to 1024, resistors, capacitors, and inverters 1025 to 1028, the input digital signals (Vd8, Vd
When d7, Vd6, Vd5) is the low level of the clock signal, the ratio of the low level is determined. Inverter 1025-1
028 closes the switches 1033 to 1036 when the low level rate is equal to or higher than the determination voltage. as a result,
A low potential power source is output from the amplifier 1037.

By adopting this power supply voltage supplier 109, the voltage of the data signal transmitted via the transmission line can be made substantially equal to the voltage of the clock signal. By making the voltage of the data signal equal to the voltage of the clock signal, the voltage of the data signal of the entire system can be made uniform.

The operation of the transmitting / receiving apparatus configured as above will be described below with reference to FIGS. Note that FIG. 12 is a flowchart showing the control procedure of the transmission / reception device.

First, in FIG. 1, the clock signal receiving amplifier 101 outputs the waveform of the clock signal input via the transmission line to the A / D converter 102 without changing the waveform. The A / D converter 102 outputs a digital signal corresponding to the voltage of the input clock signal together with the amplitude value of the clock signal, the clock signal shaper 103, the power supply voltage supplier 104, the judgment voltage variable buffer 105, and the power supply voltage supplier 109. And output to.

The clock signal shaper 103 reproduces the clock signal based on the logic signal corresponding to the rising / falling detection signal of the clock signal and outputs it to the logic circuit 106 and the frequency / voltage converter 108. The power supply voltage supplier 104 supplies necessary power to the clock signal receiving amplifier 101 and the A / D converter 102 based on the amplitude of the clock signal.

The variable judgment voltage buffer 105 judges the magnitude relationship of the data signal received via the transmission line based on the judgment voltage determined based on the amplitude of the clock signal, generates the first logic signal, and outputs it to the logic circuit 106. Output. The logic circuit 106 receives the regenerated clock signal and the first logic signal, performs necessary processing, generates a second logic signal, and outputs the output waveform variable buffer 10
Output to 7.

The frequency / voltage converter 108 outputs to the output waveform variable buffer 107 a voltage that changes according to the frequency of the reproduced clock signal. Power supply voltage supply 1
09 supplies the output waveform variable buffer 107 with necessary power based on the amplitude information of the clock signal. The variable output waveform buffer 107 is data obtained by waveform-converting the second logic signal under the condition determined based on the input voltage from the frequency / voltage converter 108 and the power supply voltage supplied from the power supply voltage supply 109. The signal is transmitted via the transmission path.

Next, the control procedure of the transmitter / receiver will be described. In FIG. 12, in step ST1201,
As the condition of the clock signal input via the transmission line,
The maximum / minimum voltage is set in the power supply voltage supply 104, and the maximum / minimum frequency is set in the frequency / voltage converter 108.

At step ST1202, initial values of high / low power supply voltages are set in the clock signal receiving amplifier.

In step ST1203, the input of the clock signal is started.

In step ST1204, the clock signal shaper 10 calculates the digital signal corresponding to the voltage of the clock signal and the amplitude of the clock signal in the A / D converter 102.
3, the power supply voltage supplier 104, and the judgment voltage variable buffer 10
5 and the power supply voltage supplier 109.

In step ST1205, it is determined whether the amplitudes Va1 and Va8 of the clock signal input to the power supply voltage supplier 104 are within the maximum / minimum voltage range. In step ST1205, it is determined whether or not the frequency of the reproduction clock signal input to the frequency / voltage converter 108 is within the minimum / maximum frequency range. If it is within the range, step S
When it is out of the range, the process proceeds to T1206 and step ST120.
Go to 8.

In step ST1206, the judgment voltage variable buffer 105 judges the magnitude relation between the data signal received via the transmission line and the judgment voltage determined on the basis of the amplitudes Va1 and Va8 of the clock signal, and the first judgment is made. Generate a logic signal.

In step ST1207, the variable output waveform buffer 107 determines the logic circuit 10 under the conditions determined based on the voltage input from the frequency / voltage converter 108 and the power supply voltage supplied from the power supply voltage supply 109.
The second logic signal input from 6 is subjected to waveform conversion, and the obtained data signal is transmitted via the transmission path.

In step ST1208, it is determined whether or not the voltage condition and the frequency condition of the clock signal and the initial value of the high / low power supply voltage of the clock signal receiving amplifier 101 are changed. When changing, step ST1201
If not changed, the process proceeds to step ST1209.

In step ST1209, it is determined whether the clock signal input via the transmission line needs to be constantly monitored. If you want to constantly monitor the clock signal, step ST
Returning to 1204, if constant monitoring is not necessary, the control ends.

As described above, according to the present embodiment, the voltage condition of the judgment voltage for judging the level of the received data and the judgment result based on the amplitude and frequency of the clock signal input via the transmission line are used. Since it is possible to add control to the waveform condition of the output data generated by, the transmission / reception conditions can be automatically optimized according to the voltage change of the received signal.

Further, the voltage condition and the frequency condition and the power supply voltage of the clock signal receiving amplifier can be reset with reference to the clock signal input through the transmission line, and the power consumption of the clock signal receiving amplifier can be reduced.

Further, the judgment voltage can have a hysteresis characteristic, and the influence of noise of the data signal received via the transmission line is reduced.

Further, the voltage of the data signal transmitted by the variable output waveform buffer 107 can be made substantially equal to the voltage of the clock signal, and the voltage of the data signal of the entire system can be made uniform.

Further, since the waveform of the data signal transmitted by the variable output waveform buffer can be made variable according to the clock frequency, it is possible to save current and reduce high frequency components of the signal.

(Embodiment 2) FIG. 13 is a block diagram showing a configuration of an information processing apparatus according to Embodiment 2 of the present invention.

In FIG. 13, this information processing apparatus includes a plurality of functional units 1300-1 to 300-N, a clock signal generator 1302, and an inter-functional unit bus line 130.
3 and 3. Multiple functional units 1300-1 to 13
00-N has the same configuration, and is configured by a functional block 1304 that processes a data signal in each functional unit and an input / output unit 1305 that corresponds to the transmission / reception device described in the first embodiment.

A plurality of functional units 1300-1 to 130
The input / output units 1305 of 0-N transmit and receive data via the inter-functional unit bus line 1303. The clock signal generated by the clock signal generator 1302 is the bus line 1 between the functional units.
Multiple functional units 1300-1 to 13 through 303
00-N is supplied to each input / output unit 1305. In this information processing apparatus, in each of the plurality of functional units 1300-1 to 300-N, the functional block 1304 processes the data signal in its own functional unit and outputs the data signal to be passed to another functional unit to the input / output unit 1305. Output to the inter-functional unit bus line 1303, and the input / output unit 1305 receives and processes a data signal acquired from another functional unit via the inter-functional unit bus line 1303. At this time, the input / output unit 130
As described in the first embodiment, 5 controls the voltages and waveforms of the judgment voltage variable buffer 105 and the output waveform variable buffer 107 on the basis of the amplitude and frequency of the clock signal output from the clock signal generator 1302. Add.

As described above, according to the present embodiment, the transmission / reception device according to the first embodiment includes the input / output unit corresponding to the transmission / reception device according to the first embodiment. , Control can be added to the voltage condition of the judgment voltage for judging the level of the received data and the waveform condition of the output data generated by the judgment result, with reference to the amplitude and frequency of the clock signal input via the transmission path. Therefore, it is possible to obtain an information processing apparatus capable of automatically optimizing the transmission / reception conditions according to the voltage change of the received signal.

Since the transmission / reception conditions can be automatically optimized based on the input clock signal, it is possible to flexibly deal with addition and deletion of functional units.

(Embodiment 3) FIG. 14 is a block diagram showing a configuration of an information communication system according to Embodiment 3 of the present invention.

In FIG. 14, this information communication system includes a plurality of information processing devices 1400-1 to 1400-N, a clock signal generator 1402 and an inter-device transmission path 1403. Information processing devices 1400-1 to 1400
-N has the same configuration, and is configured by an information processing unit 1404 that processes a data signal in each information processing device and an external interface 1405 corresponding to the transmission / reception device described in the first embodiment.

A plurality of information processing devices 1400-1 to 140
The external interfaces 1405 of 0-N transmit and receive data via the inter-device transmission path 1403. The clock signal generated by the clock signal generator 1402 is supplied to the external interfaces 1405 of the plurality of information processing devices 1400-1 to 1400-N via the inter-device transmission path 1403. In the information processing system, in each of the plurality of information processing devices 1400-1 to 1400-N,
The information processing unit 1404 processes a data signal in its own information processing apparatus and outputs a data signal to be passed to another information processing apparatus from the external interface 1405 to the inter-device transmission path 1403. A data signal acquired from another information processing apparatus is received via 1403 and processed. At this time, as described in the first embodiment, the external interface 1405 uses the voltages of the judgment voltage variable buffer 105 and the output waveform variable buffer 107 based on the amplitude and frequency of the clock signal output from the clock signal generator 1402. , Add control to the waveform.

As described above, according to the present embodiment, since the external interface corresponding to the transmitting / receiving apparatus according to the first embodiment is provided, the transmitting / receiving apparatus according to the first embodiment operating as the external interface transmits the data. Since the control can be added to the voltage condition of the judgment voltage for judging the level of the received data and the waveform condition of the output data generated by the judgment result, with reference to the amplitude and frequency of the clock signal input via the path. An information communication system capable of automatically optimizing transmission / reception conditions according to a change in voltage of a received signal can be obtained.

Further, since the transmission / reception conditions can be automatically optimized on the basis of the input clock signal, it is possible to flexibly deal with the addition / deletion of information processing devices and the extension / shortening of transmission paths between devices. be able to.

Furthermore, when the waveform of the data signal cannot be optimized, it can be determined that the system configuration is inappropriate.

[0092]

As described above, according to the present invention,
Control can be added to the voltage condition of the determination voltage for determining the level of the received data and the waveform condition of the output data generated based on the determination result, with reference to the amplitude and frequency of the clock signal input via the transmission path. Therefore, it is possible to realize a transmission / reception method and a transmission / reception device that automatically optimize transmission / reception conditions according to a voltage change of a received signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a transmission / reception device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of a clock signal receiving amplifier shown in FIG.

3 is a configuration diagram showing an example of the A / D converter shown in FIG.

FIG. 4 is a configuration diagram showing an example of the clock signal shaper shown in FIG.

FIG. 5 is a configuration diagram showing an example of the power supply voltage supply device shown in FIG.

FIG. 6 is a configuration diagram showing an example of a judgment voltage variable buffer shown in FIG.

7 is a configuration diagram showing an example of a variable judgment voltage buffer shown in FIG.

8 is a configuration diagram showing an example of the output waveform variable buffer shown in FIG.

9 is a configuration diagram showing an example of the frequency / voltage converter shown in FIG.

10 is a configuration diagram showing an example of the power supply voltage supply device shown in FIG.

FIG. 11 is a timing chart for explaining the operation of each part of the transmission / reception device shown in FIG.

FIG. 12 is a flowchart for explaining a control procedure of the transmission / reception device shown in FIG.

FIG. 13 is a block diagram showing a configuration of an information processing device according to a second embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of an information communication system according to a third embodiment of the present invention.

FIG. 15 is a block diagram of a conventional transmission / reception device.

[Explanation of symbols]

101 Clock signal receiving amplifier 102 A / D converter 103 Clock signal shaper 104,109 power supply voltage supply 105 Judgment voltage variable buffer 106 logic circuit 107 Output waveform variable buffer 108 Frequency / voltage converter

Claims (11)

[Claims] 1. A receiving amplifier that amplifies a clock signal input through a transmission line with a gain of 1, a clock signal output by the receiving amplifier is converted into a digital signal, and the digital signal is amplitude information of the clock signal. An A / D converter that outputs the same, a first power supply voltage supplier that determines a power supply voltage to be supplied to the reception amplifier from amplitude information of the clock signal, a clock signal shaper that reproduces a clock signal from the digital signal, A logic that determines the high level / low level of a data signal received via a transmission line with a determination voltage determined based on the amplitude information of the clock signal, and generates a logic signal based on the determination result and the reproduced clock signal. A signal generator and a frequency / voltage converter for converting the frequency of the regenerated clock signal into a voltage; An output waveform converter for converting a waveform of a logic signal under a condition determined based on a power supply voltage and an output voltage of the frequency / voltage converter to generate a data signal to be transmitted through a transmission line, and an amplitude of the clock signal. And a second power supply voltage supplier that determines the power supply voltage to be supplied to the output waveform converter from information. 2. The transmitter / receiver according to claim 1, wherein the determination voltage determined by the logic signal generator has a hysteresis characteristic. 3. The transmitter / receiver according to claim 1, wherein the output waveform converter makes the voltage of the data signal to be transmitted substantially equal to the voltage of the clock signal. 4. The output waveform converter according to claim 1, wherein the waveform of the data signal to be transmitted is variable according to the frequency of the reproduction clock signal. Transceiver. 5. The output waveform converter lengthens the rising / falling transition time of the data signal to be transmitted when the frequency of the reproduction clock signal is low. The transmission / reception device according to Crab. 6. A step of setting the voltage condition of the first power supply voltage supplier based on the amplitude information of the clock signal from the transmission line and setting the frequency condition to the frequency / voltage converter, and gaining the clock signal from the transmission line. Setting the power supply voltage of the receiving amplifier to be amplified by 1 in the first power supply voltage supplier;
Based on the amplitude information of the clock signal, the step of digitally converting the clock signal output by the receiving amplifier, outputting the converted digital signal together with the amplitude information of the clock signal, the step of regenerating the clock signal from the digital signal, Determining whether the voltage is within the range of the voltage condition, determining whether the frequency of the reproduced clock signal is within the range of the frequency condition, and determining that the clock signal is within the voltage condition and within the frequency condition. In this case, the high level / low level of the data signal received via the transmission line is determined by the determination voltage determined from the amplitude information of the clock signal, and a logic signal is generated from the determination result and the reproduced clock signal. The power supply voltage and the frequency of the recovered clock signal are converted in the frequency / voltage converter. A step of converting the waveform of the logic signal under a condition determined based on the voltage and generating a data signal to be transmitted through a transmission line; and a power supply voltage determined based on amplitude information of the clock signal as a second power supply voltage. A transmitting / receiving method comprising: a step of setting in a feeder. 7. When the clock signal is out of the range of the voltage condition and the frequency condition, a step of resetting the voltage condition and the frequency condition and the power supply voltage of the receiving amplifier to the first power supply voltage supplier is provided. 7. The transmission / reception method according to claim 6, wherein: 8. The transmission / reception method according to claim 7, wherein when the voltage of the clock signal is out of the hardware control range, the first power supply voltage supplier notifies the outside of the control range. 9. The frequency / voltage converter notifies that the frequency of the reproduction clock signal is out of the control range when the frequency is out of the hardware control range.
The sending and receiving method described in. 10. A plurality of functional units and a clock signal generator are connected via a bus line between the functional units,
An information processing device in which an input / output unit of each functional unit transmits / receives data via the inter-functional unit bus line, wherein the plurality of functional units serve as the input / output unit. An information processing apparatus, comprising: the transmitting / receiving apparatus described in 1. 11. An information communication system in which a plurality of information processing devices and a clock signal generator are connected via an inter-device transmission line, and an external interface section of each information processing device transmits and receives data via the inter-device transmission line. In the system, the plurality of information processing devices include the transmission / reception device according to any one of claims 1 to 5 as the external interface unit.