JP2003110055A - Surface-packaging-type semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily recognize the installation direction to a packaging substrate and the terminal number of each external terminal. SOLUTION: A bump 16 used as an external terminal formed in a semiconductor package 10 is formed by an asymmetric pattern where the direction of the package 10 is fixed uniquely. Concretely speaking, for example, a dummy terminal 17 is formed near a specific external terminal (a first terminal 16a), thus easily recognizing that the terminal that is positioned near the dummy terminal 17 is the first terminal 16a, and at the same time easily mounting the package to a packaging substrate with a proper direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package having a size substantially equal to that of a semiconductor chip and having a plurality of external terminals electrically connected to the semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices have been mounted in electronic devices such as mobile phones and various PDA (Personal Digital Assistant) devices. 2. Description of the Related Art In recent years, semiconductor devices have been required to be further miniaturized, thinned, and lightened to improve mounting efficiency in order to cope with the reduction in size and weight of electronic devices.

As such a semiconductor device, there is provided a so-called surface mount type semiconductor package in which mounting efficiency is improved by arranging external terminals two-dimensionally.

The surface-mount type semiconductor package has a semiconductor element formed on one main surface of a wiring board made of a ceramic material or a resin material, and the other main surface of the wiring board has input / output terminals and circuits of the semiconductor element. A large number of external terminals connected to the pattern through holes are formed. Since such a surface mount semiconductor package can be formed in a size substantially equal to that of a semiconductor chip, a chip size package (CSP:
Chip Size Package) is also called, it is possible to significantly improve the mounting efficiency compared to the package of the conventional structure.

As a chip size package,
A PGA (Pin Grid Array) semiconductor package in which a large number of pin terminals forming external terminals are arranged in a grid pattern on the bottom surface of a wiring board on which semiconductor elements are mounted, or arranged in a grid pattern. There is a BGA (Ball Grid Array) semiconductor package in which external terminals are formed by solder balls. As the chip size package, there is a wafer level CSP formed by forming an external extraction electrode portion on a semiconductor chip without using a wiring substrate and sealing the surface with a resin.

[0006]

By the way, the surface mount type semiconductor package is formed in the same size as the semiconductor chip as described above, and since the size of the semiconductor chip has been reduced more and more in recent years, for example, in each of the vertical and horizontal directions. 1.0 m
It is formed in a very small size of about m and 0.5 mm.

Therefore, for example, characters or symbols (hereinafter referred to as markings) indicating the direction of attachment to a mounting board of an electronic device or the terminal number of each external terminal are printed on the surface-mounting type semiconductor package. It is very difficult to describe due to such reasons. However, if such a marking is not described, it may be attached to the mounting substrate in the wrong direction, which may damage the package or the semiconductor element inside, or the electronic device to be mounted may not operate normally. Problems such as not working will occur.

Therefore, the present invention has been made in view of the above-mentioned conventional circumstances, and is attached to a mounting substrate even when it is formed in a small size where it is difficult to describe characters and symbols. An object of the present invention is to provide a surface-mount type semiconductor package capable of easily identifying the orientation and the terminal number of each external terminal.

[0009]

A surface mount semiconductor package according to the present invention has a size substantially equal to the size of a semiconductor chip, and has a plurality of external terminals electrically connected to the semiconductor chip. In the surface mount type semiconductor package formed as described above, the external terminals as a whole are formed in an asymmetrical arrangement pattern in which the orientation of the package is uniquely determined.

In the surface mount semiconductor package according to the present invention configured as described above, the external terminals are formed in an asymmetrical layout pattern in which the orientation of the package is uniquely determined. Even if it is formed in a size that is difficult to read, by reading the external terminals, it is possible to easily discriminate the mounting direction on the mounting board and the terminal number of each external terminal.

As a concrete method for realizing the above-mentioned asymmetrical layout pattern, for example, a dummy terminal is formed in the vicinity of a predetermined external terminal, or a predetermined external terminal is different from other external terminals. It may be formed with a terminal diameter, or a predetermined external terminal may be formed at a position deviated from a predetermined reference terminal position. Further, for example, a dummy terminal is formed on the surface on which the external terminal is formed, and a predetermined character pattern is formed by the external terminal and the dummy terminal, whereby the external terminal has an asymmetrical arrangement pattern as a whole. It may be present.

Further, the external terminals are formed in a layout pattern corresponding to the layout pattern of the electrode terminals formed on the mounting board on which the package is mounted, and when mounted in a predetermined direction on the mounting board. It is desirable that only all the external terminals are connected to the electrode terminals. Accordingly, when the surface mount semiconductor package according to the present invention is mounted on the mounting board, even if the surface mounting type semiconductor package is mounted in the wrong orientation, the external terminals and the electrode terminals of the mounting board are not electrically connected. It is possible to prevent the semiconductor element formed in the surface mount type semiconductor package and various other elements arranged on the mounting board from being damaged.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, a case where the present invention is applied to the semiconductor package 10 as shown in FIG. 1 will be described.

As shown in FIG. 1, the semiconductor package 10 has semiconductor elements, circuit patterns, etc. formed on one main surface of a silicon substrate 11, and an insulating layer is formed on the side on which these semiconductor elements, circuit patterns are formed. Is formed as a polyimide layer 12. A rewiring layer 13 is formed on the polyimide layer 12 as a conductive layer that is through-hole connected to the input / output terminals of the semiconductor element formed on the silicon substrate 11 and the circuit pattern. A post electrode 14 made of a conductive material is formed on the surface 13. The polyimide layer 12, the rewiring layer 13, and the post electrode 14 are filled with a sealing member 15 made of a resin material on the side of the silicon substrate 11 on which the semiconductor element and the circuit pattern are formed.

Here, the redistribution layer 13 is the silicon substrate 1
It is provided to electrically connect the input / output terminals and the circuit pattern of the semiconductor element formed on the first electrode to the post electrode 14 formed at a predetermined position. Further, the end surface of the post electrode 14 constitutes substantially the same surface as the sealing member 15, and faces the outside from the sealing member 15.

In the semiconductor package 10, bumps 16 as external terminals are formed on the post electrodes 14. That is, the semiconductor package 10 shown in FIG.
External terminals electrically connected to the semiconductor elements formed on the silicon substrate 11 via the rewiring layer 13 and the post electrodes 14 are formed by the bumps 16 without using a wiring substrate, and so-called wafer level CSP is used. Is configured as.

In the semiconductor package 10 configured as described above, as shown in FIG. 1, the bumps 16 and the circuit are formed by the solder 22 with the bumps 16 placed on the circuit patterns 21 formed on the mounting substrate 20. The pattern 21 is joined and electrically connected.

Next, the layout pattern of the external terminals in the semiconductor package 10 will be described. In the semiconductor package 10, the bumps 16 as external terminals are
The package is formed in an asymmetrical layout pattern in which the orientation of the package is uniquely determined. This makes it easy to determine the orientation to attach to the mounting board and the terminal number of each external terminal by reading the external terminals, even if they are formed in a small size that makes it difficult to write characters and symbols. It is possible to do.

Here, the asymmetrical layout pattern of the external terminals in the semiconductor package 10 may have various configurations. In the following, a specific example of the layout pattern will be sequentially described with reference to the drawings. And In the following, it is assumed that the external terminals in the semiconductor package 10 are formed with the arrangement pattern as shown in FIG. 2 as a basic shape. That is, in the semiconductor package 10, as shown in FIG. 2, the bumps 16 as external terminals have a total of four bumps, namely the first terminal 16a, the second terminal 16b, the third terminal 16c, and the fourth terminal 16d. Assume that they are installed.

However, in the semiconductor package 10, the number of external terminals is not particularly limited and may be any number. 2 is a plan view of the semiconductor package 10 as seen from the bottom surface side, that is, the side where the bumps 16 are formed.

As a first example of the layout pattern of the external terminals in the semiconductor package 10, as shown in FIG.
An example is a case where a dummy terminal 17 that is not electrically connected to a semiconductor element or the like is formed in the vicinity of a predetermined external terminal (for example, the first terminal 16a).

As a result, the arrangement pattern of the external terminals can be made asymmetric, and the terminal located in the vicinity of the dummy terminal 17 can be determined to be the first terminal 16a. Therefore, by reading the arrangement pattern of the external terminals, it is possible to easily determine the mounting direction on the mounting board and the terminal number of each external terminal.

As a second example of the layout pattern of the external terminals in the semiconductor package 10, as shown in FIG. 4, a predetermined external terminal (for example, the first terminal 16a) is used.
Other external terminals (for example, second to fourth terminals 16b to 16)
The case where the terminal diameter is different from that in d) can be mentioned. Although FIG. 4 illustrates a case where the terminal diameter of the first terminal 16a is larger than the other external terminals, the first terminal 16a has a smaller terminal diameter than the other external terminals. You may form with.

As a result, the arrangement pattern of the external terminals can be made asymmetric, and the first terminals having different terminal diameters can be used.
The terminal 16a can be easily distinguished from other external terminals. Therefore, by reading the arrangement pattern of the external terminals, it is possible to easily determine the mounting direction on the mounting board and the terminal number of each external terminal.

As a third example of the layout pattern of the external terminals in the semiconductor package 10, as shown in FIG. 5A, a predetermined external terminal (for example, the third terminal 16) is used.
There may be mentioned a case where d) is formed at a position deviated from the reference terminal position in the basic terminal pattern as shown in FIG.

As a result, the arrangement pattern of the external terminals can be made asymmetric, and the third terminal 16d formed at the displaced position can be easily distinguished from the other external terminals. Therefore, by reading the arrangement pattern of the external terminals, it is possible to easily determine the mounting direction on the mounting board and the terminal number of each external terminal.

At this time, as shown in FIG. 5B, the mounting substrate 20 to which the semiconductor package 10 is attached is mounted as shown in FIG.
It is desirable that the electrode terminals 22 are formed in a pattern corresponding to the arrangement pattern of the external terminals shown in (a). As a result, when the semiconductor package 10 is mounted on the mounting substrate in the correct direction, all the external terminals can be connected to the electrode terminals 22 of the mounting substrate 20 as shown in FIG. As shown in (b) and FIG. 6 (c),
When the semiconductor package 10 is mounted on the mounting board in a state of being rotated in the direction of 90 ° or 180 °,
It is possible to prevent all the external terminals and the electrode terminals 22 of the mounting substrate 20 from being electrically connected.

As a result, even when the semiconductor package 10 is mounted on the mounting substrate 20 in the wrong orientation, the semiconductor element inside the package is damaged or another semiconductor element mounted on the mounting substrate 20 is damaged. It is possible to prevent such a situation from being adversely affected.

As a fourth example of the layout pattern of the external terminals in the semiconductor package 10, as shown in FIG. 7, dummy terminals 17 are formed on the external terminal forming surface and the first to fourth terminals 16a are formed. A predetermined character pattern may be formed by ˜16d and the dummy terminal 17. In addition,
In FIG. 7, a pattern indicating the letter “M” indicating that this semiconductor package 10 is manufactured by “Mitsumi Electric Co., Ltd.” is provided with external terminals and dummy terminals 1.
It is composed of 7 and.

As a result, the arrangement pattern of the external terminals can be made asymmetric, and the orientation of the semiconductor package 10 and the terminal number of each external terminal can be confirmed by checking the character pattern on the surface on which the external terminals are formed. It is possible to easily distinguish such as. Although the semiconductor package 10 of the present embodiment has been described as the wafer level CSP, the same effects can be obtained by the first to fourth embodiments with respect to other CSPs.

[0031]

In the surface mount type semiconductor package according to the present invention, the layout pattern of the external terminals and the product information are associated with each other. Therefore, by reading the layout pattern of the external terminals, the information related to the product can be obtained. I can know.

Therefore, even if the characters or symbols are formed in a small size that is difficult to describe, the product information such as the manufacturer name, the manufacturing line number, the manufacturing date, the product name, or the product number is displayed. It is possible to surely know the information, improve the quality control of the product, and surely prevent accidental attachment at the time of attachment to an electronic device or the like.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor package shown as an embodiment of the present invention.

FIG. 2 is a schematic view showing a basic arrangement pattern of external terminals formed on the bottom surface side of the same semiconductor package.

FIG. 3 is a diagram showing an arrangement pattern of external terminals as a first example to which the present invention is applied, and is a schematic diagram showing a case where dummy terminals are arranged in the vicinity of predetermined external terminals.

FIG. 4 is a diagram showing an arrangement pattern of external terminals as a second example to which the present invention is applied, and is a schematic diagram showing a case where a predetermined external terminal is formed with a terminal diameter different from that of other external terminals. .

FIG. 5 is a diagram showing an arrangement pattern of external terminals as a third example to which the present invention is applied, and is a schematic diagram showing a case where a predetermined external terminal is formed at a position displaced from a reference terminal position.

FIG. 6 is a schematic diagram showing an electrical connection state when this semiconductor package is attached to a mounting substrate in a correct orientation and an incorrect orientation when external terminals are formed in the arrangement pattern shown in FIG. .

FIG. 7 is a diagram showing an arrangement pattern of external terminals as a fourth example to which the present invention is applied, in which a predetermined character pattern (“M” in the figure) is formed by dummy terminals arranged on a surface on which external terminals are formed. FIG. 6 is a schematic diagram showing a case where a letter-shaped pattern) is formed.

[Explanation of symbols]

10 Semiconductor package 11 Silicon substrate 12 Polyimide layer 13 Rewiring layer 14 Post electrode 15 Sealing member 16 bumps (external terminals) 17 dummy terminals 20 mounting board

Claims (6)

[Claims] 1. A surface mount semiconductor package having a plurality of external terminals that are substantially the same size as a semiconductor chip and that are electrically connected to the semiconductor chip. A surface mount semiconductor package, wherein the package is formed in an asymmetrical arrangement pattern in which the orientation of the package is uniquely determined. 2. The surface mounting type according to claim 1, wherein the dummy terminal is formed in the vicinity of a predetermined external terminal, so that the external terminal has an asymmetrical arrangement pattern as a whole. Semiconductor package. 3. The predetermined external terminal is formed with a terminal diameter different from that of the other external terminals, so that the external terminals have an asymmetrical arrangement pattern as a whole. Surface mount semiconductor package. 4. The predetermined external terminal is formed at a position deviated from a predetermined reference terminal position, so that the external terminal has an asymmetrical arrangement pattern as a whole. The surface mount semiconductor package described. 5. The external terminals are formed in a layout pattern corresponding to a layout pattern of electrode terminals formed on a mounting board on which the package is mounted, and when mounted in a predetermined direction on the mounting board. 5. The surface mount semiconductor package according to claim 4, wherein only all the external terminals are connected to the electrode terminals. 6. A layout pattern in which a dummy terminal is formed on a surface on which the external terminal is formed, and a predetermined character pattern is formed by the external terminal and the dummy terminal, so that the external terminal is asymmetrically arranged as a whole. The surface mount semiconductor package according to claim 1, wherein