JP2003109973A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a heterostructure field-effect transistor which comprises a thin barrier wall and whose high electron concentration is realized without spoiling high electron mobility. SOLUTION: In a GaN channel Layer 202, a region B whose distance Z from an interface with an AlXGa1- XN barrier layer 201 is Z1 to Z1 +dB is doped with an n-type dopant such as silicon or the like. Z1 represents a value larger than the width Z0 (where 30Å<=Z0 <=40Å) of a region in which two-dimensional electrons are gathered. Electrons supplied from the n-type dopant such as the silicon or the like inside the region B are drawn to a heterointerface by a strong channel electric field so as to contribute to conduction as the two-dimensional electrons. Consequently, the electrons are not subjected directly to an impurity ionization scattering operation due to the dopant, and the high electron mobility of the semiconductor device is maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device made of an ultrahigh frequency compound having high temperature, high output and high breakdown voltage.

[0002]

2. Description of the Related Art Generally, a heterostructure field effect transistor (heterostructure field effect transistor) using a compound semiconductor is used.
In ct Transistor (HFET), a transistor operation is performed by doping an n-type dopant such as silicon into the barrier layer on the substrate surface side of the channel layer.
Dimensional electrons are supplied. In this way, the modulation doping in which the barrier layer is doped instead of the inside of the channel makes it possible to obtain a high electron mobility that is advantageous for transistor operation.

In order to improve the operation of the transistor, it is effective to reduce the thickness of the barrier layer so that the two-dimensional electrons exist closer to the surface. Currently in practical use (In)
In a GaAs HFET, 2 that can be accommodated in the channel
Dimensional electron concentration is 1 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² c
It is about m ⁻² . Even if the thickness of the barrier layer is reduced to about 100 to 150Å or less, 2 × 10 ¹⁸ cm ⁻³ to 1
By doping the barrier layer with a concentration of about 0 × 10 ¹⁸ cm ⁻³ , two-dimensional electrons can be supplied and the maximum two-dimensional electron concentration that can be accommodated in the channel can be realized.

On the other hand, HFETs (G
In an aN-based HFET), positive polarization charge is generated at the hetero interface between the channel layer and the barrier layer on the substrate surface side of the channel layer. As a result, 1 × 10 ¹³ cm ^{−2 to} 5
It becomes possible to accommodate a two-dimensional electron having a very high concentration of × 10 ¹³ cm ^{−2 in} the channel.

This GaN-based HFET is (In) GaAs
The characteristic point that is different from the system HFET is that 0.5 × 10 5 is obtained as a result of the presence of the above-mentioned polarization charge even without doping.
Two-dimensional electrons with a concentration of about ¹³ cm ^{−2 to} 2 × 10 ¹³ cm ⁻² are generated.

[0006]

In the GaN-based HFET, in order to realize the maximum two-dimensional electron concentration that can be accommodated in the channel, it is necessary to dope the barrier layer to supply electrons. . However, if the thickness of the barrier layer is reduced to 150 Å or less, since the two-dimensional electron concentration that can be originally accommodated in the channel is very high, even if the barrier layer is doped to supply electrons,
It is not possible to achieve the maximum electron density that can be accommodated.

As described above, in the conventional GaN-based HFET, when the electron barrier layer is thinned, the GaN-based HFET is
There was a problem that the potential for realizing high electron concentration originally possessed by could not be fully extracted.
This is because the maximum electron concentration that can be accommodated is (In) GaAs-based H
This is because a GaN-based HFET, which is about an order of magnitude larger than an FET, has a very high potential for high power operation.

The present invention has been made in view of the above problems, and its object is to provide a GaN-based HF.
An object of the present invention is to provide a semiconductor device having a thin barrier layer having a thickness of 150 Å or less, which is advantageous for transistor operation, and capable of realizing an original high electron concentration without impairing high electron mobility in ET.

[0009]

In order to achieve such an object, the invention as set forth in claim 1 provides a channel layer of a nitride on a substrate, and a substrate surface side closer to the substrate surface side than the channel layer. In the semiconductor device in which the first barrier layer is stacked, the channel layer is located within a range from an interface between the first barrier layer and the first barrier layer to a predetermined depth of 30 Å or more and 40 Å or less, and an n-type dopant. A first region whose doping concentration is suppressed to a predetermined concentration or less, and an n-type dopant at a doping concentration higher than the doping concentration of the first region, which is located closer to the surface of the substrate than the first region. And a second region that is doped.

The invention described in claim 2 is the same as claim 1.
In the semiconductor device described in the paragraph 1, the doping concentration of the first region is 1 × 10 ¹⁸ cm ⁻³ or less.

The invention described in claim 3 is the same as claim 1.
Alternatively, in the semiconductor device described in the paragraph 2, the doping concentration of the second region is 2 × 10 ¹⁸ cm ⁻³ or more.

The invention according to claim 4 is the same as claim 1.
The semiconductor device according to any one of 1 to 3,
Is characterized by being made of indium gallium nitride.

The invention described in claim 5 is the same as claim 1.
The semiconductor device according to any one of 1 to 3,
The region (1) is made of aluminum gallium nitride.

The invention described in claim 6 is the same as claim 1.
The semiconductor device according to any one of 1 to 5 is characterized in that a second barrier layer located on the side of the substrate opposite to the channel layer is further provided.

The invention described in claim 7 is the same as claim 6
In the semiconductor device described in the paragraph 1, the second barrier layer has a band gap larger than that of the channel layer.

The invention according to claim 8 is the same as claim 6
Alternatively, in the semiconductor device according to the seventh aspect, the second barrier layer may include a third region located within a range from an interface with the channel layer to a predetermined depth, and a surface of the substrate opposite to the third region. And a fourth region located on the side of the third region in which the doping concentration of the n-type dopant is suppressed to a predetermined concentration or less, and the doping concentration of the n-type dopant in the third region is the fourth region.
Is higher than the doping concentration of the region.

The invention according to claim 9 is the same as that of claim 8.
In the semiconductor device described in the paragraph 1, the doping concentration of the third region is 2 × 10 ¹⁸ cm ⁻³ or more.

Further, the invention according to claim 10 is the semiconductor device according to claim 8 or 9, characterized in that the doping concentration of the fourth region is 1 × 10 ¹⁸ cm ⁻³ or less. .

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

In the present invention, the heterostructure field effect transistor is provided on the side opposite to the substrate surface side from the region where the two-dimensional electrons travel.
“Selective back-doping” is performed to supply channel electrons by avoiding two-dimensional electrons. "Selective back-doping" utilizes (i) a small two-dimensional electron distribution width derived from the large polarization effect peculiar to the hetero interface of a GaN-based HFET and (ii) a strong channel electric field in the vertical direction of the substrate. .

FIG. 1 is a diagram showing a two-dimensional electron distribution and a channel potential shape in an AlGaN / GaN HFET having an Al composition of 0.15 calculated. In this figure, Al is formed only on the substrate surface side of the GaN channel.
The potential 101 of the field effect transistor having a single hetero structure having a GaN barrier layer, its two-dimensional electrons 104, and AlGaN also on the side of the GaN channel opposite to the substrate surface.
Potential 102 of a field effect transistor having a double hetero structure having a barrier layer and its two-dimensional electron 1
03 are shown respectively.

In both structures, the distribution width of two-dimensional electrons is 3
It is shown that it is as small as 0Å to 40Å, which is about one-third of that of GaAs-based HFETs, and that the channel electric field (gradient of triangular potential) is as large as 2-3 times that of GaAs-based HFETs. This characteristic is a characteristic that a large polarization charge of the order of 1 × 10 ¹³ cm ⁻² is generated at the AlGaN / GaN hetero interface (interface formed by the AlGaN channel layer and the GaN channel layer) to form a large electric field. Further, it is shown that the channel electric field is stronger in the double hetero structure than in the single hetero structure because there are two hetero interfaces.

In the GaN-based HFET, due to the characteristics (i) and (ii) shown in FIG. 1, even when doping is performed on the side of the substrate opposite to the region where two-dimensional electrons are present, the electrons are doped. It is possible to move to the vicinity of the hetero interface from the region where it was carried out and to exist as a two-dimensional electron. In the present invention, 30 Å near the hetero interface of the channel layer
Doping is performed while avoiding a region of ˜40 Å where two-dimensional electrons exist. This makes it possible to avoid a decrease in electron mobility due to ionized impurity scattering that may occur due to doping.

(First Embodiment) FIG. 2 is a diagram showing a layer structure of a heterostructure field effect transistor which is an example of a semiconductor device to which the present invention is applied. In this figure, the heterostructure field effect transistor is applied with a single heterostructure having an AlGaN barrier layer only on the substrate surface side of the GaN channel.

A buffer layer 203 is laminated on the substrate 204, and a GaN channel layer (GaN channel layer) 202 in which two-dimensional electrons are present is laminated on the buffer layer 203, which is closer to the substrate surface than the channel layer. Is Al _X Ga
_{The 1-X} N barrier layer 201 is laminated. Where Al
The composition X is an arbitrary value of 0 <X ≦ 1, and is Al _X Ga
_{The 1- XN} barrier layer 201 does not necessarily have to be constant.

On the substrate 204, sapphire, SiC, C
aN, Si, GaAs or the like is used. GaN, AlN, or AlGaN is used for the buffer layer 203.

_A region A having a layer thickness d _A in the Al _X Ga _1-X N barrier layer 201 is doped. here,
The structural parameters (that is, the layer thickness d _SC of the Schottky contact layer, the layer thickness d A of the region _A and the doping concentration and the layer thickness d _{SP of the} spacer layer) regarding the Al _X Ga _1-X N barrier layer 201 are arbitrary. This is because the action according to the present invention can be obtained for any of the above structural parameters. However, the action of the present invention is important in FIG. 2 in which the Al _X Ga _1-X N barrier layer 20 is used.
This is the case of the structure in which the thickness d _SC + d _A + d _{SP of 1} is 150 Å or less. In such a structure, area A
This is because a situation occurs in which the number of electrons that can be supplied from the device is less than the number of electrons that can be accommodated in the channel.

A depth-direction one-dimensional coordinate axis (Z axis) is defined with the anti-substrate surface direction being positive from the hetero interface between the Al _X Ga _{1 -X} N barrier layer 201. GaN channel layer 20
2, the distance Z from the hetero interface in the Z-axis direction is Z ₁
The region B located in the range of Z ₁ + d _B or less is doped with an n-type dopant such as silicon. Here, Z ₁ is the width Z ₀ (30 Å) of the region where the two-dimensional electrons gather.
≦ Z ₀ ≦ 40 Å).

The layer thickness d _{B of the} region _B is 0Å <d _B ≦ 2
The condition of 000Å is met. This is because when the layer thickness of the region B exceeds 2000 Å, electrons are present in the region B, and as a result, the region B does not function as a two-dimensional electron supply source, so that d _B > 2000 Å is unnecessary in the present invention. Depends on.

As described above, the fact that the region B which is a part of the GaN channel layer 202 is doped is a major feature of the heterostructure field effect transistor according to the present embodiment.

FIG. 3 is a diagram showing a channel potential structure when the heterostructure field effect transistor according to this embodiment is an AlGaN / GaN HFET. In this figure, the vertical axis is the potential (unit: eV)
Indicates. The electrons supplied from the n-type dopant such as silicon in the region B do not exist in the region B and contribute to conduction, but are attracted to the hetero interface by the strong channel electric field and move in the direction indicated by the arrow 302. Dimensional electron 30
3 contributes to conduction. Therefore, the electrons are not directly subjected to the impurity ionization scattering due to the dopant, and the high electron mobility is maintained.

Note that 0 ≦ Z <Z _{0 where} two-dimensional electrons exist
If the doping concentration is suppressed to be equal to or lower than the predetermined concentration, the region satisfying the condition can obtain the action of the present invention. That is, even if doping is performed in this region, if the doping concentration is a low concentration of 1 × 10 ¹⁸ cm ⁻³ or less, 10
High electron mobility of 00 cm ² / Vs or higher is maintained. In addition, the two-dimensional electron concentration is set to 1 × 1 by increasing the doping concentration of the region B to 2 × 10 ¹⁸ cm ⁻³ or higher.
It is possible to increase it by 0 ¹³ cm ⁻² or more. Further, the effect of the present invention can be obtained regardless of whether the region A is doped or not.

As described above, the heterostructure field effect transistor according to the present embodiment has a thin barrier layer (AlGaN channel layer) of 150 Å or less, which is advantageous for transistor operation, and has a high electron concentration that is originally attainable. It can be realized without impairing the high electron mobility.

(Second Embodiment) In the present embodiment, in the structure shown in the first embodiment, a region in which two-dimensional electrons run in the GaN channel layer 202 immediately below the Al _X Ga _1-X N barrier layer (that is, A part or the whole of 0 ≦ Z ≦ Z ₀ ) is an In _Y Ga _1-YN layer (0 ≦ Y ≦ 1).
Even in such a structure, the potential structure shown in FIG. 3 is realized, and the effect of the present invention is obtained.

(Third Embodiment) In the present embodiment, in the structure shown in the first embodiment, a region in which two-dimensional electrons of the GaN channel layer run immediately below the Al _X Ga _1-X N barrier layer (that is, 0 ≦). Part or all of Z ≦ Z ₀ ) is defined as an Al _Y Ga _1-YN layer (0 ≦ Y ≦ 1, Y <X). Even in such a structure, the potential structure shown in FIG. 3 is realized, and the effect of the present invention is obtained.

(Fourth Embodiment) FIG. 4 is a diagram showing a layer structure of a heterostructure field effect transistor which is an example of a semiconductor device to which the present invention is applied. In this figure, the heterostructure field effect transistor uses a double heterostructure having an AlGaN barrier layer having a larger bandgap than the GaN channel layer on the side of the GaN channel layer opposite to the substrate surface.

A buffer layer 405 is laminated on the substrate 406.
On the buffer layer 405._X3Ga_1-X3
An N barrier layer 404 is stacked to form Al_X3Ga_1-X3N obstacle
Al on the wall layer 404_X2Ga_1-X2N barrier layer 40
3 are stacked, Al_X2Ga _1-X2Of the N barrier layer 403
A GaN channel layer (Ga) on which two-dimensional electrons exist
N channel layer) 402 is laminated to form the GaN channel layer 4
Al on 02_X1Ga_1-X1N barrier layer 401
Layered. Here, the Al composition X1 is 0 <X1 ≦ 1.
The Al composition X2 is 0 <X ≦ 1.
The Al composition X3 is an arbitrary value satisfying 0 ≦ X3 ≦ 1. this
These values do not necessarily have to be constant.

On the substrate 406, sapphire, SiC, C
aN, Si, GaAs or the like is used. GaN, AlN, or AlGaN is used for the buffer layer 405.

_A region A having a layer thickness d _A in the Al _X1 Ga _{1 -X1} N barrier layer 401 is doped. Here, the structural parameters regarding the Al _X1 Ga _{1 -X1} N barrier layer 401 (layer thickness d _{SC of} the Schottky contact layer,
The layer thickness d _{A of the} region A, the doping concentration, and the spacer layer layer thickness d _SP ) are arbitrary. This is because the action according to the present invention can be obtained for any of the above structural parameters. However, the action of the present invention is particularly important,
In FIG. 4, the structure is such that the thickness d _SC + d _A + d _SP of the Al _X1 Ga _{1 -X1} N barrier layer 401 is 150 Å or less. This is because in such a structure, the number of electrons that can be supplied from the region A generally falls below the number of electrons that can be accommodated in the channel.

Al _X Ga _1-X1 N barrier layer 401 and Ga
A depth direction one-dimensional coordinate axis (Z axis) is defined with the anti-substrate surface direction being positive from the hetero interface with the N channel layer 402. In the GaN channel layer 402, Al _X Ga
Region B in which the distance Z from the interface with the _1-X N barrier layer 401 in the Z-axis direction is in the range of Z ₁ or more and Z ₁ + d _B or less.
Is doped with an n-type dopant such as silicon. Here, Z ₁ is the width Z of the region where the two-dimensional electrons gather.
It is a value larger than ₀ (30Å ≦ Z ₀ ≦ 40Å).

The layer thickness d _{B of the} region _B is 0 <d _B ≦ 20.
The condition of 00Å is satisfied. This is because when the layer thickness of the region B exceeds 2000 Å, electrons are present in the region B, and as a result, the region B does not function as a two-dimensional electron supply source, so that d _B > 2000 Å is unnecessary in the present invention. It depends.

In this figure, the region B is a GaN layer.
The channel layer 402 and Al on the surface opposite to the substrate_X2Ga_1-X2
The most common condition over both regions of N barrier layer 403
The region B is the GaN channel layer 40.
2 only Al on the opposite side of the substrate _X2Ga_1-X2N barrier layer
It is possible to obtain the action of the present invention with only 403,
Such structures are also included within the scope of the invention.

FIG. 5 is a diagram showing a channel potential structure when the heterostructure field effect transistor according to this embodiment is an AlGaN / GaN HFET. In this figure, the vertical axis is the potential (unit: eV)
Indicates. In the double hetero structure, Al on the surface opposite to the substrate side
_X2 for channel field due to the presence of Ga _1-X2 N barrier layer 403 is _enhanced, than the structure of the Al _{X2 Ga 1-X2} N barrier layer is not present FIG 2, more electron accumulation and conduction in the region B Less likely to happen. Therefore, area B
It becomes possible to perform higher concentration doping, and it is possible to enhance the electron supply capability to the channel.

The electrons supplied from the n-type dopant such as silicon in the region B do not exist in the region B and contribute to conduction, but are attracted to the hetero interface by the strong channel electric field and move in the direction indicated by the arrow 502. And contributes to conduction as the two-dimensional electrons 503. Therefore, the electrons are not directly subjected to the impurity ionization scattering by the dopant, and the high electron mobility is maintained.

Note that 0 ≦ Z <Z _{0 where} two-dimensional electrons exist
If the doping concentration is suppressed to be equal to or lower than the predetermined concentration, the region satisfying the condition can obtain the action of the present invention. That is, even if doping is performed, the doping concentration is 1 × 1.
At a low concentration of 0 ¹⁸ cm ⁻³ or less, 1000 cm ²
High electron mobility of / Vs or higher is maintained. Further, the two-dimensional electron concentration is set to 1 × 10 ¹³ cm by increasing the doping concentration of the region B to 2 × 10 ¹⁸ cm ⁻³ or higher.
^-It can be increased by ^-2 or more. Further, the effect of the present invention can be obtained regardless of whether the region A is doped or not.

With such a structure, a thin barrier layer (AlGaN channel layer) having a thickness of 150 Å or less, which is advantageous for transistor operation, is provided, and a high electron concentration which is originally attainable is obtained.
It can be realized without impairing the high electron mobility.

(Fifth Embodiment) In this embodiment, in the structure of the fourth embodiment, the substrate surface side Al _X1 Ga _{1-
The X1} N barrier layer 401 and the anti-substrate surface side Al _X2 Ga
GaN channel layer 40 between _1-X2 N barrier layer 403
2 of part or _all, In _{Y Ga 1-Y} N layers (0 ≦
Y ≦ 1). Even in such a structure, the potential structure shown in FIG. 5 is realized, and the effect of the present invention is obtained.

(Sixth Embodiment) In the present embodiment, in the structure of the fourth embodiment, the substrate surface side Al _X1 Ga _{1-
The X1} N barrier layer 401 and the anti-substrate surface side Al _X2 Ga
GaN channel layer 40 between _1-X2 N barrier layer 403
A part or all of 2 is an Al _Y Ga _1-YN layer (0 ≦
Y ≦ 1, Y <X1, Y <X2). Even in such a structure, the potential structure shown in FIG. 5 is realized,
The effect of the present invention can be obtained.

[0049]

As described above, according to the present invention,
In a GaN-based HFET, a thin barrier layer having a thickness of 150 Å or less, which is advantageous for transistor operation, can be provided, and an originally achievable high electron concentration can be realized without impairing high electron mobility.

[Brief description of drawings]

FIG. 1 is a diagram showing a two-dimensional electron distribution and a channel potential of Al _0.15 GaN / GaN.

FIG. 2 is a diagram showing a layer structure of a single hetero structure field effect transistor according to an embodiment of the present invention.

FIG. 3 is a diagram showing a channel potential of a single hetero structure field effect transistor according to an embodiment of the present invention.

FIG. 4 is a diagram showing a layer structure of a double hetero structure field effect transistor according to an embodiment of the present invention.

FIG. 5 is a diagram showing a channel potential of a double hetero structure field effect transistor according to an embodiment of the present invention.

[Explanation of symbols]

101, 102 potentials 103, 104 two-dimensional electrons 201 barrier layer 202 channel layer 203 buffer layer 204 substrate 301 barrier layer 302 arrow 303 two-dimensional electron 401 barrier layer 402 channel layer 403 barrier layer 405 buffer layer 406 substrate 502 arrow 503 two-dimensional electron A, B area d _A , d _B , d _SC , d _SP layer thickness

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F102 GB01 GC01 GD01 GJ02 GJ04                       GJ05 GJ10 GK04 GL04 GL08                       GL14 GL15 GM04 GM08 GM09                       GM10 GQ01 GQ03 GQ06

Claims (10)

[Claims] 1. A semiconductor device in which a nitride channel layer and a first barrier layer located on the substrate surface side of the channel layer are stacked on a substrate, wherein the channel layer is the first barrier layer. A first region located within a predetermined depth of 30 Å or more and 40 Å or less from the interface with the barrier layer and having an n-type dopant doping concentration suppressed to a predetermined concentration or less, and the first region. Located on the opposite side of the substrate from the first substrate,
N higher than the doping concentration of the region
And a second region doped with a type dopant. 2. The semiconductor device according to claim 1, wherein
The doping concentration of the first region is 1 × 10 ¹⁸ cm
^-3 or less, The semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 1, wherein the doping concentration of the second region is 2 × 10 5.
A semiconductor device having a size of ¹⁸ cm ⁻³ or more. 4. The semiconductor device according to claim 1, wherein the first region is made of indium gallium nitride. 5. The semiconductor device according to claim 1, wherein the first region is made of aluminum gallium nitride. 6. The semiconductor device according to claim 1, further comprising a second barrier layer located on the side of the substrate opposite to the channel layer. . 7. The semiconductor device according to claim 6,
The semiconductor device, wherein the second barrier layer has a bandgap larger than that of the channel layer. 8. The semiconductor device according to claim 6, wherein the second barrier layer has a third region located within a range from an interface with the channel layer to a predetermined depth, and And a fourth region which is located on the side opposite to the substrate surface side of the third region and in which the doping concentration of the n-type dopant is suppressed to a predetermined concentration or less, and the doping concentration of the n-type dopant in the third region is the fourth region. The semiconductor device is characterized in that the doping concentration is higher than the region. 9. The semiconductor device according to claim 8, wherein
The doping concentration of the third region is 2 × 10 ¹⁸ cm
^-3 or more, The semiconductor device characterized by the above-mentioned. 10. The semiconductor device according to claim 8, wherein the doping concentration of the fourth region is 1 × 10.
A semiconductor device having a size of ¹⁸ cm ⁻³ or less.