JP2003109395A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control individually power sources of a plurality of memory-macro and to transfer surely data required for each memory-macro. SOLUTION: A memory-macro 11 is arranged in a semiconductor chip 10. The memory-macro 11 has a fuse data latch circuit 14. The fuse data latch circuit 14 holds data supplied from a fuse circuit 12. Power sources are supplied individually to the memory-macro 11 and the fuse data latch circuit 14.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit,
For example, ASIC (Application Specific Integrated Ci)
rcuits), in particular, a memory macro that is embedded together with logic circuits.

[0002]

2. Description of the Related Art In recent years, for example, DR applied to ASIC
Memory macros such as AM (dynamic RAM) macros are being actively developed. This memory macro includes, for example, a plurality of basic unit blocks. Each basic unit block is composed of, for example, a memory cell array, a row decoder, a column decoder, a sense amplifier, a selection transistor that connects the sense amplifier and a data line, and the like.

Further, as shown in FIG. 6, the memory macro 1
1 has a fuse circuit 12 as a nonvolatile ROM. The fuse circuit 12 has a plurality of fuses (not shown), and information necessary for the memory macro to operate,
For example, the address of the defective cell in the memory cell array is stored. The data stored in the fuse circuit 12 is stored in the fuse circuit 1 when power is supplied to the memory macro 11.
The data is read from the data No. 2 and supplied to the fuse data latch circuit 14 via the fuse data transfer circuit 13 and held therein.

Even if the semiconductor chip has a plurality of memory macros, the configuration and operation of each memory macro are the same as in FIG. That is, when power is supplied to each memory macro, the data is read from the fuse in each memory macro and supplied to the fuse data latch circuit via the fuse data transfer circuit in the same macro.

[0005]

By the way, when the fuse is arranged in the memory macro, the wiring cannot be laid on the upper layer of the region where the fuse is arranged.
As described above, when the fuse is provided, the layout of the signal line and the power line is hindered. For this reason, it has been devised to arrange the fuse outside the memory macro.

FIG. 7 shows a case where the fuse circuit 12 and the fuse data transfer circuit 13 are provided outside the memory macro 11.

FIG. 8 specifically shows the structure shown in FIG. 7, and the same parts as those in FIG. 7 are designated by the same reference numerals.
In FIG. 8, the fuse circuit 12 is a fuse 12-
1, 12-2 to 12-i, data holding circuits 15-1 and 1
5-2 to 15-i and transfer transistors 16-1 and 16-2 to 16-i for transferring data. The data holding circuits 15-1, 15-2 to 15-i are
The fuses 12-1, 12-2 to 12-i and the transfer transistors 16-1 and 16-2 to 16-i are connected to each other.

Each data holding circuit is composed of, for example, a P-channel transistor Q1, an N-channel transistor Q2, and inverter circuits IV1 and IV2 as a latch circuit. The signal φ1 is applied to the gate of the transistor Q1.
Is supplied, and the signal φ2 is supplied to the gate of the transistor Q2. In addition, the transfer transistors 16-1 and 1
A signal φ3 is supplied to each of the gates 6-2 to 16-i.

The fuse data transfer circuit 13 includes D-type flip-flop circuits 13-1, 1 connected in series.
3-2 to 13-i-1 and a buffer circuit BF. Each flip-flop circuit 13-1, 13
The transfer transistor 1 is connected to the input terminals D of −2 to 13-i−1.
Output signals 6-1 and 16-2 to 16-i-1 (not shown) are supplied. The signal φ4 is supplied to the clock signal input terminal CK. The output terminal of the buffer circuit BF is connected to the fuse data latch circuit 14.

The fuse data latch circuit 14 includes a D-type flip-flop circuit 14-1 connected in series,
14-2 to 14-i. The signal φ4 is supplied to the clock signal input terminals CK of the flip-flop circuits 14-1 and 14-2 to 14-i. This D
Type flip-flop circuits 14-1, 14-2 to 14
-I constitutes a shift register.

The signals φ1 to φ3 are transfer start signals TS.
Is generated by the control circuit 17 which operates according to The clock oscillator 18 and the counter 19 generate the signal φ4 under the control of the control circuit 17.

FIG. 9 shows the operation of FIG. 8 and shows signals φ1 to φ4.

In the above structure, first, the signal φ1 is set to the low level, and the respective data holding circuits 15-1, 15-2 to 15-1.
The output terminal of 5-i is set to low level. After this, the signal φ2
Is set to a high level, the fuses 12-1, 12-2 ...
12-i data is data holding circuits 15-1 and 15-2.
~ 15-i. As a result, when the fuse is blown, the output signal of the data holding circuit remains low level, and when the fuse is not blown, the output signal of the data holding circuit becomes high level. When the fuse data is taken into the data holding circuit, the signal φ
3 is set to the high level, and the output signal of the data holding circuit is supplied to the fuse data transfer circuit 13 via the transfer transistors 16-1, 16-2 to 16-i. After that, when the signal φ4 is supplied to the fuse data transfer circuit 13,
The data held in the fuse data transfer circuit 13 is sequentially transferred to and held in the fuse data latch circuit 14.

However, such a fuse data transfer system has the following problems.

(A) When power is supplied to the memory macro, the data stored in the fuse must be transferred without fail.

That is, the above operation is executed every time the power is supplied to the memory macro. Moreover, the configuration shown in FIG. 8 is a serial data transfer system. Therefore, it takes time to transfer the data. Therefore, it takes time from the power supply to the memory macro to the end of the memory macro setup operation.

It is essential to transfer fuse data to the memory macro when the entire semiconductor integrated circuit provided with the memory macro is activated. However, for example, in a system in which the power to the memory macro is frequently turned on and off in order to reduce power consumption, it is necessary to execute fuse data transfer that requires a long time each time power is supplied to the memory macro. It was difficult to activate the memory macro at high speed.

(B) When there are a plurality of memory macros in the semiconductor integrated circuit, the fuses arranged in each memory macro are collectively arranged at one place, and the data of these fuses are collectively transferred serially. It is possible.

In this case, the degree of freedom in the layout of the signal lines and the power supply lines is further improved, and the total wiring length can be shortened even if the fuse and the memory macro are arranged at separate positions.

FIG. 10 shows another example of FIG. 8 and shows a configuration in which fuses of each memory macro are collectively arranged at one place. 10, the same parts as those in FIG. 8 are designated by the same reference numerals.

FIG. 10 shows n memory macros 11-1 to 11-1.
11-n. These memory macros 11-1 to 11-1
11-n are connected in series. The fuse circuit 20 is provided with n fuse groups 20-1 to 20-n corresponding to the n memory macros 11-1 to 11-n. Corresponding to these fuse groups 20-1 to 20-n,
The data holding circuit group, the transfer transistor group, and the fuse data transfer circuit group are provided.

The operation of the circuit shown in FIG. 10 is almost the same as that of the circuit shown in FIG.
The data of −n is the data holding circuits 15-1 to 15-i × n.
Read out. These data holding circuits 15-1 to 15
-I × n data is transfer transistors 16-1 to 16-
It is transferred to the fuse data transfer circuit 13 via i × n. Data is sequentially transferred from the fuse data transfer circuit 13 to the memory macros 11-n to 11-1. The fuse data holding circuit 14 of each of the memory macros 11-n to 11-1 is composed of a shift register. For this reason,
When the serial transfer of all the fuse data is completed, the fuse data holding circuit 14 holds the fuse data required by each memory macro.

The configuration shown in FIG. 10 is easy to implement because even if there are a plurality of memory macros, the same circuit system as in the case of one memory macro can be applied. However, since the fuse data is transferred serially, the same problem as in (a) occurs.

On the other hand, FIG. 11 is a block diagram of the circuit shown in FIG. 10. In FIG. 11, the same parts as those in FIG. 10 are designated by the same reference numerals. In the semiconductor chip 10, n memory macros 11 from the fuse circuit 12 side
-1 to 11-n are connected in series. It is assumed that the memory macros 11-1 to 11-n are supplied with power from independent power supplies.

Here, it is assumed that the memory macros 11-1 to 11-
It is assumed that power is supplied to all n memory macros. It is assumed that the power supplies of the memory macro 11-i and the memory macro 11-j are turned off from this state. Then, the fuse data holding circuits 14 in the memory macro 11-i and the memory macro 11-j lose the fuse data.

Thereafter, as shown in FIG. 12, the memory macro 11-i remains in the off state, and the memory macro 11-j is turned off.
It is assumed that power is supplied again to the. In this case, since the memory macro 11-i is off, the memory macro 11-i
There is a problem that fuse data is not transferred to j.

That is, when the power is supplied to the memory macro 11-j, it is necessary to also supply the power to the memory macro 11-i. For this reason, the power supply of each memory macro cannot be turned on / off independently. Therefore, it is necessary to supply power to all the memory macros in order to transfer the fuse data. In this case, since the power consumption increases, it is difficult to apply this configuration to a system in which the power of the memory macro is frequently turned on / off to reduce the power consumption.

The present invention has been made to solve the above problems, and an object of the present invention is to individually control the power supplies of a plurality of memory macros.
An object of the present invention is to provide a semiconductor integrated circuit capable of surely transferring necessary data to each memory macro.

[0029]

In order to solve the above problems, a semiconductor integrated circuit of the present invention includes at least one functional circuit having a certain function, which is arranged on a semiconductor chip.
A holding circuit that holds information necessary for the operation of the functional circuit and a power supply circuit that separately supplies power to the functional circuit and the holding circuit are provided.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows an embodiment of the present invention. A memory macro 11 is arranged on the semiconductor chip 10. This memory macro 11
Is, for example, a DRAM, but is not limited to the DRAM. Further, on the semiconductor chip 10, a fuse circuit 12, a fuse data transfer circuit 13, and a fuse data latch circuit (FDLC) 14 are arranged. The fuse circuit 12, the fuse data transfer circuit 13, and the fuse data latch circuit 14 are the fuse circuit 1 shown in FIG.
2. The fuse data transfer circuit 13 and the fuse data latch circuit 14 have the same configuration.

That is, the fuse circuit 12 has a plurality of fuses, a data holding circuit, and a transfer transistor. The data stored in each fuse is read and held in each data holding circuit. The data held in these data holding circuits is supplied to the fuse data transfer circuit 13 via the transfer transistor. The fuse data transfer circuit 13 has a plurality of D-type flip-flop circuits connected in series that form a shift register. Each flip-flop circuit holds the output data of the data holding circuit and sequentially outputs the held data.

The fuse data latch circuit 14 has a plurality of D-type flip-flop circuits connected in series which form a shift register. The fuse data latch circuit 14 holds the data supplied from the fuse data transfer circuit 13.

In the first embodiment, the power supplied to the fuse data latch circuit 14 and the power supplied to the memory macro 11 are separate. That is,
The memory macro 11 is connected to the power supply pad 31a, and the fuse data latch circuit 14 is connected to the power supply pad 31b. These power supply pads 31a and 31b are supplied to the power supplies PW1 and PW separately from the outside of the semiconductor chip 10, for example.
2 is supplied.

In the above structure, when the memory macro 11 is activated, the power supplies PW1 and PW2 are supplied. Along with this, the data stored in the fuse circuit 12 is supplied to the fuse data latch circuit 14 via the fuse data transfer circuit 13. In this state, for example, when the power PW1 of the memory macro 11 is turned off, the power PW2 of the fuse data latch circuit 14 is kept on, so that the data held in the fuse data latch circuit 14 is held. . After that, when the power PW1 of the memory macro 11 is turned on, it is not necessary to transfer the data from the fuse circuit 12 again. Therefore, the memory macro 11 is activated immediately after the power PW1 is turned on again.

According to the first embodiment, the power supplied to the memory macro 11 and the fuse data latch circuit 14 are separate. Therefore, after the memory macro 11 is activated, the data of the fuse data latch circuit 14 can be held even when the power supply PW1 of the memory macro 11 is turned off. Therefore, when the power of the memory macro 11 is turned on again, it is not necessary to transfer the data from the fuse circuit 12, so the memory macro 11
Can be started at high speed.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
The same parts as those in the first embodiment are designated by the same reference numerals, and only different parts will be described.

In FIG. 2, the memory macro 11 and the fuse data latch circuit 14 are connected to the power supply pad 31a via, for example, transistors 41 and 42 as switch circuits. That is, the memory macro 11 is connected to the power supply pad 31 a via the transistor 41, and the fuse data latch circuit 14 is connected to the power supply pad 31 a via the transistor 42. Signals CS1 and CS2 output from the signal generation circuit 43 are supplied to the gates of these transistors 41 and 42, respectively. The signal generation circuit 43 controls the signals CS1 and CS2, for example, when the memory macro is activated or in a mode in which the power consumption of the semiconductor chip 10 is reduced.

That is, when the memory macro is activated, the signal generation circuit 43 sets both the signals CS1 and CS2 to the high level. Therefore, both the transistors 41 and 42 are turned on, and the memory macro 11,
Also, the fuse data latch circuit 14 is powered on. In this state, as in the first embodiment,
Data is output from the fuse circuit 12, and this data is transferred to and held in the fuse data latch circuit 14 via the fuse data transfer circuit 13. After that, when the power of the memory macro 11 is turned off to reduce power consumption, for example, the signal generation circuit 43 holds only the signal CS1 at the low level and holds the signal CS2 at the high level. Therefore, only the transistor 41 is turned off, and the power supply to the memory macro 11 is stopped. At this time,
Since the transistor 42 remains on, the fuse data latch circuit 14 continues to hold data. After this,
When the memory macro 11 is activated again, the signal generation circuit 43 sets the signal CS1 to the high level. Then,
The transistor 41 is turned on, and power is supplied to the memory macro 11 via the transistor 41. At this time,
Since the fuse data latch circuit 14 holds the data, it is not necessary to transfer the data from the fuse circuit 12.

The same effects as those of the first embodiment can be obtained by the second embodiment. Moreover, in the case of the second embodiment, the transistors 41 and 42 are provided between the memory macro 11 and the fuse data latch circuit 14 and the power supply pad 31a, and these transistors 41 and 42 are provided.
The power supply to the memory macro 11 and the fuse data latch circuit 14 is controlled by controlling the conduction of the. Therefore, since the power supplied from the outside can be one system, there is an advantage that the configuration of the power can be simplified.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
In FIG. 3, the same parts as those in FIG. 11 are denoted by the same reference numerals, and only different parts will be described.

As shown in FIG. 3, the semiconductor chip 10 is provided with a plurality of memory macros. As described above, in the case of such a configuration, in the fuse circuit 12, as shown in FIG. 10, fuses of each memory macro are collectively arranged.

In the third embodiment, the memory macros 11-1 to 11-i and 11-j to 11-n have different power supply pads 31-1 to 31-i and 31-j to 31.
Connected to -n. These power supply pads 31-1 to 3
1-i, 31-j to 31-n have power supplies PW1 to PW
i, PWj to PWn are respectively supplied. Therefore, each memory macro 11-1 to 11-i, 11-j to
The power supplies 11-n can be turned on and off individually.

Further, each memory macro 11-1 to 11-
i, 11-j to 11-n fuse data latch circuit 1
4, fuse circuit 12 and fuse data transfer circuit 13
Are connected to the power supply pad 31-0. The power supply PW0 is supplied to the power supply pad 31-0. That is, power is supplied to the fuse data latch circuit 14, the fuse circuit 12, and the fuse data transfer circuit 13 from a system different from the memory macros 11-1 to 11-i and 11-j to 11-n.

The operation of the above configuration will be described. For example, when the initial power is turned on, all macros 11-1 to 11-
i, 11-j to 11-n are activated. That is, the power supplies PW1 to PWn are supplied to all the memory macros 11-1 to 11-i and 11-j to 11-n. At the same time, the power supply PW0 is supplied to the fuse data latch circuit 14, the fuse circuit 12, and the fuse data transfer circuit 13.
In this state, the data read from the fuse circuit 12 is sequentially transferred to and held in the fuse data latch circuit 14 of each memory macro via the fuse data transfer circuit 13.

In this state, for example, the memory macro 1
The power supplies for 1-i and 11-j are turned off.
Even when the power supply to the memory macro 11-j is turned on, the power supply PW0 is continuously supplied to the fuse data latch circuit 14 during this time. Therefore, even when the power supply to the memory macros 11-i and 11-j is turned off, these memory macros 11-i and 11-j are also turned off.
The data of the fuse data latch circuit 14 of -j is retained without being erased. Therefore, memory macro 1
There is no need to retransmit the data when the power supply for 1-j is turned on.

According to the third embodiment, the power supplies PW1 to PWi and PWj to PWn are individually supplied to the memory macros 11-1 to 11-i and 11-j to 11-n, respectively. Memory macros 11-1 to 11-i, 11-j to 1
The 1-n fuse data latch circuit 14, the fuse circuit 12, and the fuse data transfer circuit 13 are supplied with a power supply PW0 different from the memory macro. Therefore, the power of any memory macro can be turned on and off, and even if the power of any memory macro is turned on again, it is not necessary to transfer the fuse data again. Can be started at high speed.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
2 shows an embodiment of the present invention. FIG. 4 is a modification of the third embodiment shown in FIG. 3, and shows a case where the third embodiment is applied to a semiconductor integrated circuit mounted together with a logic circuit. Therefore, in FIG. 4, the same parts as those in FIG. 3 are denoted by the same reference numerals, and only different parts will be described.

That is, in FIG. 4, the semiconductor chip 1
A logic circuit 51 is provided at 0. The logic circuit 51 includes a power supply PW from the power supply pad 31-0.
0 is supplied. That is, this logic circuit 51
The power source is separated from each memory macro and is driven by the same power source as the fuse data latch circuit 14, the fuse circuit 12, and the fuse data transfer circuit 13.

According to the fourth embodiment, the logic circuit 5
The power supply for 1 and each memory macro is separated. For this reason,
The power of any memory macro can be turned on / off, and even if the power of any memory macro is turned on again, it is not necessary to transfer the fuse data again, so the memory macro can be operated at high speed. It can be started.

In the third and fourth embodiments, power is supplied to each memory macro, the fuse data latch circuit 14, the fuse circuit 12, the fuse data transfer circuit 13, and the logic circuit 51 from individual power supply pads. Supplied. However, the present invention is not limited to this, and it is possible to combine the second embodiment with the third and fourth embodiments. That is, it is possible to control the power supply to each memory macro, the fuse data latch circuit 14, the fuse circuit 12, the fuse data transfer circuit 13, and the logic circuit 51 via a plurality of transistors. In this case, it is possible to reduce the number of power supply pads and power supplies.

(Fifth Embodiment) FIG. 5 shows the fifth embodiment of the present invention.
The same parts as those in FIG. 10 are designated by the same reference numerals.

In the above-described first to fourth embodiments, when the power supply of the memory macro is off, it is not necessary to transfer the data from the fuse circuit. On the other hand, in the fifth embodiment, data can be transferred even when the power of the memory macro is off. Therefore, among the plurality of memory macros in which the respective fuse data latch circuits 14 are connected in series, the memory macros other than the last memory macro have a bypass circuit for bypassing the data.

That is, in FIG. 5, the memory macro 1
For example, power sources PW1 and PW2 are supplied to 1-1 and 11-2, respectively. Memory macros 11-1, 11-
The method of supplying power to 2 may be either directly from the power pad or via a transistor. The memory macros 11-1 and 11-2 have a fuse data latch circuit 14. Each fuse data latch circuit 14
Is composed of a plurality of D-type flip-flop circuits connected in series. The bypass circuit 61 is connected in parallel to the fuse data latch circuit 14 of the memory macro 11-1.

That is, the fuse data latch circuit 14
For example, a CMOS transfer gate (hereinafter, simply referred to as a transfer gate) 6 is provided at the input end and the output end of the
2, 63 are connected. Further, transfer gates 64, 65 are provided at the input end and the output end of the bypass circuit 61.
Are connected. These transfer gates 64,
65 operates at a logic level opposite to that of the transfer gates 62 and 63. The input ends of the transfer gates 62 and 64 are commonly connected to the output end of the fuse data transfer circuit 13. In addition, the transfer gates 63 and 65
The output terminal of the is connected to the input terminal of the transfer gate 66 in common. The output end of the transfer gate 66 is the fuse data latch circuit 1 of the memory macro 11-2.
4 is connected to the input end.

Each of the memory macros 11-1 and 11-2 outputs, for example, fuse data request signals RS1 and RS2. Each of the memory macros 11-1 and 11-2 receives the request signal RS1, when data is required for some reason, for example, when power is supplied.
Set RS2 to high level. Further, each of the memory macros 11-1 and 11-2 receives the request signals RS1 and R when the power is turned off, or when the fuse data latch circuit 14 holds necessary data.
Set S2 to low level.

The request signal RS1 output from the memory macro 11-1 is supplied to the transfer gates 62 to 65 and also to one input terminal of the OR circuit 67. The request signal RS2 output from the memory macro 11-2 is supplied to the transfer gate 66 and the other input terminal of the OR circuit 67. The output signal of the OR circuit 67 is supplied to the control circuit 17 as the transfer start signal TS.

The operation of the above configuration will be described. First, the memory macro 11-1 does not need to transfer fuse data, for example, the power is off or the power is on but the fuse data latch circuit 14 already holds the necessary data. Suppose At this time, the request signal RS1 output from the memory macro 11-1 is at low level. Therefore, the transfer gates 62 and 63 are in a non-conducting state, and the transfer gates 64 and 65 are in a conducting state. Therefore, bypass circuit 61 is set to be able to transfer data.

In this state, the memory macro 11-2
When the request signal RS2 output from the high level signal becomes high, the transfer start signal TS output from the OR circuit 67 becomes high level in response to the request signal RS2. Therefore, the data is read from the fuse circuit 12, and this data is transferred to the fuse data transfer circuit 13, the transfer gate 64, the bypass circuit 61, and the transfer gate 6.
It is transferred to the fuse data latch circuit 14 of the memory macro 11-2 via 5, 66.

At this time, if the necessary data is held in the fuse data holding circuit 14 of the memory macro 11-1, the signal φ4 for moving the flip-flop circuit of the fuse data holding circuit 14 is deactivated.

On the other hand, for example, when the request signal RS1 output from the memory macro 11-1 becomes high level, the transfer gates 62 and 63 are rendered conductive and the transfer gates 64 and 65 are rendered non-conductive. Therefore, the data path is switched from the bypass circuit 61 to the fuse data holding circuit 14.

Further, the OR circuit 6 is responsive to the request signal RS1.
The transfer start signal TS output from 7 goes high. Therefore, the data is read from the fuse circuit 12, and this data is transferred to the fuse data latch circuit 14 of the memory macro 11-1 via the fuse data transfer circuit 13 and the transfer gate 62.

In this manner, the memory macro that has issued the transfer request receives the data from the fuse circuit by the fuse data holding circuit 14, and the memory macro that has not issued the transfer request does not receive the fuse data. That is,
Each memory macro can receive fuse data independently of each other. Therefore, the power of each memory macro can be turned on / off independently of each other.

According to the fifth embodiment, the fuse data latch circuit 14 of the memory macro is provided with the bypass circuit 61 in parallel, and the data paths of the fuse data latch circuit 14 and the bypass circuit 61 are output from the memory macro. It can be switched according to the request signals RS1 and RS2. Therefore, data can be fetched from the fuse circuit 12 to the fuse data latch circuit 14 as needed. Therefore, the power supply of each memory macro can be controlled individually, and furthermore, the memory macro to which the power supply is supplied can be activated at high speed.

The above embodiments have been described with respect to the memory macro. However, the present invention is not limited to this, and the present invention can also be applied to a macro as at least one functional circuit having a certain function including a logic circuit and an analog circuit. That is, a fuse data transfer circuit that stores data necessary for the operation of the functional circuit in the fuse circuit and transfers the data stored in the fuse circuit to the fuse data latch circuit provided in the mechanism circuit as needed is provided. It is possible to apply each of the above-described embodiments to a semiconductor integrated circuit.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0067]

As described above in detail, according to the present invention,
It is possible to provide a semiconductor integrated circuit that can individually control the power supplies of a plurality of memory macros and can reliably transfer the necessary data to each memory macro.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a memory macro.

FIG. 7 is a block diagram showing another example of a memory macro.

FIG. 8 is a circuit diagram specifically showing the configuration shown in FIG.

9 is a timing chart showing the operation of FIG.

FIG. 10 is a circuit diagram showing another example of FIG.

11 is a block diagram showing the circuit shown in FIG. 10 as a block.

FIG. 12 is a block diagram showing the operation of FIG. 11.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip, 11, 11-1 to 11-n ... Memory macro, 12 ... Fuse circuit, 13 ... Fuse data transfer circuit, 14 ... Fuse data latch circuit, 31a, 31b, 31-0, 31-1 to 31 -I, 31
-J to 31-n ... Power supply pad, PW0, PW1 to PWi, PWj to PWn ... Power supply, 41, 42 ... Transistor, 51 ... Logic circuit, 61 ... Bypass circuit, 62-66 ... Transfer gate, 67 ... OR circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ryo Haga             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 5L106 AA01 CC04 CC08                 5M024 AA50 AA91 BB30 BB32 BB40                       DD80 FF20 HH10 KK35 MM20                       PP01 PP02 PP03 PP07

Claims (8)

[Claims] 1. A at least one functional circuit having a certain function arranged on a semiconductor chip, a holding circuit for holding information necessary for the operation of the functional circuit, and a power supply for the functional circuit and the holding circuit separately. And a power supply circuit for supplying the power. 2. A at least one memory macro having at least a memory cell array arranged on a semiconductor chip, a holding circuit for holding information necessary for the operation of the memory macro, and a power supply for the memory macro and the holding circuit separately. And a power supply circuit for supplying the power. 3. The power supply circuit includes first and second power supply pads arranged on the semiconductor chip, a first wiring connecting the first power supply pad and the memory macro, and the first power supply pad. A second connecting the second power supply pad and the holding circuit
3. The semiconductor integrated circuit according to claim 2, further comprising: 4. The power supply circuit includes a power pad arranged on the semiconductor chip, a first switch provided between the power pad and the memory macro, the power pad and the holding circuit. 3. A second switch provided between the first switch and the second switch, and a signal generation circuit for selectively turning on and off the first switch and the second switch.
The semiconductor integrated circuit described. 5. The semiconductor chip further comprises a storage circuit for storing the information necessary for the operation of the memory macro, and a transfer circuit for transferring the information read from the storage circuit to the holding circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the storage circuit and the transfer circuit are supplied with the same power as the holding circuit. 6. The semiconductor integrated circuit according to claim 2, wherein the semiconductor chip further comprises a logic circuit, and the logic circuit is supplied with the same power as the holding circuit. 7. A first and a second memory macro having memory cell arrays arranged on a semiconductor chip, and information provided in the first memory macro and necessary for the operation of the first memory macro. And a second holding circuit which is provided in the second memory macro and which holds information necessary for the operation of the second memory macro, and a second holding circuit which is provided in parallel with the first holding circuit. Bypass circuit, a first switching circuit that switches between the first holding circuit and the bypass circuit according to a first request signal output from the first memory macro, and the second memory macro A second switching circuit for receiving the data supplied from the first holding circuit or the bypass circuit in the second holding circuit in response to a second request signal output from the second holding circuit. You Semiconductor integrated circuit. 8. A memory circuit for storing the information necessary for the operation of the memory macro, a transfer circuit for transferring the information read from the memory circuit to the holding circuit, and a memory circuit for the first memory macro. And a control circuit for reading the information from the storage circuit in response to the first request signal output and the second request signal output from the second memory macro. The semiconductor integrated circuit according to claim 7.