JP2003102034A - Interface device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface device for digital signal transfer capable of decreasing the number of signal lines between an output circuit and a reception circuit. SOLUTION: The interface device 271 comprises an output circuit 28A1 for transferring image data SD and a reception circuit 28B1 . A parallel-to-serial conversion circuit 37 to the output circuit 28A1 converts image data PD into serial image data SD in 2-bit width synchronously with a clock BCLK (frequency: 54 MHz) from a bit clock generating circuit 35 and provides an output. Although a clock PCLK (destination: 13.5 MHz) from a pixel clock generating circuit 36 is transferred to the reception circuit 28B1 , the clock BCLK is not transferred to the reception circuit 28B1 . The reception circuit 28B1 regenerates the clock BCLK whose frequency is a multiple of four of that of the transferred clock PCLK and supplies the clock BCLK to a serial-to-parallel conversion circuit 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device used for data transfer in an image processing device such as a digital camera.

[0002]

2. Description of the Related Art Digital still cameras and digital
In an image pickup device such as a video camera, light transmitted through an optical system including a lens group is detected by an image pickup element such as a CCD sensor or a CMOS sensor and photoelectrically converted into an image signal. The image signal is a digital signal (original image data)
After the / D conversion, various image processes such as pixel interpolation, color space conversion, contour enhancement, and resolution conversion are performed by an image processing chip (LSI) or the like. Next, the signal subjected to the image processing is transferred to a display device such as an LCD (liquid crystal display device) or an EVF (electronic viewfinder) provided in the eyepiece and displayed as an image.

The display devices often use a composite color video signal (hereinafter referred to as "composite signal"). Since an analog composite signal is a composite of all signals necessary for video display such as video signals and synchronization signals, it has the advantage of reducing the number of signal lines. FIG. 8 is a schematic configuration diagram showing an interface device 100 including an output circuit 100A for transferring an analog composite signal 105 and a receiving circuit 100B. The output circuit 100A receives a digital image signal (Y / R signal, Cb / G signal, Cr / B signal) from the video signal source.
And horizontal / vertical synchronization signals HD and VD are input. The digital image signal is an RGB signal composed of R (red), G (green) and B (blue) color components, or a Y signal (luminance signal) and Cb and Cr signals (color difference signal). YCbCr signal, where Y / R signal is either Y signal or R signal, Cb / G signal is either Cb signal or G signal, and Cr / B signal is either Cr signal or B signal One is shown respectively.

In the output circuit 100A, the digital encoder 102 outputs a composite signal of the pixel clock PCLK supplied from the pixel clock generator 101, the digital image signal, the horizontal synchronizing signal HD and the vertical synchronizing signal VD.
And outputs to the / A converter 103. The D / A converter 103 converts the input signal into an analog composite signal 105 and outputs it to the receiving circuit 100B. It should be noted that the pixel clock generator 101 generates a pixel clock so as to be synchronized with the timing when image signals of 8-bit width are input in parallel. The frequency of the pixel clock is based on ITU-R (International Telecommunication Union Radio Communications Division) Recommendation BT. In the case of a TV signal compliant with 601, the frequency is 13.5 MHz. On the other hand, the analog decoder 104 of the receiving circuit 100B receives the analog image signal (analog RGB signal or analog YCbCr signal) and the synchronization signals HD and V from the transferred composite signal 105.
D is extracted and output.

In addition, analog RGB signals and analog YC
The bCr signal and digital image signal may also be used for data transfer. FIG. 9 is a block diagram showing a schematic configuration of the interface device 110 including an output circuit 110A that outputs an analog image signal and a receiving circuit 110B. As shown in the figure, Y / R signals of 8 bits width, C
The b / G signal and the Cr / B signal are converted into analog signals by the D / A converters 111A, 111B and 111C, respectively. These analog signals together with the pixel clock PCLK, the vertical synchronizing signal VD, and the horizontal synchronizing signal HD are received by the receiving circuit 1.
10B is transferred. When a display device such as an EVF is configured by a color CRT, the number of signal lines between the output circuit 110A and the reception circuit 110B is increased as compared with the interface device 100 shown in FIG. 8, but a composite signal is converted to an analog RGB signal. Because the conversion circuit of is unnecessary,
The number of components in the display device can be reduced, which is advantageous in low power consumption and low cost.

Further, as shown in the schematic diagram of FIG. 10, a digital interface comprising an output circuit 115A and a receiving circuit 115B for transferring digital image signals (Y / R signals, Cb / G signals, Cr / B signals). Device 115 is also known. Pixel clock PCLK, Y / R signal, Cb /
G signal, Cr / B signal and horizontal / vertical synchronization signal HD,
VD is transferred as a digital signal. Display device
In the case of an LCD driven by digital signals, a digital signal input from the video signal source to the output circuit 115A can be transferred without being converted into an analog signal, so that signal deterioration due to D / A conversion is avoided. It is possible,
There is an advantage that noise is hard to mix in. However,
Since a large number of signal lines of 8 to 16 bits are required for each color component, there is a drawback that the circuit scale increases. Therefore, as shown in FIG. 11, the D / A converters 121A to 121C of the output circuit 120A intentionally convert the digital image signals (Y / R signals, Cb / G signals, Cr / B signals) into analog signals and transfer them. , A / D converter 12 of the receiving circuit 120B
At present, the interface device 120 that performs A / D conversion of analog image signals received by 2A to 122C is often used.

In addition, a DVI (Digital Vi for LCD panel)
The deo Interface standard specifies TMDS (Transition Mini).
Serial transmission methods such as mized Differential Signaling) are used. In this serial transmission system,
As shown in FIG. 2, the output circuit 130A is a parallel-serial conversion circuit 131A to 131C that parallel-serializes a digital image signal (Y / R signal, Cb / G signal, Cr / B signal) having an 8-bit width into a serial signal. Convert, increase rate and transfer. The parallel-serial conversion circuits 131A to 131C output the frequency (=) of the pixel clock PCLK from the bit clock generator 132.
It is supplied with a bit clock BCLK having a frequency (= 108 MHz) that is eight times as high as 13.5 MHz), and performs parallel-serial conversion in synchronization with this bit clock BCLK.

On the other hand, the receiving circuit 130B has serial-parallel conversion circuits 133A to 133C for converting the received serial signal into an 8-bit width digital signal and outputting it. Further, the bit clock BCLK and the pixel clock PCLK are transferred from the output circuit 130A to the receiving circuit 130B, and the serial-parallel conversion circuits 133A to 133C capture the serial signal in synchronization with the bit clock BCLK and Serial / parallel conversion is executed in synchronization with the clock PCLK to output digital image signals of 8-bit width. However, since the high-speed bit clock BCLK is transferred inside the device, there is a problem that it becomes a source of radiation noise.

[0009]

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an interface device for digital signal transfer which can reduce the number of signal lines between an output circuit and a receiving circuit. In point.

[0010]

In order to solve the above problems, the invention according to claim 1 is an interface comprising an output circuit for transferring digital data and a receiving circuit for receiving the data transferred from the output circuit. A device,
It said output circuit is a multiple of N _1-bit (N ₁ is N _2; N ₂ 2
A parallel-serial conversion circuit that serially converts the above integer) width data into N ₂ -bit width data in synchronization with a bit clock and outputs the data to the reception circuit, and the parallel-serial conversion circuit that generates the bit clock. A bit clock generation circuit for outputting to the conversion circuit; and a data clock generation circuit for generating and outputting a data clock at the timing when the data of N ₁ bit width is input to the parallel-serial conversion circuit, The receiving circuit includes a PLL circuit for recovering a bit clock obtained by multiplying the data clock transferred from the output circuit by N ₁ / N _2, and the N circuit transferred from the output circuit.
Serial-parallel conversion in which _2- bit width data is sequentially taken in in synchronization with the bit clock supplied from the PLL circuit, converted in parallel into N ₁ bit width data in synchronization with the data clock, and output. And a circuit.

According to a second aspect of the present invention, in the interface device according to the first aspect, the parallel-serial conversion circuit of the output circuit has N ₁ bit width for each of the plurality of color component data forming the image data. and outputs the converted serial data in N ₂ bit wide from the data of the serial-parallel conversion circuit of the receiving circuit, a plurality of the N transferred from the output circuit
_{The 2-} bit width data is converted into N ₁ -bit width data in parallel.

The invention according to claim 3 is the interface device according to claim 2, wherein the plurality of color component data comprises luminance data and color difference data multiplexed in pixel units.

The invention according to claim 4 is the interface device according to any one of claims 1 to 3, wherein a part of the data of the N ₁ bit width in the output circuit is for video display. The sync signal is inserted.

The invention according to claim 5 provides the invention according to claim 1.
5. The interface device according to any one of claims 4 to 4, wherein the serial-parallel conversion circuit of the reception circuit temporarily stores the data of the N ₂ bit width over a plurality of cycles of the bit clock. According to a shift register and an externally supplied control signal, N ₁ bit wide data is selected from the shift register so as to correct the phase shift of the N ₂ bit wide data with respect to the bit clock. And a selector for outputting in parallel.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Digital still camera. First, a configuration example of a digital still camera incorporating the interface device according to the embodiment of the present invention will be shown, and then the interface device according to each embodiment will be described in detail.

FIG. 1 shows the digital still camera 1.
It is a functional block diagram showing a schematic configuration of. The digital camera 1 includes an optical mechanism 10 having a lens group, a prism, an AF (auto focus) function, an automatic exposure adjustment function, and the like. The reflected light from the subject passes through this optical mechanism 10 and the optical LPF (low pass
The light is received by the CCD image pickup device 12 through the filter 11.

The CCD image pickup device 12 converts the light incident through the optical mechanism 10 and the optical LPF 11 into an analog signal and outputs it to the analog signal processing circuit 13. This CCD
The image sensor 12 operates by receiving a drive signal supplied from the CCD drive circuit 15, and a charge storage unit that stores carriers (electrons or holes) generated by the photoelectric effect and an electric field applied to the stored carriers for transfer. And a charge transfer section for performing the operation. On the photosensitive portion of the CCD image pickup device 12,
Single-plate color filter that colors the incident light in pixel units
An array is provided. Therefore, the CCD image pickup device 1
R (red), G (green), B (blue) on the photosensitive part of 2.
The light colored with the three primary colors or four colors such as Y (yellow color), M (magenta color), C (cyan color), and G (green) enters and undergoes photoelectric conversion. Incidentally, CC
A CM having no charge transfer section in place of the D image sensor 12
An OS image sensor may be adopted.

The analog signal processing circuit 13 includes a CDS (Co
rrelated Double Sampling circuit, AGC (Automatic Gain Control)
A circuit and an A / D conversion circuit are provided. Generally, CC
The D image pickup device 12 alternately outputs a reference signal having a reference level of a normal black level and an image signal including the reference signal in a time division manner. The CDS circuit samples the reference signal and the image signal in order to remove the noise component contained in the image signal, and extracts and outputs the difference signal between the two signals. Further, the AGC circuit outputs a signal in which the signal level of the differential signal input from the CDS circuit is optimized, and A
The / D conversion circuit samples the input signal from the AGC circuit and outputs a digital image signal (original image data; Raw Image Data) quantized by a predetermined number of quantization bits.

RPU (real-time processing
The unit 14 is an integrated circuit that operates in synchronization with the clock signal supplied from the timing generator 16. The RPU 14 is the analog signal processing circuit 1
3 has a function of performing various kinds of digital image processing such as shading correction processing, pixel interpolation processing, gamma correction processing, color space conversion processing, contour enhancement processing and resolution conversion processing on the original image data input in real time. . For example, in the pixel interpolation process, the single-plate color filter array interpolates a plurality of color components per pixel for an image signal having only a single color component per pixel. As a result, an image signal having three primary color components of R, G, B or four color components of Y, M, C, G etc. is generated for one pixel.

The image signal output from the RPU 14 is transferred to the CPU (central processing unit) 18 via the main bus 32 and subjected to various processes. CPU1
Reference numeral 8 operates in synchronization with a clock signal supplied from a PLL (Phase-Locked Loop) circuit 17, and executes software processing by using the main memory 21 such as DRAM as a work area. Further, the CPU 18 uses the compression / expansion processing unit 20.
When the image signal is started, the JPEG (Joint Ph
otographic Expert Group) method and motion JPEG
After compression-encoding with a method, the compressed data is written out to the memory card 23 via the interface 22 or a personal interface via the external interface 24.
It can be output to an external device such as a computer.

The CPU 18 can be controlled so that still images (frames) continuously output from the RPU 14 are displayed as moving images on the LCD 30 functioning as a finder. That is, the CPU 18 causes the RPU 14 to
The frames output after being subjected to resolution conversion according to the resolution of the LCD 30 are sequentially transferred to the display module 25 via the main bus 32. The display module 25 uses the digital image signal (R
The GB signal and the YCbCr signal) are output to the interface device 27 in frame units.

The interface device 27 includes the output circuit 2
8A and a receiving circuit 28B. The output circuit 28A receives N ₁ -bit wide data input from the display module 25 as N, as will be described later.
₂ (N ₁ : a multiple of N ₂ ) bit width is converted to serial data and transferred to the receiving circuit 28B. The receiving circuit 28B also transfers the transferred serial data to the original N ₁ bit width. LCD drive circuit 2
Output to 9. Then, the LCD drive circuit 29 controls the input data of N ₁ bit width to be written in the LCD 30 in frame units.

The user of the digital still camera 1 visually recognizes the moving image displayed on the LCD 30 in the viewfinder, sets the framing and exposure of the main subject, sets the shutter speed, and determines the shooting timing. . When the user presses a release button (not shown) at the moment of shooting, the CPU 18 detects the state and controls the RPU 14 to output high-resolution image data. The high resolution image data is
After being compressed and encoded by the compression / expansion processing unit 20 described above, the data is transferred to the interface 22 via the main bus 32 and written in the memory card 23.

The PLL circuit 17 also generates a clock signal by multiplying the oscillation signal supplied by the oscillator 17A. The clock signal is a timing generator 16 that regulates the operation timing of the CCD drive circuit 15,
It is supplied to the output circuit 28A, the CPU 18, and the like.

The data transfer via the main bus 32 may be performed under the control of a DMA (Direct Memory Access) controller 19 connected to the main bus 32, not via the CPU 18.

An embodiment of the interface device 27 mounted on the digital still camera 1 having the above configuration will be described in detail below.

Embodiment 1. FIG. 2 is a functional block diagram showing a schematic configuration of the interface device 27 ₁ according to the first embodiment of the present invention. This interface device 2
Reference numeral 7 ₁ denotes an 8-bit width image signal PD input from the display module 25 and a 2-bit width image signal S.
The output circuit 28A ₁ for converting the data into D and outputting them in series, and the receiving circuit 28B ₁ for receiving the image signal SD having a 2-bit width transferred from the output circuit 28A ₁ are provided.

In the output circuit 28A ₁ , the pixel clock generating circuit 36 generates a pixel clock (data clock) PCLK having a frequency fp of 13.5 MHz and outputs it to the receiving circuit 28B ₁ . Further, the bit clock generation circuit 35 has a bit clock B having a frequency fb (= 54 MHz) which is four times the frequency of the pixel clock PCLK.
CLK is generated and supplied to the parallel-serial conversion circuit 37. This bit clock BCLK is used by the receiving circuit 28B ₁
Not transferred to. The parallel-serial conversion circuit 37 takes in the image data PD of 8-bit width input from the display module 25 (video signal source), and outputs the bit clock B.
The image data SD having a width of 2 bits is serially converted in synchronism with CLK and output to the receiving circuit 28B ₁ . The frequency ratio (fb / fp = 4) between the pixel clock PCLK and the bit clock BCLK is the ratio (= 2) between the bit width of the input image data PD (= 8) and the bit width of the image data SD (= 2). It is the same as 8/2).

Further, the display module 25
Horizontal sync signal HD and vertical sync signal VD supplied from
Is also transferred to the receiving circuit 28B ₂ via the signal line.

FIG. 3 is a timing chart for explaining the operation of the output circuit 28A ₁ . In FIG. 3, the signal waveforms of the pixel clock PCLK and the bit clock BCLK, and the 8-bit 8-bit signal PD forming the image data PD input from the display module 25.
(1), PD (2), ..., PD (8) and the 2-bit signal SD of the image data SD output by the parallel-serial conversion circuit 37.
(1) and SD (2) are shown. Signal PD (1)
-PD (8) inputs parallel data X ₁ (1), ..., X ₁ (8) of 1 bit each in one cycle T ₁ , and in the next one cycle T ₂ (= T ₁ ), 1-bit parallel data X
Inputting ₂ (1), ..., X ₂ (8). Further, the parallel-serial conversion circuit 37, in one cycle T ₁ , receives the 8-bit data X input in parallel in the cycle immediately before the cycle T _1.
0 (1), X ₀ (2), ..., X ₀ (8) are rearranged in time series, and 2-bit signals SD (1), SD (2) synchronized with the bit clock BCLK are output. . In the next cycle T ₂ , the parallel-serial conversion circuit 37 receives the 8-bit data X input in parallel with the cycle T ₁ immediately before the cycle T _2.
2-bit signals SD (1), SD obtained by synchronizing ₁ (1), X ₁ (2), ..., X ₁ (8) with the bit clock BCLK.
(2) is converted to serial and output.

On the other hand, in the receiving circuit 28B ₁ , the PLL circuit 40 reproduces the bit clock BCLK by multiplying the frequency of the pixel clock PCLK transferred from the output circuit 28A ₁ by 4 and supplies it to the serial-parallel conversion circuit 41. To do. The serial-parallel conversion circuit 41 converts the 2-bit width image data SD transferred from the output circuit 28A ₁ into the bit clock BCL.
The image data SD captured in synchronism with K is converted into image data PD having an 8-bit width in parallel in parallel with the pixel clock PCLK and output.

Next, the circuit configuration of the serial / parallel conversion circuit 41 will be described. FIG. 4 is a schematic configuration diagram of the serial-parallel conversion circuit 41. Generally, when the pixel clock PCLK is transferred from the output circuit 28A ₁ to the receiving circuit 28B ₁ , the timing when the pixel clock PCLK reaches the receiving circuit 28B ₁ is shifted due to the circuit configuration in the digital still camera 1, and the pixel clock PCLK is transferred. Bits regenerated from PCLK
The clock BCLK and the transferred image data SD may not be accurately synchronized. In such a case, the phase of the image data SD with respect to the bit clock is shifted, so that the display image is deteriorated. Serial-parallel conversion circuit 4 shown in FIG.
1 has a function of correcting the phase shift of the image data SD with respect to the reproduced bit clock BCLK and converting the 2-bit width image data SD in parallel to the 8-bit width image data PD.

As shown in FIG. 3, the 2-bit width signal SD output from the output circuit 28A ₁ is composed of serial signals SD (1) and SD (2) each having a 1-bit width. The serial-parallel conversion circuit 41 shown in FIG. 4 shifts and temporarily stores seven cycles of one serial signal SD (1).
A register 50 and a shift register 53 for temporarily storing seven cycles of the other serial signal SD (2) are provided. One shift register 50 is composed of seven D flip-flops 50A to 50G connected in series in seven stages. That is, the data output terminal (Q) of the D flip-flop of the previous stage is connected to the data input terminal (D) of the D flip-flop of the next stage, and each of the D flip-flops 50A to 50G has a bit clock. BC
Each time the LK is input, the held data is moved from the previous stage to the next stage. The other shift register 53 also shifts
7 D flip-flops 5 as well as register 50
3A to 53G are connected in series in 7 stages.

"0", "1", "2", "of the first selector 51
The input terminals marked with 3 "are respectively connected to the first to fourth stages, the second to fifth stages, the third to sixth stages, and the fourth stage of the shift register 50. 4 held from eyes to 7th stage
Input parallel data of bit width. First selector 51
Selects any one of the input terminals marked with "0", "1", "2", and "3" by the control signal AD0, and the 4-bit width data input to the input terminal is stored in the upper bit register. Output to 52 and hold. Similarly, the second selector 54 "
The input terminals labeled with "0", "1", "2", and "3" are respectively connected to the first to fourth stages and the second stage of the shift register 53.
Stages to 5th stage, 3rd stage to 6th stage, 4th stage to 7th stage
The 4-bit width parallel data held at the stage is input.
The second selector 54 receives "0", "in response to the control signal AD1.
Select one of the input terminals marked with "1", "2", "3",
The 4-bit width parallel data input to the input terminal is output to and stored in the lower bit register 55.

Upper bit register 52 and lower bit
The register 55 takes in parallel data PD (1) and PD (2) of 4-bit width input to the data input terminal (D) each time the pixel clock PCLK is input,
Further, the held parallel data PD (1) and PD (2) are output from the data output terminal (Q). Then, the parallel data PD (1) and PD (2) are combined into an 8-bit width image data PD, which is output from the serial-parallel conversion circuit 41.

The first selector 51 and the second selector 54 described above receive the control signals AD0 and AD1 and receive parallel data SD (1) and SD for the bit clock BCLK.
When there is no phase shift in (2), 4-bit width data output from the D flip-flops in the first to fourth stages is selected, and when the phase shift is one cycle, Second
If 4-bit wide data output from the D flip-flops of the fifth to fifth stages is selected and the phase shift is two cycles, the D flip-flops of the third to sixth stages are selected. From the D flip-flops in the fourth to seventh stages are selected when the phase shift is 3 cycles. It will be. Since the phase shift is predicted in the design stage or development stage of the circuit of the digital still camera 1 or detected in the circuit inspection stage, the control signals AD0 and AD1 are set so as to correct the phase shift. Adjusted in advance.

The 8-bit width image data PD output by the serial-parallel conversion circuit 41 as described above is L shown in FIG.
After being output to the CD drive circuit 29, an image is displayed on the LCD 30.

As described above, according to the first embodiment, the PL
In the L circuit 40, from the low frequency pixel clock PCLK transferred from the output circuit 28A ₁ to the bit clock BCL
Since K is reproduced, the output circuit 28A ₁ to the receiving circuit 2
It is not necessary to transfer the bit clock BCLK to 8B ₁ . Therefore, the number of signal lines arranged between the output circuit 28A ₁ and the receiving circuit 28B ₁ can be reduced. In addition, since it is not necessary to transfer a high-frequency bit clock in the digital still camera 1, the circuit scale can be reduced, radiation noise can be suppressed, and the S / N ratio of the image signal can be improved. Becomes

Embodiment 2. FIG. 5 is a functional block diagram showing a schematic configuration of the interface device 27 ₂ according to the second embodiment of the present invention. Note that, in FIG. 5, the functional blocks denoted by the same reference numerals as those shown in FIG. 2 have substantially the same configuration as that described above, and detailed description thereof will be omitted.

The Y / R signal, the Cb / G signal and the Cr / B signal as image data PD are input in parallel to the output circuit 28A ₂ of the interface device 27 ₂ from the display module 25. Further, the parallel / serial conversion circuits 37A, 37B, and 37C are the same as those in the first embodiment.
The parallel-serial conversion circuit 37 operates in the same manner. That is, each of the parallel-serial conversion circuits 37A, 37B, 37C has Y
The / R signal, the Cb / G signal, and the Cr / B signal are captured, and the captured signals are synchronized with the 54 MHz (= 13.5 × 4 MHz) bit clock BCLK supplied from the bit clock generation circuit 35. The image data SD having a 2-bit width is serially converted and output. Each image data SD is transferred to the receiving circuit 28B ₂ via a signal line.

The 13.5 MHz pixel clock PCLK, the horizontal synchronizing signal HD and the vertical synchronizing signal VD output from the pixel clock generating circuit 36 are also transferred to the receiving circuit 28B ₂ via the signal line.

In the receiving circuit 28B ₂ , the PLL circuit 40 has an output circuit 28A ₁ similar to the first embodiment.
The bit clock BCLK obtained by multiplying the frequency of the pixel clock PCLK transferred from 4 by 4 is regenerated and supplied to the serial / parallel conversion circuits 41A, 41B and 41C, respectively. The serial-parallel conversion circuits 41A, 41B, and 41C are the same as those in the first embodiment.
The serial-parallel conversion circuit 41 operates in the same manner. That is, the serial / parallel conversion circuits 41A, 41B, and 41C respectively transfer the transferred Y / R signal of 2 bits width, Cb / G signal, and Cr.
/ B signal in synchronism with the bit clock BCLK, and then each of the captured signals is applied to the pixel clock PCLK.
In parallel with each other, the image data PD of each 8-bit width is converted in parallel and output. Then, each image data PD, the horizontal synchronizing signal HD, and the vertical synchronizing signal VD are output to the LCD drive circuit 29 shown in FIG.

As described above, according to the second embodiment, reception
The serial-parallel conversion circuits 41A, 41B, 41C on the side are PLL
The circuit 40 reproduces a plurality of bit clocks BCLK.
Color component data (Y / R signal, Cb / G signal, Cr / B signal
No.) can be used for each color component.
The output circuit 28A does not need to transfer the clock BCLK. ₂
And receiving circuit 28B₂Reduces the number of signal lines placed between
it can. Therefore, downsizing the circuit required for data transfer,
Reduction of radiation noise and improvement of S / N ratio of image signal
It is possible to plan.

Embodiment 3. FIG. 6 is a functional block diagram showing a schematic configuration of the interface device 27 ₃ according to the third embodiment of the present invention. Note that, in FIG. 6, the functional blocks denoted by the same reference numerals as those shown in FIG. 2 have substantially the same configuration as that described above, and a detailed description thereof will be omitted.

In the third embodiment, the display module 25 shown in FIG. 1 has an 8-bit wide CbCr signal in which the color difference signals of the Cb signal and the Cr signal are multiplexed and an 8-bit wide Y signal (luminance signal). ) And are output in parallel. Incidentally, I
TU-R Recommendation BT. According to 601, the component ratio of the Y signal, the Cb signal, and the Cr signal is Y: Cb: Cr = 4: 2 :.
Two can be adopted.

Output circuit 2 of interface device 27 ₃
At 8A ₃ , the parallel-serial conversion circuits 37A and 37B operate in the same manner as the parallel-serial conversion circuit 37 of the first embodiment, and fetch the Y signal and the CbCr signal, respectively. Each of the taken-in signals is synchronized with the 54 MHz bit clock BCLK supplied from the bit clock generation circuit 35 to generate 2 signals.
The image data SD having a bit width is serially converted and output, and is transferred to the receiving circuit 28B ₃ via a signal line.

The 13.5 MHz pixel clock PCLK, the horizontal synchronizing signal HD and the vertical synchronizing signal VD output from the pixel clock generating circuit 36 are also transferred to the receiving circuit 28B ₂ via the signal line.

In the receiving circuit 28B ₃ , the PLL circuit 40 has an output circuit 28A ₃ similar to the first embodiment.
The bit clock BCLK obtained by multiplying the frequency of the pixel clock PCLK transferred from 4 by 4 is regenerated and supplied to the serial / parallel conversion circuits 41A and 41B, respectively. The serial-parallel conversion circuits 41A and 41B are the same as the serial-parallel conversion circuit 41 of the above-described first embodiment.
The Cr signal is taken in in synchronism with the bit clock BCLK, and then each of the taken signals is supplied to the pixel clock PCLK.
The image data PD is converted into 8-bit width image data PD and output. The 8-bit wide image data PD, the horizontal synchronizing signal HD, and the vertical synchronizing signal VD are L shown in FIG.
It is output to the CD drive circuit 29.

As described above, the interface device 27 _{3 according to the} third embodiment has a structure in which two color difference signals are multiplexed.
Since one CbCr signal and one luminance signal are transferred, the number of signal lines arranged between the output circuit 28A ₃ and the receiving circuit 28B ₃ can be further reduced. Therefore, the circuit required for data transfer can be downsized, radiation noise can be reduced, and the S / N ratio of the image signal can be improved.

Fourth Embodiment In the third embodiment, the horizontal synchronizing signal H is output between the output circuit 28A ₃ and the receiving circuit 28B _3.
A signal line for transferring D and the vertical synchronizing signal VD is required. In the fourth embodiment of the present invention, the synchronization signal H
An interface device 27 ₄ capable of reducing the signal lines for transferring D and VD will be described. FIG. 7 is a functional block diagram of the interface device 27 _{4 according to} the _fourth embodiment. In FIG. 7, the functional blocks denoted by the same reference numerals as those shown in FIG. 6 have substantially the same configuration as that described above, and detailed description thereof will be omitted.

In the fourth embodiment, as in the third embodiment, the display module 25 shown in FIG. 1 has an 8-bit width CbCr signal and an 8-bit width Y signal in which color difference signals are multiplexed. The (luminance signal) is output to the interface device 27 ₄ in parallel. In the interface device 27 ₄ , as shown in FIG. 7, the upper 7 bits of the Y signal and the 1 bit of the horizontal synchronizing signal HD are combined, The parallel-serial conversion circuit 37A is input as the bit-width image data PD, and the upper 7 bits of the CbCr signal and the 1-bit of the vertical synchronization signal VD are combined to form the parallel-serial conversion circuit 37B as the 8-bit width image data PD. To enter. Further, both the horizontal synchronizing signal HD and the vertical synchronizing signal VD are inserted in the least significant bit of the image data PD.

On the other hand, in the receiving circuit 28B ₄ , the image data PD output from the serial-parallel conversion circuit 41A is separated into a 7-bit Y signal and a 1-bit horizontal synchronizing signal HD,
On the other hand, the image data PD output from the serial-parallel conversion circuit 41B is separated into a 7-bit CbCr signal and a 1-bit vertical synchronization signal VD. Also, although not clearly shown in FIG.
The separated Y signal and CbCr signal are added with the least significant bit of zero, and the data shown in FIG.
It is output to the D drive circuit 29.

As described above, according to the fourth embodiment, since the synchronizing signals HD and VD are inserted and transferred to the image data PD, the number of signal lines between the output circuit 28A ₃ and the receiving circuit 28B ₃ can be reduced. . Therefore, the circuit required for data transfer can be downsized, radiation noise can be reduced, and the S / N ratio of the image signal can be improved.

In the first to fourth embodiments described above, the digital
Although an example suitable for a camera has been described, the interface device according to the present invention is not limited to a digital camera, and can be applied to other devices that need data transfer. Further, the transfer data does not have to be limited to the image data.

[0055]

As described above, according to the interface device of the first aspect of the present invention, the receiving circuit is a PLL.
Since the circuit regenerates the bit clock from the low-frequency data clock (pixel clock) transferred from the output circuit, it is not necessary to transfer the high-frequency bit clock from the output circuit to the receiving circuit. Therefore, the number of signal lines arranged between the output circuit and the receiving circuit can be reduced, the circuit required for data transfer can be downsized, the generation of radiation noise due to the bit clock can be suppressed, and the image signal can be suppressed. Of S
It is possible to improve the / N ratio.

According to the second aspect, since the bit clock reproduced by the PLL circuit can be shared by a plurality of color component data, the number of signal lines arranged between the output circuit and the receiving circuit is reduced, and the circuit of the circuit is reduced. It is possible to reduce the size, reduce the radiation noise, and improve the S / N ratio of the image signal.

According to the third aspect, since the luminance signal and the signal in which a plurality of color difference signals are multiplexed can be transferred, the signal line provided between the output circuit and the receiving circuit is the amount corresponding to the multiplexed color difference signals. The number of can be reduced. Therefore, it is possible to further enhance the aforementioned effect of claim 2.

According to claim 4, among the signal lines arranged between the output circuit and the receiving circuit, the number of signal lines for synchronizing signal transfer can be reduced, so that the above-mentioned effects of claims 1 to 3 are further enhanced. It becomes possible.

According to the fifth aspect, since the serial-parallel conversion is executed while correcting the phase shift of the data of the N ₂ bit width with respect to the bit clock reproduced from the data clock, it results from the data transfer. Image quality deterioration can be prevented.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a configuration example of a digital still camera incorporating an interface device according to an embodiment of the present invention.

FIG. 2 is a functional block diagram showing a schematic configuration of the interface device according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the output circuit of the interface device according to the first embodiment.

FIG. 4 is a functional block diagram showing a schematic configuration of a serial-parallel conversion circuit of the interface device according to the first exemplary embodiment.

FIG. 5 is a functional block diagram showing a schematic configuration of an interface device according to a second embodiment of the present invention.

FIG. 6 is a functional block diagram showing a schematic configuration of an interface device according to a third embodiment of the present invention.

FIG. 7 is a functional block diagram showing a schematic configuration of an interface device according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional example of an interface device for transferring an analog composite signal.

FIG. 9 is a block diagram showing a conventional example of an interface device for transferring an analog signal.

FIG. 10 is a block diagram showing a conventional example of an interface device for transferring a digital signal.

FIG. 11 is a block diagram showing a conventional example of an interface device for transferring an analog signal.

FIG. 12 is a block diagram showing a conventional example of an interface device that converts a digital signal into a serial signal and transfers the serial signal.

[Explanation of symbols]

1 Digital Still Camera 27, 27 _{1 to} 27 ₄ Interface Device 28A, 28A _{1 to} 28A ₄ Output Circuit 28B, 28B _{1 to} 28B ₄ Reception Circuit 35 Bit Clock Generation Circuit 36 Pixel Clock Generation Circuit 37, 37A to 37C Serial conversion circuit 40 PLL circuit 41, 41A to 41C Serial-parallel conversion circuit

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Claims (5)

[Claims] 1. An interface device comprising an output circuit for transferring digital data and a receiving circuit for receiving the data transferred from the output circuit, wherein the output circuit comprises N ₁ bits (N ₁ is N ₂ A serial-to-serial conversion circuit that serially converts data having a width of N ₂ is 2 or more) into data having a width of N ₂ bits in synchronization with a bit clock and outputs the data to the receiving circuit. A bit clock generation circuit that generates a clock and outputs the clock to the parallel-serial conversion circuit, and a data clock generation circuit that generates and outputs a data clock at the timing when the data having the N ₁ bit width is input to the parallel-serial conversion circuit. And a circuit for receiving the data clock transferred from the output circuit by N times.
A PLL circuit for recovering a bit clock multiplied by ₁ / N _2; and data of the N ₂ bit width transferred from the output circuit, sequentially fetched in synchronization with the bit clock supplied from the PLL circuit, And a serial-parallel conversion circuit that converts the data into N ₁ -bit width data in parallel in synchronization with the data clock and outputs the data. 2. The interface device according to claim 1, wherein the parallel-serial conversion circuit of the output circuit converts each of a plurality of color component data forming image data from N ₁ bit width data to N ₂ bit data. The serial-to-parallel conversion circuit of the receiving circuit converts the plurality of N ₂ -bit width data transferred from the output circuit into N ₁ -bit width data in parallel. Interface device. 3. The interface device according to claim 2, wherein the plurality of color component data includes luminance data and color difference data multiplexed in pixel units. 4. The interface device according to claim 1, wherein a synchronizing signal for video display is inserted into a part of bits of the N ₁ bit width data in the output circuit. Interface device. 5. The interface device according to claim 1, wherein the serial-parallel conversion circuit of the receiving circuit has the N ₂ bit width over a plurality of cycles of the bit clock. a shift register for temporarily storing data in accordance with the control signal supplied from the outside, from the shift register, so as to correct the phase shift of the data of the N _2-bit width to the bit clock N _An interface device including a selector that selects _1- bit width data and outputs the data in parallel.