JP2003101883A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform application to an electronic still camera for instance and to process output signals of an image pickup element by a sufficient phase margin even in the case that a number of pixels increases regarding an image pickup device. SOLUTION: A reset pulse ϕResetA is outputted for each plurality of pixels and a solid-state image pickup element 12 is driven so as to output an integrated value of stored electric charges successively for a plurality of the pixels. Also, in a signal processing of an image pickup result ϕVoutA, the output signals of the solid-state image pickup element ϕVoutA by the integrated values are successively sampled and held and a difference value is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device,
For example, it can be applied to an electronic still camera. The present invention outputs a reset pulse for each of a plurality of pixels, drives the solid-state image sensor so as to sequentially output the integrated value of the accumulated charges for the plurality of pixels, and performs the signal processing of the imaging result in By sequentially holding and sampling the output signal of the solid-state image sensor based on the integrated value and detecting the difference value, it is possible to process the output signal of the image sensor with a sufficient phase margin even when the number of pixels increases. .

[0002]

2. Description of the Related Art Conventionally, in an image pickup apparatus such as an electronic still camera, a CCD (Charge Coupled Device) solid-state image pickup element sequentially outputs an image pickup result in a raster scanning order, and the image pickup result is output to a pixel by a correlated double sampling circuit. It is designed to process sequentially in units.

That is, FIG. 3 is a block diagram showing a peripheral structure of a CCD solid-state image pickup device (CCD) 2 in a conventional electronic still camera. CCD solid-state image sensor 2
The vertical transfer registers extending in the vertical direction are arranged in the horizontal direction at a predetermined pitch, and the photoelectric conversion units forming the pixels are arranged along the vertical transfer registers. CCD
In the solid-state imaging device 2, one end of these vertical transfer registers is connected to a horizontal transfer register extending in the horizontal direction, and an output unit (floating diffusion amplifier) is arranged at the end of the horizontal transfer register.

The CCD solid-state image pickup device 2 transfers the accumulated charge accumulated in each photoelectric conversion section to a vertical transfer register by a predetermined drive pulse output from the timing generator (TG) 3 and then similarly from the timing generator 3. The accumulated charges are sequentially transferred in the vertical transfer register by the supplied vertical transfer pulse, and thereby the accumulated charges are transferred to the horizontal transfer register line by line.

The horizontal transfer pulse φH-tr output from the timing generator 3 causes the horizontal transfer register to sequentially transfer the accumulated charges to the output section every time the accumulated charges for one line are transferred to the horizontal transfer register. As a result, the CCD solid-state image pickup device 2 sequentially outputs the accumulated charge of each pixel to the output section in the order of raster scanning, and outputs the image pickup result via this output section.

Here, in the output section, a predetermined capacity is charged by the accumulated charge transferred from the horizontal transfer register in this way, and the charge charged in this capacity by the reset pulse φReset output from the timing generator 3. Is reset. The output unit outputs the terminal voltage of the capacitor obtained by charging the capacitor in this way to the outside as an imaging result.

As a result, the CCD solid-state image sensor 2 accumulates one pixel by the horizontal transfer pulse φH-tr after the charge charged in the capacitance of the output portion is reset by the reset pulse φReset output from the timing generator 3. The electric charges are charged in this capacitance, and by repeating this processing in synchronization with the horizontal transfer pulse φH-tr, the imaging result by the accumulated electric charges of each pixel is output.

As a result, in the output signal φVout of the CCD solid-state image pickup device 2, the horizontal transfer pulse φH-tr.
The master clock φMa that is the generation reference in FIG. 4B.
After the signal level rises due to the inclusion of the reset pulse φReset (FIG. 4 (B)) in units of two cycles T of the star (FIG. 4 (A)), the output value LP by the precharge unit, the output value of the data unit LDs are output so as to be continuous. Here, the precharge unit is reset pulse φRe
The portion of the potential due to the terminal voltage of the capacitance described above in the state where the electric charges are discharged by the set, and the data portion is the portion of the potential due to the terminal voltage of the above capacitance when charged with the accumulated electric charges.

As a result, in the output signal φVout thus obtained, the difference value between the output value LP of the precharge section and the output value LD of the data section accurately indicates the accumulated charge amount of each pixel. Become. Further, in the electronic still camera 1, it is also necessary to remove 1 / f noise from the output signal φVout of the image pickup result obtained in this way.

Therefore, the correlated double sampling circuit (CD
As shown in FIG. 5, the S: Correlated Double Sampling) 4 outputs the output value LP of the precharge unit in the sample hold circuit (S / H) 4A by the first sample hold pulse φSHP output from the timing generator 3.
Is sample-held (FIGS. 5A and 5B). Further, by the second sample hold pulse φSHD (FIG. 5 (C)) output from the timing generator 3, the sample hold circuit (S / H) 4B samples and holds the output value LD of the data section, and also the sample hold circuit 4A. The sample-and-hold value (output value LP by the precharge unit) is sample-held by the sample-and-hold circuit (S / H) 4C.

Further, the subtraction circuit 4D subtracts the output value LD of the data portion sample-held by the sample-hold circuit 4B from the output value LP of the precharge portion sample-held by the sample-hold circuit 4C. The image pickup signal S1 having a continuous signal level corresponding to the accumulated charge amount of each pixel is output.

Timing generator 3
Generates and outputs various drive signals for the CCD 2 and the correlated double sampling circuit 4, etc., and the electronic still camera 1
Then, the image pickup signal S1 is signal-processed on the basis of the drive signal of the timing generator 3 and displayed on the display device,
Further, the data is compressed and recorded on a predetermined recording medium.

[0013]

By the way, in this type of image pickup apparatus, the driving frequency tends to increase due to the increase in the number of pixels of the CCD solid-state image pickup element.
As shown in, the period TP of the precharge portion and the period TD of the data portion also tend to be short.

As a result, in the image pickup apparatus having the conventional configuration, the phase margin of the sample hold with respect to the precharge section and the data section becomes narrow in the processing of correlated double sampling, and the phase control of the sampling pulse must be stricter accordingly. There was a problem that the system design was difficult after all.

As one method for solving these problems, for example, Japanese Patent Application Laid-Open No. 9-9000 proposes a method of synthesizing and accumulating charges accumulated by consecutive pixels inside a CCD solid-state image pickup device. However, in the case of this method, there is a problem that the resolution of the imaging result is lowered.
As a result, although it can be applied when monitoring the imaging result, it cannot be applied when actually recording the imaging result in the recording medium.

The present invention has been made in consideration of the above points, and proposes an image pickup apparatus capable of processing an output signal of an image pickup element with a sufficient phase margin even when the number of pixels increases. Is.

[0017]

In order to solve such a problem, in the invention of claim 1, the timing generator outputs a reset pulse for every plural pulses of the transfer pulse, so that during the period of the plural pulses. ,
In synchronism with the transfer pulse, the accumulated charge of each pixel is sequentially added to charge the capacitance of the output section of the solid-state image sensor, and the signal processing circuit continues in synchronism with the transfer pulse in the period of the plurality of pulses. The imaging result is sequentially sampled, and a subtraction value is generated between consecutive sampling results, so that the imaging result corresponding to each pixel of the solid-state imaging device is output.

According to the structure of the first aspect, the timing generator outputs the reset pulse for every plural pulses of the transfer pulse, so that the pixel of each pixel is synchronized with the transfer pulse during the period of the plural pulses. The accumulated charge is sequentially added to charge the capacitance of the output section of the solid-state image pickup device, and the signal processing circuit sequentially samples the consecutive imaging results in synchronism with the transfer pulse in the period of the plurality of pulses and continuously. By generating the subtraction value between the sampling results to output the imaging result corresponding to each pixel of the solid-state image sensor, for example, when the image sensor is a CCD solid-state image sensor, these plural pulses In between, the sampling result corresponding to each pixel of the solid-state image sensor can be obtained by sampling the number of pulses + 1 times. On the other hand, in the case of the conventional configuration, each pixel needs to be sampled twice. As a result, according to the configuration of claim 1, the output signal of the image sensor is processed with a sufficient phase margin even when the number of pixels is increased by the number of times of sampling can be reduced as compared with the conventional case. You can

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 1 is a block diagram showing an electronic still camera which is an image pickup apparatus according to an embodiment of the present invention. In the electronic still camera 11, the same components as those of the electronic still camera 1 described above with reference to FIG.
A duplicate description will be omitted.

In this electronic still camera 11, CC
The D solid-state imaging device 12 is configured in the same manner as the CCD solid-state imaging device 2 described above with reference to FIG. 3, except that the operation is partly different due to the different drive signals output from the timing generator 13.

That is, the CCD solid-state image pickup device 12 sequentially transfers the accumulated charge of each pixel to the output section in synchronization with a predetermined transfer pulse to charge the capacity of the output section, and at the same time, by the predetermined reset pulse, changes the capacity of this capacity. The electric charge is discharged, and the output section supplies a voltage corresponding to the electric charge of the capacitance to the imaging signal φ.
Output as VoutA.

As shown in FIG. 2, in the CCD solid-state image pickup device 12, the reset pulse φResetA (FIG. 3B) output in synchronization with the master clock φMaster (FIG. 3A) is generated by the horizontal transfer register. With respect to the transfer of the accumulated charge (FIG. 3C), it is supplied so as to rise intermittently every two cycles. That is, the CCD solid-state image sensor 12
In contrast to the prior art, as indicated by the symbol A, the reset pulse φResetA is supplied by thinning out every other cycle.

In the CCD solid-state image pickup device 12, after the charge of the capacitance is reset by the reset pulse φResetA at the output portion, the charge accumulated by the first pixel is input from the horizontal transfer register, and further by the first pixel. With the accumulated charge being held, the accumulated charge of the subsequent second pixel is controlled to flow from the horizontal transfer register.

As a result, in the CCD solid-state image sensor 12, after the signal level rises due to the mixing of the reset pulse φResetA, the output value LP of the precharge section, the output value LD1 of the accumulated charge of the first pixel, and the first value Signal LD according to the total value of the accumulated charge of the pixel of
The image pickup signal φVoutA is output by repeating 2 (FIG. 2D).

That is, the CCD solid-state image pickup device 12 has a horizontal transfer pulse φ corresponding to the reset pulse φResetA.
Horizontal transfer pulse φH-tr for each multiple pulses of H-tr
In synchronism with the above, the image pickup signal φVoutA obtained by sequentially adding and accumulating the accumulated charge of each pixel to the capacitance of the output section is output.

With these, the timing generator 13
3 except that a reset pulse φResetA is output for each of a plurality of horizontal transfer pulses φH-tr.
The CCD solid-state image sensor 12 is driven by the same drive signal as that of the timing generator 3 described above.

Further, the timing generator 13 outputs the first and second sample and hold pulses φSHP and φSHD (FIGS. 2E and 2F) corresponding to the precharge portion and the data portion for each pixel, respectively. First
Sample hold pulse φSHP of AND circuit 14A
To the AND circuits 14B, 14C and 14D. Further, the timing generator 13 uses the reset pulse φRes
In the output cycle of etA, the first half 1/2 cycle and the second half 1
Mask pulse φM whose signal level is switched between / 2 cycles
DK (FIG. 2G) is generated from the master clock φMaster, and this mask pulse φMDK is supplied to the AND circuit 14
It is input to A to 14C, and the inverted signal of the mask pulse φMDK is input to the AND circuit 14D.

As a result, the timing generator 13
The AND circuit 14A generates a sample hold pulse corresponding to the precharge section, while the AND circuits 14B and 14C generate a sample hold pulse for the leading data section LD1. Also AND circuit 1
4D generates a sample hold pulse for the subsequent data section LD2.

The timing generator 13 inputs the output signals of the AND circuits 14A and 14B to the switch circuit (SW) 15A and inputs the output signals of the AND circuits 14C and 14D to the switch circuit (SW) 15B. The timing generator 13 switches the operation of these switch circuits 15A and 15B by a mask pulse φMDK,
The output signal of the switch circuit 15A is supplied to the sample hold circuit 4A of the correlated double sampling circuit 4, while the output signal of the switch circuit 15B is supplied to the sample hold circuits 4B and 4C.

Thus, in the correlated double sampling circuit 4, when the reset pulse φResetA is output, the output signals of the AND circuits 14A and 14C are output to the correlated double sampling circuit 4 and the reset pulse φR is output.
At the time point t1 (FIG. 2) of the fall of the first sample hold pulse φSHP immediately after the output of resetA, the sample hold circuit 4A causes the potential LP of the precharge portion to rise.
Sample hold. At time t2 when the second sampling and holding pulse SHD falls, the potential LP of the precharge portion sampled and held by the sampling and holding circuit 4A is sampled and held by the sampling and holding circuit 4C, and the sampling and holding circuits 4A and 4B are also held.
Then, the potential LD1 of the first data portion is sampled and held.

Thus, in the correlated double sampling circuit 4, the potential difference between the potential LP of the precharge portion sample-held by the sample-hold circuit 4B and the potential LD1 of the first data portion sample-held by the sample-hold circuit 4B is calculated. The subtraction circuit 4D outputs it.

After that, AND circuits 14A and 14C
Instead of outputting the output signals of the AND circuits 14B and 14D to the correlated double sampling circuit 4, at the time t3 of the trailing edge of the second sample hold pulse SHD,
The potential LD1 of the data portion sampled and held by the sample and hold circuit 4A is sampled and held by the sample and hold circuit 4C, and the sample and hold circuits 4A and 4 are
The potential LD2 of the second data portion is sample-held by B, the potential LD1 of the first data portion sample-held by the sample-hold circuit 4B, and the potential LD of the second data portion sample-held by the sample-hold circuit 4B.
The potential difference with respect to 2 is output from the subtraction circuit 4D.

As a result, in the correlated double sampling circuit 4, by driving the timing generator 13,
Horizontal transfer pulse φ by reset pulse φResetA
In the period of a plurality of pulses of H-tr, consecutive imaging results φVout are synchronized with the horizontal transfer pulse φH-tr.
By sequentially sampling A and generating a subtraction value between consecutive sampling results, the imaging result S2 corresponding to each pixel of the solid-state imaging device 12 is output.

(2) Operation of Embodiment With the above configuration, the electronic still camera 11
Imaging result φVou obtained from the CDD solid-state imaging device 12
After tA is processed by the correlated double sampling circuit 4, it is processed by a predetermined signal processing circuit, displayed on a display device, and recorded on a predetermined data recording medium.

In the electronic still camera 11, in the CDD solid-state image pickup device 12, each pixel is composed of photoelectric conversion units arranged in a matrix, and the charge accumulated by each pixel is transferred to the horizontal transfer register via the vertical transfer register. Then, by the operation of this horizontal transfer register synchronized with the horizontal transfer pulse φH-tr, the signals are sequentially supplied to the output section. Further, in the output section, the potential generated by charging a predetermined capacitance with the accumulated charge is the image pickup signal φVout.
A is output to the correlated double sampling circuit 4.

In the electronic still camera 11, in this output section, every plural pulses of the horizontal transfer pulse φH-tr,
After the reset pulse φResetA is output, and thereby the potential LP of the precharge portion formed by first discharging the capacitance of the output portion is obtained, the accumulated charge of each pixel is sequentially added in synchronization with the horizontal transfer pulse. An image pickup signal φVoutA obtained by charging this capacitance is obtained.

As a result, in the electronic still camera 1,
Corresponding to the output signal φVoutA of the CCD solid-state image sensor 12, the correlated double sampling circuit 4 obtains the potential LP of the precharge portion, and then sequentially accumulates the charges accumulated in each pixel in synchronization with the transfer pulse. Potential L added
An image pickup signal S2 having a signal level corresponding to each pixel is obtained by sequentially sampling and holding D1 and LD2 and detecting a difference value.

In the sample hold in the correlated double sampling circuit 4 executed in this way, C
In the output signal φVoutA of the CD solid-state image pickup device 12, after the potential LP of the precharge portion is first obtained, potentials LD1 and LD2 obtained by sequentially adding the accumulated charges of each pixel are obtained in synchronization with the transfer pulse. As a result, these potentials LP, LD1 and LD2 are sequentially sampled,
The image pickup signal S2 can be obtained. That is, the sampling result corresponding to the accumulated charge amount of each pixel can be obtained by sampling n + 1 times with respect to the pulse number n of the horizontal transfer pulse φH-tr between the reset pulses φResetA.

On the other hand, when the reset pulse is output for each pixel (FIG. 4), the potential LP of the precharge section and the potential LD of the data section are continuous for each pixel, so that these precharges are performed. It is necessary to carry out sampling twice for each pixel depending on the timing corresponding to the copy section and the data section.

As a result, in this embodiment, the output signal of the image pickup device can be processed with a sufficient phase margin even when the number of pixels is increased because the number of times of sampling is smaller than in the conventional case.

Further, in this embodiment, by changing the structure of the timing generator 13 and changing the driving of the correlated double sampling circuit having the same structure as the conventional one, the CCD is changed.
By processing the output signal φVout of the solid-state image pickup device 12, sample-holding the potentials LD1 and LD2, detecting the difference value, and obtaining the image pickup signal S2 at the signal level corresponding to each pixel, in comparison with the conventional configuration. A sufficient phase margin can be secured by simply changing the configuration. In addition, the CCD solid-state image sensor 12, the correlated double sampling circuit 4
Can be configured the same as the conventional configuration.

Further, the timing generator 13 can be configured so as to be suitable for the processing of the output signal φVout of the CCD solid-state image pickup device 12, and a phase margin can be further added to the two samplings in the first pixel. By doing so, it is possible to further simplify the phase management of the sample and hold pulse and to simplify the overall configuration.

In the sample-hold circuit 4A and the like, the charge injection time into the capacitor used for sample-hold is set by the duty of the sample-hold pulse. If the number of samplings can be reduced in this way, As for the duty of the sample hold pulse, the management can be simplified, and the entire configuration can be simplified accordingly.

(3) Effects of the Embodiments According to the above-described configuration, the reset pulse is output for each of a plurality of pixels, and the solid-state imaging is sequentially performed for the plurality of pixels so that the integrated value of the accumulated charge is output. In addition to driving the element, in the signal processing of the image pickup result, the output signal of the solid-state image pickup element by these integrated values is sequentially sampled and held to detect the difference value, so that even if the number of pixels increases, there is sufficient phase margin. The output signal of the image sensor can be processed.

Further, by changing the driving of the correlated double sampling circuit according to the conventional structure and sequentially sampling and holding the output signal of the solid-state image pickup device to detect the difference value, it is possible to pick up an image with a sufficient phase margin with a simple structure. The output signal of the device can be processed.

(4) Other Embodiments In the above-described embodiments, the case where the reset pulse is output for every two pixels has been described, but the present invention is not limited to this, and for every plural pixels of three or more pixels. Even if the reset pulse is output to the above, the same effect can be obtained.

Further, in the above-mentioned embodiments, the case where the present invention is applied to the image pickup device of the single plate type has been described, but the present invention is not limited to this and can be widely applied to the image pickup device of the three plate type. .

In the above embodiment, the case where the present invention is applied to an electronic still camera has been described.
The present invention is not limited to this, and is integrated with, for example, an image pickup device having a recording function such as a video tape recorder with a camera, an image pickup device having a communication function such as a mobile phone, and further integrated with a personal computer. It can be widely applied to various image pickup devices.

[0050]

As described above, according to the present invention, the reset pulse is output for each of a plurality of pixels, and the solid-state image pickup device is driven so that the integrated value of the accumulated charge is sequentially output for the plurality of pixels. In addition, in the signal processing of the image pickup result, the output signal of the solid-state image pickup device based on these integrated values is sequentially sampled and held to detect the difference value, so that even if the number of pixels increases, the image pickup device has a sufficient phase margin. The output signal can be processed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electronic still camera according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the electronic still camera shown in FIG.

FIG. 3 is a block diagram showing a conventional electronic still camera.

FIG. 4 is a time chart for explaining the operation of the electronic still camera shown in FIG.

FIG. 5 is a time chart for explaining a sample hold pulse.

[Explanation of symbols]

1, 11 ... Electronic still camera, 2, 12 ... CCD solid-state image sensor, 3, 13 ... Timing generator, 4
...... Correlated double sampling circuit, 4A to 4H …… Sample and hold circuit

Claims (2)

[Claims] 1. A solid-state imaging device for outputting an imaging result, a timing generator for generating a drive signal for the solid-state imaging device, and a signal processing circuit for processing the imaging result. The charge accumulated in each pixel is sequentially transferred to the output unit in synchronization with the transfer pulse to charge the capacitance of the output unit, and the charge of the capacitance is discharged by a predetermined reset pulse, and the output unit is Outputs a voltage according to the charge as the imaging result, and the timing generator outputs the reset pulse for each of the plurality of pulses of the transfer pulse, thereby synchronizing with the transfer pulse during the period of the plurality of pulses. Then, the charge accumulated in each pixel is sequentially added to charge the capacitor, and the signal processing circuit is configured to transfer the transfer pattern during the period of the plurality of pulses. The continuous imaging result is sequentially sampled in synchronism with the pulse, and the subtraction value is generated between the continuous sampling results to output the imaging result corresponding to each pixel of the solid-state imaging device. Image pickup device. 2. The signal processing circuit is a correlated double sampling circuit that subtracts and outputs a sample hold result of the imaging result by the first and second sample hold circuits, and the timing generator is configured to output the plurality of pulses. 2. The drive signal for the correlated double sampling circuit is generated so that the first and second sample and hold circuits sequentially sample the consecutive image pickup results during the period.
The imaging device according to.