JP2003101597A - Frequency demodulation method and processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency demodulation method and a processor which has comparatively low signal throughput for a receiving system and demodulates a frequency-modulated data accurately without increasing delays. SOLUTION: This frequency demodulation comprises is so constituted that, for the frequency-modulated data obtained by frequency-modulation of input data, a demodulation circuit that converts a scalar signal in passband into a vector signal in baseband by demodulating frequency modulated data obtained by frequency modulated input data with an intermediate carrier frequency of binary data values, a difference circuit that obtains phase deviation from the phase differences for a vector signal in the baseband obtained from the demodulation circuit, and a determination circuit that determines the binary data value for the input data based on the phase deviation obtained from the difference circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency demodulation method and a processor, and more particularly to frequency demodulation of data frequency-modulated by a frequency modulation method for performing frequency modulation using a common filter for a number of carrier frequency modes. The present invention relates to a frequency demodulation method and a processor and a modem device that employ such a frequency demodulation method.

[0002]

2. Description of the Related Art Conventionally, various modem devices adopting a frequency modulation method have been proposed. When using a plurality of carrier frequencies, the modem device on the transmission side needs to be provided with a filter for each carrier frequency. On the other hand, in the modem device on the receiving side, in order to judge the received data, it is necessary to provide a bandpass filter having a pass band at a frequency corresponding to the original binary data value. The original binary data value is determined by the presence / absence of output of each bandpass filter.

[0003]

However, when the number of filters corresponding to a plurality of carrier frequencies is provided, the design load becomes large, the configuration of the modem device becomes complicated, and the modem device cannot be manufactured at low cost. There was a problem.

On the other hand, in order to perform analog / digital conversion on the received data and judge the data by digital signal processing, it was necessary to use a narrow bandpass filter. However, in order to realize a narrow bandpass filter, it is necessary to set a large number of taps in the bandpass filter in order to satisfy sufficient cutoff characteristics. Also, there is a problem that the delay increases and it is difficult to improve the performance of the modem device.

Therefore, the present invention has a simple and inexpensive structure,
In addition, a frequency demodulation method for frequency demodulating data frequency-modulated by a frequency modulation method capable of suppressing an increase in delay by relatively reducing the signal processing amount, and a processor and a modem device adopting such a frequency demodulation method The purpose is to provide.

[0006]

SUMMARY OF THE INVENTION The above problem is that a passband scalar signal is generated by demodulating frequency-modulated data obtained by frequency-modulating input data at a carrier frequency intermediate between binary data values. A demodulation means for converting into a band vector signal, a difference means for obtaining a phase shift amount from a phase difference between the baseband vector signals obtained from the demodulation means, and a phase shift amount obtained based on the phase shift amount obtained from the difference means. It can be achieved by a processor having a judging means for judging the binary data value of the input data. In this case, since the frequency change of the baseband vector signal obtained from the demodulating means is obtained from the phase shift amount based on the phase difference, the signal processing amount of the receiving system is relatively small and the delay amount does not increase. The frequency-modulated data can be demodulated accurately.

The difference means may include means for normalizing the baseband vector signal obtained from the demodulation means. In this case, by obtaining the phase shift amount from the normalized baseband vector signal, an accurate phase shift amount can be obtained regardless of the data transmission rate.

The determining means determines a binary data value of the input data based on the polarity of the phase shift amount.
May be included. In this case, the binary data value of the input data can be accurately determined with a simple circuit configuration. The judging means may further include second means for holding the judgment result of the binary data value corresponding to the polarity for a certain holding time after the first means judges the polarity of the phase shift amount. . In this case, chattering at the time of determining the binary data value can be prevented.

The processor may further include means for holding the value of the binary data at a predetermined value when the carrier is off. In this case, by preventing so-called dust data from being output, malfunction of an external device or the like can be prevented.

The difference means is a first circuit for normalizing the baseband vector signal obtained from the demodulation means, and a second circuit for obtaining the phase difference of the vector signal based on the normalized vector signal. And a third circuit for converting the phase difference of the vector signal into a phase shift amount. Further, the difference means may further include a fourth circuit which holds the value of the binary data at a predetermined value when the carrier is off. In this case, by obtaining the phase shift amount from the normalized baseband vector signal, an accurate phase shift amount can be obtained regardless of the data transmission rate.

The processor may further comprise an interpolator means for converting the sampling frequency of the phase shift amount obtained from the difference means and supplying it to the judging means. In this case, the amount of jitter of received data can be reduced.

The above problem is that the frequency-modulated data obtained by frequency-modulating the input data is demodulated at the carrier frequency intermediate between the binary data values to convert the passband scalar signal into the baseband vector signal. Demodulation step, a difference step of obtaining a phase shift amount from the phase difference of the baseband vector signal obtained in the demodulation step, and binary data of the input data based on the phase shift amount obtained in the difference step. And a frequency demodulation method including a determination step of determining a value. in this case,
Since the frequency change of the baseband vector signal obtained in the demodulation step is calculated from the phase shift amount based on the phase difference, the signal processing amount of the receiving system is relatively small and the delay amount does not increase. The modulated data can be demodulated accurately.

Therefore, according to the present invention, the frequency change of the baseband vector signal obtained by the demodulation means or the demodulation step is obtained from the phase shift amount based on the phase difference. Is relatively small and the delay amount does not increase, so that the frequency-modulated data can be accurately demodulated.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, (a) shows the transmission system of the modem device,
(B) shows a receiving system of the modem device.

In the transmission system shown in FIG. 1A, binary input data A (0) and Z (1) are converted into signal points of 1 (A) and -1 (Z), and if necessary, the band. The signal is subjected to signal processing such as limitation and input to the frequency shift circuit 1. The frequency shift circuit 1 applies frequency shift corresponding to a binary data value to input data. The bandpass filter 2 applies a common band limitation to the output of the frequency shift circuit 1. The modulation circuit 3 frequency-modulates the output of the bandpass filter 2 with an intermediate carrier frequency of binary data values. The frequency-modulated data output from the modulation circuit 3 is subjected to signal processing as necessary and transmitted to the transmission medium.

On the other hand, in the receiving system shown in FIG.
The frequency-modulated data received via the transmission medium is subjected to signal processing as necessary and input to the demodulation circuit 11. The demodulation circuit 7 demodulates the frequency-modulated data at a carrier frequency intermediate between the binary data values. The difference circuit 8 obtains the frequency change of the baseband vector signal obtained from the demodulation circuit 7 from the phase shift amount based on the phase difference. The determination circuit 9 determines the binary data value of the binary input data based on the frequency change obtained from the difference circuit 8.

According to the present invention, even if there are a large number of carrier frequencies, the common bandpass filter 2 limits the common band, so that the structure of the transmission system of the modem device is simple and the modem device can be manufactured at low cost. can do. Further, since the frequency change of the baseband vector signal obtained from the demodulation circuit 7 is obtained from the phase shift amount based on the phase difference, the signal processing amount of the receiving system is relatively small and the delay amount does not increase. The frequency-modulated data can be demodulated accurately.

[0018]

2 is a block diagram showing an embodiment of a modem device according to the present invention. The embodiment of the modem device adopts one embodiment of the processor according to the present invention and one embodiment of the frequency demodulation method according to the present invention.

In FIG. 2, the modem device generally comprises a microprocessor unit (MPU) 11 and a digital signal processor (DSP) 12. MPU11
Is composed of a signal point generation circuit 21 and a setting acquisition unit 23. On the other hand, the DSP 12 includes a first bandpass filter 31, a frequency shift circuit 32, a second bandpass filter 33, an interpolator (interpolator) 34, and a modulation circuit 35.
And a transmission system including the carrier input circuit 36, a decimator (decimator) 41, a demodulation circuit 42, a carrier input circuit 43, a roll-off filter 44, a difference circuit 45, a carrier detection circuit 46, an interpolator 47, and a determination circuit 48. And a receiving system including. In addition, in FIG. 2 and an equivalent circuit diagram and a block diagram described later, a signal line indicated by a single solid line indicates a scalar signal line, and a signal line indicated by a double solid line indicates a vector signal line.

First, the transmission system of the modem device will be described.

In the signal point generating circuit 21 and the setting fetching section 23 in the MPU 11, for example, input binary data A input to the modem device from a host device (not shown), respectively.
(0), Z (1) and the mode setting signal are input.
The input binary data A (0) and Z (1) are converted into signal points of 1 (A) and -1 (Z) by the signal point generation circuit 21 in the MPU 11, and the first bandpass filter in the DSP 12 is provided. It is input to 31. This first bandpass filter 3
1 is provided to limit the signal frequency band to within the frequency band of the transmission medium that transmits the frequency-modulated data. Since the most bandwidth is required when the transmission speed used is the highest, the characteristics of the first bandpass filter 31 are as follows.
It is set according to the maximum transmission speed.

The mode setting signal is the mode of the modem device,
That is, the maximum transmission speed is set. In this embodiment, for convenience of explanation, it is assumed that the modem device has, for example, four modes. These four modes, namely the first, second, third and fourth modes, are 200 bps and 300 bp, respectively.
s, 600 bps and 1200 bps. The setting fetching unit 23, based on the mode setting signal,
It generates and outputs a control signal or the like for controlling each part in 12 according to the set mode. Note that, in FIG. 2, only a part of the control signal lines from the setting fetching unit 23 to each unit in the DSP 12 is shown in order to make the drawing easy to see.

FIG. 3 is an equivalent circuit diagram of the first bandpass filter 31. In the figure, “τ / n” is a delay corresponding to the sample time, “×” is multiplication, “Σ” and “+” are additions, and addition “+” to which RN is input indicates rounding by the coefficient RN. SD is input binary data, SD1 to SDN are delayed binary data, C1 to CN are multiplication coefficients, and TF1.
Indicates the output of the first bandpass filter 31. For example, the number of taps N is 21. The multiplication coefficients C1 to CN are
Based on the control signal input from the setting acquisition unit 23 in the MPU 11 shown in FIG. 2 according to the mode setting signal, R
It is read from the OM 31a. The multiplication coefficients C1 to CN
May be directly input from the setting fetching unit 23 according to the mode setting signal.

FIG. 4 is a diagram showing the characteristics of the first bandpass filter 31. In the figure, the vertical axis represents the amplitude spectrum P.
In arbitrary units, and the horizontal axis represents frequency f in kHz. For convenience of explanation, the sampling frequency of the input binary data is 2
8.8 kHz, maximum transmission rate is 1200 bps
(4th mode). The first bandpass filter 31 converts the sampling frequency from 28.8 kHz to 7.2 kHz by ¼ decimation in order to secure a band that is not easily affected by code distortion and reduce the amount of calculation, and the fourth bandpass filter 31 Filter calculation is performed for each.
At the time of this conversion, the characteristic of the first bandpass filter 31 is set so that there is no attenuation up to 1.8 kHz, as shown in FIG. 4, so that the aliasing component does not affect the used band. There is.

The output of the first bandpass filter 31 is
The frequency shift circuit 32 causes the input binary data A (0),
The frequency deviation ± Δf corresponding to the data values A and Z of Z (1) is applied. For example, ITU Recommendation V. 23, and the maximum transmission speed is 1200 bps (fourth mode), A
= 2100 Hz, Z = 1300 Hz, the frequency shift amount is ± 400 Hz from the center (carrier) frequency 1700 Hz,
The amount of phase shift at a sampling frequency of 7.2 kHz is 40
0Hz × 360 ° / 7.2kHz = 20 ° = 0.349
It is 06585 radians. Therefore, the phase shift amount θ in the frequency shift circuit 32 is equal to the sampling frequency 7.
The phase shift amount at 2 kHz is the first bandpass filter 3
Since the output value of 1 is multiplied by −1 to +1, −0.349
It becomes 06585- + 0.34906585 radians.
This phase shift amount θ is converted into a vector of cos and sin, and the phase sum is calculated for each sample to obtain −400 Hz to +.
A signal having a frequency deviation ± Δf of 400 Hz is output from the frequency deviation circuit 32. FIG. 5 shows a frequency shift circuit 32.
2 is an equivalent circuit diagram of FIG. The frequency shift circuit 32 includes a conversion unit 32a for converting the phase shift amount θ into a vector of cos and sin, an inverse calculation unit 32b, and a calculation unit for separately calculating a real number and an imaginary number for vector calculation. 32
It consists of c and. In the figure, “τ / n” is the delay and “|| ² ”.
Is the square of the absolute value, "x" is multiplication, "+" is addition, and "x" and "+" with RN as input indicate rounding by the coefficient RN. Further, DLTF is a signal indicating a deviation angle / sample (amount of phase deviation) in radians, and even if it is inputted from the setting fetching section 23 in the MPU 11 shown in FIG. 2 according to the mode setting signal, as will be described later. , May be generated in the frequency shift circuit 32 based on the control signal from the setting fetching unit 23. The signal DLTF is, in this embodiment, the amount of frequency deviation / sampling frequency × 2π = ± Δf / 7.2 kHz × 2π. DFRR represents a real part and DFII represents an imaginary part, which are respectively input to a second bandpass filter 33 described later.

FIG. 6 is a block diagram showing the basic function of the frequency shift circuit 32 by simplifying the equivalent circuit diagram of FIG.
As shown in FIG. 6, the frequency shift circuit 32 includes a multiplication circuit 32-1, a conversion circuit 32-2, and a phase summation circuit 32.
-3 and a DLTF generation circuit 32-4. The multiplication circuit 32-1 outputs the output T of the first bandpass filter 31.
F1 and the MPU 11 shown in FIG. 2 according to the mode setting signal.
Signal DLT generated by the DLTF generation circuit 32-4 based on the control signal input from the setting fetching unit 23 in
F is multiplied and the multiplication result is input to the conversion circuit 32-2. Here, as described above, the maximum transmission speed is 1200 bp.
s, sampling frequency is 7.2 kHz, frequency deviation ±
When Δf is ± 400 Hz, the signal DLTF is 0.34
It is 906585 radians.

In this embodiment, 200 bp and 300 bp
In the first, second, third and fourth modes corresponding to the maximum transmission rate of s, 600 bps and 1200 bps, the sampling frequencies are all 7.2 kHz, and the frequency deviation ± Δf is ± 100 Hz and ± 100 Hz, respectively. , ± 200
Hz and ± 400 Hz.

The conversion circuit 32-2 determines the phase shift amount θ based on the multiplication result from the multiplication circuit 32-1 as cos, si.
Convert to a vector of n. The conversion in this case can be performed by an operation based on the following series expansion formula.

[0029] ^{cosθ = 1-θ 2/2} ! + Θ ^4/4 ! ^{sinθ = θ-θ 3/3} ! + Θ ^5/5! The output vector of the conversion circuit 32-2 is the phase summation circuit 32.
-3 is input.

The phase summation circuit 32-3 is a conversion circuit 32-
Phase sum components DFRR and DFII are obtained by calculating the following trigonometric function formula based on the output vector of 2.

DFRR = cos (θ_n+ Θ_n-1) = C
osθ_ncos θ_n-1 -Sin θ_nsin θ_n-1 DFII = sin (θ_n+ Θ_n-1) = Sin θ_nsi
nθ_n-1 + Cos θ_ncos θ_n-1 Output phase summation DFRR, DFI of the phase summation circuit 32-3
I is input to the second bandpass filter 33, respectively.
It

The second bandpass filter 33 is provided for limiting the unnecessary band corresponding to each mode, that is, each maximum transmission rate. In order to perform frequency division multiplex transmission, the carrier frequency may differ in the same bandwidth. For example, in order to perform frequency division multiplex transmission at the maximum transmission rate of 200 bps, the frequency deviation ± Δf is ± 100.
Carrier frequency is 800 Hz / 1200 Hz / 1 in Hz
600Hz / 2000Hz / 2400Hz / 2800H
If z, it is necessary to set the characteristics of the second bandpass filter 33 so that there is no leakage into the adjacent band. Furthermore, since the code distortion has a bandwidth that satisfies the performance within 15%, the characteristic of the second bandpass filter 33 is 20 log ₁₀ 0.1 on the transmission data spectrum.
It is necessary to set the band up to 5 = -17 dB to be flat. In this way, the second bandpass filter 33 performs processing in the baseband before modulation with the carrier frequency, and thus can be used commonly for each carrier frequency.

FIG. 7 is an equivalent circuit diagram of the second bandpass filter 33. In the figure, "τ / n" is a delay corresponding to the sample time, "x" is multiplication, "Σ" and "+" are additions,
The addition "+" input to the RN indicates rounding by the coefficient RN. DFRR1 to DFRRN, DFII1 to DFI
IN is the real and imaginary components of the delay phase sum, respectively, C1 to C
N is a multiplication coefficient (however, different from the multiplication coefficient of FIG. 3),
TF2R and TF2I represent the real and imaginary components of the output of the second bandpass filter 33. For example, in the first mode in which the maximum transmission rate is 200 bps as described above, the number of taps N is 91. The multiplication coefficients C1 to CN are stored in the ROM 33 based on the control signal input from the setting capturing unit 23 in the MPU 11 shown in FIG. 2 according to the mode setting signal.
It is read from a. The multiplication coefficients C1 to CN may be directly input from the setting fetching unit 23 according to the mode setting signal.

As can be seen from FIG. 7, the second bandpass filter 33 is basically a finite length impulse response (FIR) filter represented by the following transfer function.

[0035]

[Equation 1] 8 to 11 show characteristics of the second band pass filter 33, which are 200 bps, 300 bps, 600 bps, respectively.
It is a figure shown about the 1st-4th mode corresponding to the maximum transmission rate of 1200 bps.

For example, in the case of the first mode, the multiplication coefficients C1 to CN of the second bandpass filter 33 may be determined so as to satisfy the following conditions and stored in the ROM 33a. (1) The frequency characteristic is flat up to a frequency variation of 100 Hz or more so that the characteristic becomes constant at the frequencies corresponding to the data A (0) and Z (1). (2) The band up to 20 log ₁₀ 0.15 = −17 dB is flat on the transmission data spectrum so that the code distortion is 15% or less. (3) Energy to adjacent channels is removed. (4) A sufficient signal-to-noise (S / N) ratio outside the band is secured. (5) Out-of-band folding is considered.

Therefore, the multiplication coefficient C of the second bandpass filter 33 is set so as to satisfy the above conditions (1) to (5).
The characteristics when 1 to CN are determined are as shown in FIG. 8 for the first mode, and the sampling frequency is 7.2 k.
Hz, baud rate is 267bauds, roll-off rate (ROF) is 50.00% cos ² characteristic, number of taps is 9
It becomes 1.

Similarly, the multiplication coefficient C of the second bandpass filter 33 is set so as to satisfy the above conditions (1) to (5).
The characteristics when 1 to CN are determined are as shown in FIG. 9 for the second mode, and the sampling frequency is 7.2 k.
Hz, baud rate 440bauds, ROF 50.
The characteristics are 00% cos ² and the number of taps is 63.

The multiplication coefficients C1 to CN of the second bandpass filter 33 are set so as to satisfy the above conditions (1) to (5).
The characteristics in the case of determining
0, the sampling frequency is 7.2 kHz,
Baud rate is 1200 bauds, ROF is 50.00
% Cos ² characteristic, the number of taps is 25.

The multiplication coefficients C1 to C1 of the second band pass filter 33 are set so as to satisfy the above conditions (1) to (5).
The characteristics when CN is determined are as shown in FIG. 11 for the fourth mode, and the sampling frequency is 7.2 kHz.
z, baud rate is 2400bauds, ROF is 50.
The characteristics are 00% cos ² and the number of taps is 11.

The baseband outputs TF2R and TF2I band-limited by the second bandpass filter 33 have a sampling frequency of 7.2 in the modulation circuit 35 shown in FIG.
The frequency is converted from kHz to 14.4 kHz and is modulated with each carrier frequency from the carrier input circuit 26. The frequency-modulated data output from the modulation circuit 35 is subjected to predetermined signal processing as necessary, and then the transmission medium (not shown).
Is output to. The predetermined signal processing in the transmission system is performed by, for example, well-known circuits such as frequency characteristic compensation, transmission level adjustment, loop test, digital / analog (D / A) conversion, etc., and sent to a line which is a transmission medium. The frequency characteristic compensating circuit is provided to compensate for the deterioration of the frequency characteristic due to the line, and the loop test circuit is provided to loop back the data on the receiving side to the transmitting side during the loop test.

Next, the receiving system of the modem device will be described.

The frequency-modulated data received from the line is input to the decimator 41 after being subjected to predetermined signal processing as necessary. The predetermined signal processing in the reception system is performed by a known circuit such as analog / digital (A / D) conversion, loop test, and frequency characteristic compensation. The loop test circuit is provided to loop back the data on the transmitting side to the receiving side during the loop test, and the frequency characteristic compensating circuit is provided to compensate for the deterioration of the frequency characteristic due to the line.

The decimator 41 changes the sampling frequency from 14.4 kHz to 7.
Convert to 2 kHz. Further, the demodulation circuit 42 frequency-demodulates the received frequency-modulated data using each carrier frequency from the carrier input circuit 43. That is, the passband signal (scalar signal) obtained from the decimator 41 is converted into a baseband signal (vector signal). Further, the roll-off filter 44 removes unnecessary out-of-band signals from the baseband signal. The output of the roll-off filter 44 is input to the difference circuit 45 and the carrier detection circuit 46.

FIG. 12 is a block diagram showing a schematic configuration of the difference circuit 45. The difference circuit 45 is an automatic gain control (AGC) circuit 45-1, a phase difference circuit 45-2, a conversion circuit 45-3, and a difference correction circuit 45 which are connected as shown in FIG.
-4 and a Z hold circuit 45-5.

The AGC circuit 45-1 is provided to normalize the signal into a signal on the unit (radius 1) circumference in order to calculate the phase difference for each vector signal. As a result, the outputs RFR and RFI of the roll-off filter 44 are
Is, for example, 0 dB ± 6.0 d by the AGC circuit 45-1.
The level-adjusted and normalized vector signals cos θ and sin θ are input to the phase difference circuit 45-2.

The phase difference circuit 45-2 calculates the phase difference by the following trigonometric function formula based on the normalized vector signals cos θ and sin θ.

Cos (Δθ) = cos (θ_n−
θ_n-1) = Cos θ_ncos θ_n-1 + Sin θ_ns
in θ_n-1 cos (Δθ) = sin (θ_n−θ_n-1) = Sin θ
_ncos θ_n-1 -Cos θ_nsin θ_n-1 For example, the fourth mode with the maximum transmission rate of 1200 bps
, The frequency deviation from the center carrier of data A is +
Deviation angle (phase) of 3.6 kHz sample interval at 400 Hz
Deviation amount) is + 40 °, and the frequency deviation of data Z is −
Deviation angle (phase) of 3.6 kHz sample interval at 400 Hz
The shift amount) is −40 °. Therefore, the phase difference in this case
The output phase difference from the divider circuit 45-2 is as shown in FIG.
become.

The conversion circuit 45-3 is a phase difference circuit 45-.
The vector-expressed phase difference obtained from 2 is converted into a phase angle (phase shift amount) θ. That is, since the error is large when the vector signals sin θ and cos θ are left as they are, the conversion circuit 45-3 converts the vector signal into the phase shift amount θ. For this conversion, the second-order term is taken from the Taylor expansion formula, and the phase shift amount θ is calculated from the following formula.

[0050] cosθ = 1-θ ^2/2 from ^{θ 2 = 2 (1-cosθ} ) sinθ = θ-θ 3/6 from θ = sinθ / (1-θ 2/6) = sinθ / {(2/3 ) + (Cos θ / 3)} The phase deviation amount θ output from the conversion circuit 45-3 is represented by deviation angle / sample = frequency deviation ± Δf / sampling frequency × 2π, which is the mode, that is, the maximum transmission. The value depends on the speed. That is, in the first mode with the maximum transmission rate of 200 bps and the second mode with the maximum transmission rate of 300 bps, the sampling frequency is 3.6 kHz,
The frequency deviation ± Δf is ± 100 Hz, and the phase deviation θ
Is 0.174532925 radians = 10 °. In the third mode in which the maximum transmission rate is 600 bps, the sampling frequency is 3.6 kHz, and the frequency deviation is ± Δf.
Is ± 200 Hz, and the phase shift amount θ is 0.34906.
585 radians = 20 °. Also, the maximum transmission speed is 1
In the fourth mode of 200 bps, the sampling frequency is 3.6 kHz and the frequency deviation ± Δf is ± 400 H.
z, and the phase shift amount θ is 0.698131700 radians = 40 °. Therefore, the difference correction circuit 45-4
In order to make a common determination for each mode in the determination circuit 48 in the subsequent stage, the phase shift amount θ of the first and second modes is multiplied by 4 and the phase shift amount θ of the third mode is doubled. By doing so, the phase shift amount θ in the first to third modes is
The phase shift amount θ in the mode is adjusted.

On the other hand, the carrier detection circuit 46 detects a carrier from the outputs RFR and RFI of the roll-off filter 44, and a carrier detection signal C indicating ON / OFF of the carrier.
DI is input to the Z hold circuit 45-5 in the difference circuit 45, and the detection carrier CD is output to the MPU 11 and the host device.

FIG. 14 is a block diagram showing the configurations of the ACG circuit 45-1 and the Z hold circuit 45-5. In the figure, the ACG circuit 45-1 is composed of a multiplication circuit 51, an absolute value circuit 52, a reciprocal calculation circuit 53, and a gain correction circuit 54 which are connected as shown. On the other hand, the Z hold circuit 45
-5 includes a multiplication circuit 61, a low pass filter (LPF) 62, a subtraction circuit 63, and a sign determination circuit 64 which are connected as shown in the figure.

Outputs RFR, R of roll-off filter 44
The FI is multiplied by the gain G by the multiplication circuit 51 in the ACG circuit 45-1, and the normalized vector signal cos θ,
sin θ is input to the phase difference circuit 45-2. Further, the absolute value circuit 52 and the reciprocal arithmetic circuit 53 calculate the reciprocal of the absolute values of the normalized vector signals cos θ and sin θ, and input them to the multiplication circuit 61 of the Z hold circuit 45-5. Further, the gain G is corrected by the gain correction circuit 54 based on the difference from the reference level, and the corrected gain G is input to the multiplication circuit 51 and also the multiplication circuit of the Z hold circuit 45-5. It is also input to 61.

When the carrier is off, the signal waveform is disturbed by a transient phenomenon, so that so-called dust data, which is a kind of noise, is generated. Therefore, in order to prevent the dust data from adversely affecting the external device such as the host device, it is desirable to hold the data at Z when the carrier is off (hereinafter, referred to as Z hold). Z hold circuit 45-5
Are provided to perform this Z-hold when the carrier is off.

Multiplier circuit 61 in Z-hold circuit 45-5
The output of is input to the input side of the LPF 62 on the one hand, and is input to the subtraction circuit 63 provided on the output side of the LPF 62 on the other hand. The subtraction circuit 63 subtracts the output of the multiplication circuit 61 from the output of the LPF 62 and inputs the subtraction result to the code determination circuit 64. The code determination circuit 64 includes
The carrier detection signal CDI from the carrier detection circuit 46 is also input.

When the carrier is on, the multiplication result of the gain G in the multiplication circuit 61 and the reciprocal is 1, and the LPF 62
The difference between the signals before and after passing through is 0. On the other hand, when the carrier is off, the signal level sharply decreases and the reciprocal becomes 1 or more. Therefore, when the carrier is off, the multiplication circuit 61
The result of multiplication of the gain G and the reciprocal is 1 or more.
The difference between the signals before and after passing through F62 is negative. Therefore, the sign determination circuit 64 outputs the hold signal HLD when the difference between the signals in the subtraction circuit 63 is negative, and the received data is Z
Hold on. In addition, even after the carrier was turned off Z
In order to hold, the code determination circuit 64 actually calculates the logical product of the carrier detection signal CDI from the carrier detection circuit 46 and the hold signal HLD, and then outputs the hold signal HLD. In this way, the Z hold circuit 4
The 5-5 can instantly perform Z-hold when the carrier is off.

Phase shift amount θ output from the difference circuit 45
The hold signal HLD is input to the determination circuit 48 via the interpolator 47 shown in FIG. The interpolator 47 sets the sampling frequency of the phase shift amount θ to 7.2 kHz in order to reduce the jitter amount of the received data.
To 28.8 kHz. The determination circuit 48 determines whether the received data is A or Z by determining the polarity of the scalar signal input via the interpolator 47, and the binary data 0 (A ), 1
(Z) is output to the MPU 11 and the host device.

The scalar signal input to the determination circuit 48 is ± 0.698131700 for A and Z, that is, "+" for A and "-" for Z. Further, the scalar signal changes from "+" to "-" when changing from A to Z and changes from "-" to "+" when changing from Z to A when A and Z change. Therefore, the determination circuit 48 determines the received data by detecting the change in A and Z.

FIG. 15 is a flow chart for explaining the operation of the decision circuit 48. In the figure, in step S1, the hold signal H is output from the Z hold circuit 45-5 of the difference circuit 45.
It is determined whether LD is input. If the decision result in the step S1 is YES, the process advances to a step S4 which will be described later, and Z hold is performed. On the other hand, if the decision result in the step S1 is NO, a step S2 decides whether or not the polarity of the scalar signal input is inverted. Step S2 is repeated until the determination result is YES, and when the determination result is YES, it is determined in step S3 whether or not the polarity of the scalar signal is inverted negatively.
If the decision result in the step S3 is YES, the process advances to a step S4, and if NO, the process advances to a step S5.

A step S4 judges that the received data is Z and outputs the data Z, and the process advances to a step S6. In step S5, the received data is determined to be A, data A is output, and the process proceeds to step S6. A step S6 starts a hysteresis timer, and a step S7 decides whether or not the hysteresis timer has timed out. Step S7 is repeated until the determination result becomes YES, and when the determination result becomes YES, the process returns to step S1.

Steps S6 and S7 are provided to prevent chattering in the determination of the received data when the polarity of the scalar signal is inverted, and the steps S4 and S5.
After the judgment result of the received data by is output, the judgment result is held for a constant holding time managed by the hysteresis timer. The holding time in this case may be about 25 ± 5% of the maximum transmission rate in each mode. For example, the holding time is set to 25, which is the maximum transmission speed in each mode.
%, That is, when the time is set to about 1/4 of 1 bit, the holding time is 1.25 ms in the first mode, 0.83 ms in the second mode, and 0.42 m in the third mode.
s, 0.21 ms in the fourth mode.

FIG. 16 is a time chart for explaining the operation of the determination circuit 48. In the figure, (a) is the determination result of the received data in steps S4 and S5,
(B) is the operating state of the hysteresis timer, (c) is the judgment output monitoring in steps S6 and S7, and (d) is the output signal finally output from the judgment circuit 48, that is, data 0 (A), 1 (Z) is shown.

In the demodulation circuit 42 provided in the preceding stage, A,
Since the demodulation is performed at the Z center frequency, the determination circuit 48
Can always determine the received data A, Z at the midpoint of the phase shift, and can obtain the received data with little code distortion.

The present invention has been described above with reference to the embodiments.
It is needless to say that the present invention is not limited to the above embodiments, and various improvements and modifications can be made within the scope of the present invention.

[0065]

According to the first aspect of the present invention, the frequency change of the baseband vector signal obtained from the demodulating means is obtained from the phase shift amount based on the phase difference. Since the amount is relatively small and the delay amount does not increase, the frequency-modulated data can be accurately demodulated.

According to the second aspect of the present invention, by obtaining the phase shift amount from the normalized baseband vector signal, an accurate phase shift amount can be obtained regardless of the data transmission rate.

According to the third aspect of the invention, the binary data value of the input data can be accurately determined with a simple circuit configuration.

According to the fourth aspect of the present invention, it is possible to prevent chattering when determining a binary data value.

According to the fifth aspect of the invention, by preventing so-called dust data from being output, it is possible to prevent malfunction of an external device or the like.

According to the sixth and seventh aspects of the invention, the binary data value of the input data can be accurately determined with a simple circuit configuration, and chattering at the time of determining the binary data value can be prevented. You can also

According to the invention described in claim 8, the amount of jitter of received data can be reduced.

According to the ninth aspect of the invention, since the frequency change of the baseband vector signal obtained in the demodulation step is obtained from the phase shift amount based on the phase difference, the signal processing amount of the receiving system is reduced. Since it is relatively small and the delay amount does not increase, the frequency-modulated data can be accurately demodulated.

Therefore, according to the present invention, since the frequency change of the baseband vector signal obtained by demodulation is obtained from the phase shift amount based on the phase difference, the signal processing amount of the receiving system is relatively small. Since the delay amount is small and the delay amount does not increase, the frequency-modulated data can be accurately demodulated.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment of a modem device according to the present invention.

FIG. 3 is an equivalent circuit diagram of a first bandpass filter.

FIG. 4 is a diagram showing a characteristic of a first bandpass filter.

FIG. 5 is an equivalent circuit diagram of a frequency shift circuit.

FIG. 6 is a block diagram showing the basic function of a frequency shift circuit by simplifying the equivalent circuit diagram of FIG.

FIG. 7 is an equivalent circuit diagram of a second bandpass filter.

FIG. 8 is a diagram showing characteristics of a second bandpass filter in the first mode.

FIG. 9 is a diagram showing characteristics of a second bandpass filter in a second mode.

FIG. 10 is a diagram showing characteristics of a second bandpass filter in a third mode.

FIG. 11 is a diagram showing characteristics of a second bandpass filter in a fourth mode.

FIG. 12 is a block diagram showing a schematic configuration of a difference circuit.

FIG. 13 is a diagram showing an output phase difference from the phase difference circuit.

FIG. 14 is a block diagram showing configurations of an ACG circuit and a Z hold circuit.

FIG. 15 is a flowchart illustrating the operation of the determination circuit.

FIG. 16 is a time chart illustrating the operation of the determination circuit.

[Explanation of symbols]

1 Frequency shift circuit 2 band pass filter 3 Modulation circuit 7 Demodulation circuit 8 Difference circuit 9 Judgment circuit 11 MPU 12 DSP 21 Signal point generation circuit 23 Settings Importer 31 First Band Pass Filter 32 frequency shift circuit 33 Second Bandpass Filter 34 Interpolator 35 Modulation circuit 36 Carrier input circuit 41 decimator 42 Demodulation circuit 43 Carrier input circuit 44 roll-off filter 45 Difference circuit 46 Carrier detection circuit 47 Interpolator 48 Judgment circuit

Claims (9)

[Claims] 1. A demodulation means for converting a passband scalar signal into a baseband vector signal by demodulating frequency-modulated data obtained by frequency-modulating input data at a carrier frequency intermediate between binary data values. A difference means for obtaining a phase shift amount from the phase difference of the baseband vector signal obtained from the demodulation means, and a binary data value of the input data is determined based on the phase shift amount obtained from the difference means. And a determining means for performing the processing. 2. The processor according to claim 1, wherein the difference means includes means for normalizing a baseband vector signal obtained from the demodulation means. 3. The processor according to claim 1, wherein the determining means includes first means for determining a binary data value of the input data based on the polarity of the phase shift amount. 4. The second determining means holds the determination result of a binary data value corresponding to the polarity for a certain holding time after the first means determines the polarity of the phase shift amount. The processor of claim 3, further comprising: 5. The method according to claim 1, further comprising means for holding the value of the binary data at a predetermined value when the carrier is off.
5. The processor according to any one of items 4 to 4. 6. The first differential circuit normalizes a baseband vector signal obtained from the demodulating unit, and the second differential circuit obtains a phase difference of the vector signal based on the normalized vector signal. And a third circuit for converting the phase difference of the vector signal into a phase shift amount.
The processor according to claim 1. 7. The processor according to claim 6, wherein the difference means further includes a fourth circuit that holds the value of the binary data at a predetermined value when the carrier is off. 8. An interpolator means for converting the sampling frequency of the phase shift amount obtained from the difference means and supplying the converted sampling frequency to the judging means is further provided.
The processor according to claim 1. 9. A demodulation step for converting a passband scalar signal into a baseband vector signal by demodulating frequency-modulated data obtained by frequency-modulating input data at a carrier frequency intermediate between binary data values. And a difference step of obtaining a phase shift amount from the phase difference of the baseband vector signal obtained in the demodulation step, and a binary data value of the input data is determined based on the phase shift amount obtained in the difference step. A frequency demodulation method, which comprises: