JP2003100910A - Semiconductor memory and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of preventing the deterioration of the characteristics of a capacity insulation film due to exposure of a metal upper electrode of, and to provide its manufacturing method. SOLUTION: In a DRAM memory cell being a semiconductor memory, a bit line 21a connected to a bit line plug 20b and a local wire 21b are arranged on a first inter-layer insulation film 18. A contact is not provided on a Pt film 35 which constitutes an upper electrode 35a, and a dummy lower electrode 33b makes direct contact with dummy barrier metal 32b. Namely, the upper electrode 35a is connected to an upper layer wire (Cu wire 42) through the dummy lower electrode 33b, a dummy cell plug 30, and the local wire 21b. Since the Pt film 35 is not exposed to a reductive atmosphere, the deterioration of the characteristics of a capacity insulation film 34a can be prevented from occurring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a memory cell structure using a high dielectric film or a ferroelectric film.

[0002]

2. Description of the Related Art In recent years, a DRAM mixed process in which a DRAM is mixedly mounted in a high-performance logic circuit has been put into practical use for multimedia equipment which requires a large memory capacity and a high data transfer rate.

However, since the conventional DRAM process requires a high-temperature heat treatment to form the capacitive insulating film of the capacitor serving as the storage capacitance portion, the impurity concentration profile of the impurity diffusion layer of the transistor in the high performance logic circuit is deteriorated. There is a problem such as making it. Also, DR
In the process of a single memory such as AM or FeRAM, it is preferable to avoid heat treatment at a temperature as high as possible in order to miniaturize the memory cell transistor.

Therefore, a MIM (Metal-Insulator-Me) using a high-dielectric film that can be formed at a low temperature and can be miniaturized in memory cell size is used as the capacitive dielectric film of the storage capacitor portion.
tal) Capacitor development is essential. The high dielectric film is a BST film ((BaSr) TiO ₃ film).
There is a dielectric film having a perovskite structure such as. On the other hand, Pt, which has a strong oxidation resistance, is generally regarded as a promising material for forming the metal electrode of the MIM capacitor. Further, as the ferroelectric film, the SBT film (SrBi
A dielectric film having a perovskite structure such as a ₂ Ta ₂ O ₉ film) or a BTO film (Bi ₄ Ti ₃ O ₁₂ film) is often used.

[0005]

However, the conventional MIM capacitor serving as the storage capacitor has the following problems.

First, P provided on the capacitance insulating film
When a contact hole is directly formed in the t electrode (upper electrode),
The reducing atmosphere or the like when forming the contact plug may adversely affect the characteristics of the capacitor. This is because, in general, the dielectric film is often an oxide, and oxygen deficiency in the dielectric film may occur due to the reducing atmosphere. In particular, when the capacitive insulating film is a high dielectric film or a ferroelectric film, oxygen deficiency is likely to occur. In particular,
In the dielectric film having the perovskite structure, the characteristic deterioration due to oxygen deficiency appears remarkably.

Further, in a device such as a DRAM which has not conventionally used a Pt electrode, P which is a new material.
In the process of forming a contact to the t-electrode, it is difficult to share it with existing equipment, and it is necessary to operate with dedicated equipment. When the Pt electrode is exposed, for example, when a contact hole reaching the Pt electrode is opened in the interlayer insulating film, Pt
Since Pt is sputtered, Pt is attached to the wall surface of the chamber and members inside the chamber. If this chamber is used as it is, P
This is because t may enter and adversely affect the transistor operation.

An object of the present invention is to provide a semiconductor memory device having a good MIM capacitor characteristic and a manufacturing method thereof by taking measures to suppress deterioration of the dielectric film and prevent mixing of electrode material into the transistor region. Especially.

Another object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same which can reduce the manufacturing cost by eliminating the need for dedicated equipment.

[0010]

A semiconductor memory device according to the present invention is provided on an insulating layer on a semiconductor substrate and includes a lower electrode,
A storage capacitor portion formed of a capacitance insulating film interposed between the upper electrode and the lower electrode and the upper electrode, and an upper electrode extension portion continuously provided to the upper electrode of the storage capacitor portion,
A dummy conductor member is provided below the upper electrode extension portion so as to be in contact with at least a part thereof, and an upper layer wiring electrically connected to the dummy conductor member.

As a result, the upper electrode is connected to the upper layer wiring through the upper electrode extension, the dummy lower electrode 33b, and the dummy conductor member, so that it is not necessary to form a contact hole above the upper electrode, and the upper electrode is The step of exposing to a reducing atmosphere is unnecessary. Therefore, there is no possibility that oxygen deficiency will occur in the capacitive insulating film made of, for example, BST,
It is possible to prevent the characteristic deterioration of the capacitive insulating film. In addition, for example, when the electrodes are formed of Pt, the lower electrode, the dummy conductor member, and the upper electrode are formed by dedicated equipment for forming the Pt film, so that the device for forming the logic circuit element may be contaminated. Disappear.

The dummy conductor member may include a conductor film filling the trench provided in the insulating layer.

The dummy conductor member is a plug for electrically connecting the local wiring provided on the semiconductor substrate under the insulating layer and the upper electrode extension portion and the local wiring through the insulating layer. May be further included.

A bit line is further formed below the storage capacitor portion with the insulating layer interposed therebetween, and the local wiring is
By being formed of the same conductor film as that of the bit line, a structure suitable for a bit line lower type memory can be obtained by using the conductor film for the bit line.

At least a part of the upper electrode extension portion in plan view overlaps with the conductor plug, so that the upper electrode and the upper layer wiring are reliably connected.

The element isolation insulating film provided on the semiconductor substrate below the insulating layer and the region of the semiconductor substrate surrounded by the element isolation insulating film are provided, and the gate electrode and the semiconductor substrate are provided with the above-mentioned elements. A memory cell transistor having an impurity diffusion layer provided on both sides of the gate electrode, and provided on the element isolation insulating film,
A conductor film for the gate electrode (such as a polysilicon film) by further including a local wiring formed of the same conductor film as the gate electrode and a conductor plug penetrating the insulating layer and connected to the local wiring. By utilizing, the structure applicable to both the bit line lower type memory and the bit line upper type memory can be obtained.

A memory cell transistor provided on the semiconductor substrate and having a gate electrode and an impurity diffusion layer provided on both sides of the gate electrode in the semiconductor substrate, and the impurity diffusion layer of the semiconductor substrate are separated from each other. Local wiring formed from another impurity diffusion layer provided in
By further including a conductor plug penetrating through the insulating layer and connected to the local wiring, the process for forming the source / drain regions is utilized, and the bit line lower type memory and the bit line upper type memory A structure that can be applied to both a stationary type memory can be obtained.

Since the upper layer wiring is in contact with the dummy lower electrode, the structure applicable to both the bit line lower type memory and the bit line upper type memory is obtained with a relatively simple structure. To be

Since the storage capacitor section has a cylindrical lower electrode, a capacitive insulating film and an upper electrode, a semiconductor memory device in which memory cells are arranged in a relatively high density can be obtained.

The capacitance insulating film is preferably a high dielectric film or a ferroelectric film.

According to a first method of manufacturing a semiconductor memory device of the present invention, there is provided a storage capacitor portion comprising a lower electrode, an upper electrode, and a capacitance insulating film interposed between the lower electrode and the upper electrode, and the storage capacitor portion. A method of manufacturing a semiconductor memory device, comprising the step of: (a) forming a local wiring on a semiconductor substrate;
After the step (a), a step (b) of forming a first conductor film on the semiconductor substrate, and a step (c) of patterning the first conductor film to form at least the lower electrode. A step (d) of forming a dielectric film to be the capacitance insulating film covering the lower electrode, and a step (e) of forming a second conductor film on the semiconductor substrate after the step (d). ) And the second conductor film are patterned to integrally form the electrode that covers the entire lower electrode and the upper electrode extension that covers at least a part of the local wiring and is continuous with the upper electrode. Step (f) and, after the step (f), forming the upper layer wiring electrically connected to the upper electrode on the semiconductor substrate through at least the local wiring and the upper electrode extension ( g) and are included.

According to this method, the upper electrode can be connected to the upper layer wiring through the local wiring or the upper electrode extension portion, so that it is necessary to provide a contact hole on the upper electrode in the manufacturing process as in the conventional method. It is possible to prevent the capacitance insulating film from being reduced.

After the step (a) and before the step (b), a step (a2) of forming a first insulating film on the semiconductor substrate including the local wiring, and the first insulating film. Further including a step (a3) of forming a first conductor plug and a second conductor plug that penetrate through the conductor and both are electrically connected to the local wiring. In the step (f), the upper electrode extension portion is formed. Is formed so as to cover at least a part of the first conductor plug, and in the step (g), the second insulating film is formed on the semiconductor substrate, and then the second insulating film is formed on the second insulating film.
The semiconductor memory device of the present invention can be realized by forming a wiring embedding trench that reaches the conductor plug, and burying a conductive film in the trench to form the upper layer wiring.

In the step (a), the local wiring is made of the same conductor film as the bit line and is formed at the same time as the bit line, so that the semiconductor memory device of the present invention can be manufactured in a small number of steps.

In the step (a), the local wiring is made of the same conductor film as the gate electrode of the memory transistor, and the semiconductor memory device of the present invention can be manufactured in a small number of steps by forming it simultaneously with the formation of the gate electrode. can do.

In the step (a), the local wiring is formed of the same impurity diffusion layer as the source / drain regions of the memory transistor, and is formed separately from the source / drain regions at the same time when the source / drain regions are formed. May be done.

In the step (a), the memory cell plug electrically connected to the source region of the memory cell transistor is formed on the first insulating film formed on the semiconductor substrate, and at the same time, the local region is formed. Even when forming wiring,
The number of manufacturing steps of the semiconductor memory device of the present invention can be reduced.

The step (c) includes a step of forming a dummy lower electrode made of the first conductive film, which is separated from the lower electrode and covers at least a part of the local wiring, and the local wiring and the lower wiring. By being electrically connected to the upper electrode extension through the dummy lower electrode, the semiconductor memory device of the present invention can be easily manufactured even when the dummy lower electrode is provided.

In the step (d), the dielectric film covering the lower electrode and the dummy lower electrode is formed, and in the step (e), the second conductor film covering the dielectric film is formed. , After the step (f) and before the step (g),
Forming a dielectric film for a capacitive insulating film by patterning the dielectric film using the same etching mask as that used for forming the upper electrode and the extended portion of the upper electrode; A step of forming at least the portion located between the dummy lower electrode and the upper electrode extension to form an inter-electrode space and at the same time forming the capacitive insulating film; The method further includes the step of deforming the electrode extension by heat treatment to bring the upper electrode extension and the dummy lower electrode into contact with each other, so that the heat treatment between the steps (f) and (g) results in an upper electrode and an upper layer. The wiring is electrically connected. Therefore, the upper electrode is not exposed to the reducing atmosphere during the manufacturing process, and deterioration of the capacitive insulating film can be prevented.

After the step (a) and before the step (b), both the step (a4) of forming a first insulating film on the semiconductor substrate including the local wiring and the first insulation are performed. A step (a5) of forming a first conductor plug and a second conductor plug which penetrate the film and are electrically connected to the local wiring;
A step (a6) of forming a step insulating film on the semiconductor substrate after the step (a5), and
Forming a first opening for forming the lower electrode of the storage capacitor portion and a second opening for forming a dummy lower electrode connected to the first conductor plug (a7) ) And in the step (c), the lower electrode is formed on the side surface and the bottom surface of the first opening, and the dummy lower electrode is formed on the side surface and the bottom surface of the second opening. And in the step (f), the upper electrode extension is formed so as to cover at least a part of the dummy lower electrode, and in the step (g), a second insulating film is formed on the semiconductor substrate. After the formation, by forming a wiring burying trench reaching the second conductor plug in the second insulating film and the step insulating film, burying a conductive film in the trench to form the upper layer wiring. ,
For example, the upper layer wiring provided by the damascene method and the upper electrode can be electrically connected.

It is preferable that the dielectric film is a high dielectric film or a ferroelectric film in order to realize a semiconductor memory device.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) In the present embodiment, the present invention is applied to a so-called bit line lower type DRAM in which a bit line is provided below a storage capacitor portion.
An example applied to the memory cell structure will be described.

1A and 1B are, respectively, a cross-sectional view showing a structure of a part of a memory portion in a semiconductor memory device according to the first embodiment of the present invention, and an upper electrode / dummy electrode. It is a top view which shows a structure. In addition, FIG.
6C is a sectional view showing a manufacturing process of the semiconductor memory device in the present embodiment. FIG. Hereinafter, the structure and manufacturing method of the semiconductor memory device according to the present embodiment will be described in order. Here, in each drawing of the present embodiment, only the structure of the memory portion is shown, but the semiconductor memory device of the present embodiment is a mixed-type device in which logic circuit elements are provided in a logic circuit portion (not shown). is there. However, since the structure itself of the logic circuit element is not directly related to the essence of the present invention, the illustration is omitted.

-Structure of Memory Cell-As shown in FIG.
In the memory cell of the DRAM which is the semiconductor memory device of the present embodiment, the element isolation insulating film 11 surrounding the active region and the source formed by introducing the n-type impurity on the upper surface of the p-type Si substrate 10. The region 12 and the drain region 13 are provided apart from each other. A portion of the p-type Si substrate 10 that is interposed between the source region 12 and the drain region 13 functions as a channel region. Also, S
On the active region of the i substrate 10, a gate insulating film 14 made of silicon oxide is provided between the source region 12 and the drain region 13, and a gate electrode 15 made of polysilicon (word) is formed on the gate insulating film 14. Part of the line) is provided, and an oxide film sidewall 16 is provided on the side surface of the gate electrode 15. A memory cell transistor TR is formed by the source region 12, the drain region 13, the channel region, the gate insulating film 14 and the gate electrode 15. Although the gate electrode 15 which does not function as the gate of the memory cell transistor TR is shown in the cross section shown in FIG. 1A, these are different from those of the memory cell transistor TR in the cross section different from FIG. It works as a gate. Then, each gate electrode 15 extends in a direction substantially orthogonal to the plane of the drawing to form a DRAM.
Has become a word line.

Further, a first interlayer insulating film 18 made of BPSG is provided on the Si substrate 10 so as to cover the element isolation insulating film 11, the gate electrode 15 and the oxide film side wall 16, and the first interlayer insulating film 18 is formed. A lower layer memory cell plug 20a made of W (tungsten) penetrating the film 18 and reaching the source region 12 and a bit line plug 20b penetrating the first interlayer insulating film 18 and reaching the drain region 13 are provided. There is. Further, on the first interlayer insulating film 18,
The bit line 21a made of a laminated film of W / Ti connected to the bit line plug 20b and the bit line 21a have the same W / Ti.
A local wiring 21b made of a laminated film of Ti is provided. In addition, for example, NSG is formed on the first interlayer insulating film 18.
Second interlayer insulating film 22 made of (non-doped SiO ₂ ).
Is provided. Then, an upper layer memory cell plug 30a penetrating the second interlayer insulating film 22 to reach the lower layer memory cell plug 20a, a dummy cell plug 30b penetrating the second interlayer insulating film 22 to reach the local wiring 21b, and a second A wiring plug 30c that penetrates the interlayer insulating film 22 and reaches the local wiring 21b is provided.

A lower barrier metal 32a made of TiAlN is further provided on the upper layer memory cell plug 30a, and a TiAlN is formed on the dummy cell plug 30b.
A dummy barrier metal 32b made of is provided.
Further, a lower electrode 33a made of Pt is formed on the lower barrier metal 32a, and a dummy lower electrode 33b is formed on the dummy barrier metal 32b. Further, of the lower electrode 33a and the second interlayer insulating film 22, a BST film ((BaSr) Ti) covering both sides of the lower electrode 33a is formed.
O ₃ film) 34, Pt film 35 covering the BST film 34 to the dummy barrier metal 32 b, and Ti covering the Pt film 35.
An upper barrier metal 36 made of AlN is provided.

The portion of the BST film 34 that contacts the lower electrode 33a is the capacitive insulating film 34a. The portion of the Pt film 35 that faces the lower electrode 33a is the upper electrode 35a, and the portion of the Pt film 35 that contacts the dummy lower electrode 33b is the upper electrode extension portion 35b. The lower barrier metal 32a and the lower electrode 33a constitute a storage node SN of the DRAM memory cell. Also,
Lower electrode 33a, capacitive insulating film 34a, and upper electrode 35a
The storage capacity section MC is configured by the above.

Further, a third interlayer insulating film 41 made of FSG is provided on the second interlayer insulating film 22 and the upper barrier metal 36, and the third interlayer insulating film 41 contacts the wiring plug 30c. The Cu wiring 42 is embedded. That is, the upper electrode 35a corresponds to the upper electrode extension 35.
It is electrically connected to the Cu wiring 42 through b and the dummy conductor member. Here, the dummy conductor member means a dummy barrier metal 32b, a dummy lower electrode 33b, a dummy cell plug 30b, and a local wiring 21b, which are conductors, respectively.
And the wiring plug 30c.

Further, in the structure shown in FIGS. 1A and 1B, the effective memory cell region R including the storage capacitor portion MC, the storage node SN, the memory cell transistor TR and the like.
ec, the dummy lower electrode 33b, the upper electrode extension 35b,
Dummy cell region Rdc including the dummy cell plug 30b
And will exist.

The feature of this embodiment is that the plug contacting the upper electrode 35a or the upper electrode extension 35b (upper barrier metal 36) is not provided, and the dummy lower electrode 33 is provided.
b, dummy barrier metal 32b, dummy cell plug 30
This is that the upper electrode 35a is connected to the upper wiring (Cu wiring 42) by b and the local wiring 21b.

Then, as shown in FIG. 1B, the Pt film 35 (upper barrier metal 3) forming the upper electrode 35a is formed.
6) is shared by many memory cells, and P
Below the t film 35, a large number of lower electrodes 33a (lower barrier metal 32a) and dummy lower electrodes 33b (dummy barrier metal 32b) are provided. The dummy lower electrode 33b (dummy barrier metal 32b) is formed of the Pt film 35.
Although a plurality of Pt films 35 are provided below the Pt film 35, if at least one is provided below any part of the end of the Pt film 35, the upper electrode 35a and the dummy lower electrode 33b are electrically connected.

According to this embodiment, since there is no plug contacting the Pt film 35 (upper barrier metal 36) forming the upper electrode, a contact hole for burying the plug is formed in the third interlayer insulating film 41. You don't have to. Therefore, unlike the conventional structure, the Pt film forming the upper electrode is not exposed in the dry etching (plasma etching) process for forming the contact hole in the upper electrode. That is, if the Pt film is exposed to a reducing atmosphere while exposed, oxygen deficiency may occur in the capacitive insulating film (especially high dielectric film) made of BST or the like. Here, as in the present embodiment, TiA is formed on the Pt film.
Even if the upper barrier metal made of 1N is provided, the upper barrier metal is thin, and the contact hole is likely to reach the upper electrode made of Pt because the contact hole is usually over-etched. In consideration of the above, the upper barrier metal cannot be expected to have a function of preventing oxygen vacancies in the capacitor insulating film. On the other hand, in the present embodiment, since the contact hole is not formed above the Pt film 35, it is possible to reliably avoid the oxygen deficiency of the capacitive insulating film 34a due to the Pt film being exposed to the reducing atmosphere. .

Further, since the Pt film 35 is not exposed in the step of opening the contact hole in the third interlayer insulating film 41, the etching for forming the contact hole, the process for forming the logic circuit element, etc. Can be performed in the same device (chamber, etc.) The formation of the lower electrode 33a made of Pt, the dummy lower electrode 33b, and the upper electrode 35a itself is performed by dedicated equipment for forming the Pt film, so that there is a possibility that the device for forming the logic circuit element is contaminated. Does not occur in

-Manufacturing Method of Memory Cell- Next, the manufacturing process of the memory cell of the semiconductor memory device according to the present embodiment will be described with reference to FIGS.

The following processing is performed in the step shown in FIG. First, the element isolation insulating film 11 surrounding the active region is formed on the p-type Si substrate 10, and the source region 12 and the drain region 13, the gate insulating film 14, the gate electrode 15, and the oxide film are formed in the active region. A memory cell transistor including the sidewall 16 is formed. This memory cell transistor formation process is performed by a well-known procedure using well-known techniques such as thermal oxidation, formation and patterning of a polysilicon film, and ion implantation.

Next, on the memory cell transistor, B
After depositing the PSG film, annealing and planarization by CMP (chemical mechanical polishing) are performed to form the first interlayer insulating film 18. Further, contact holes penetrating the first interlayer insulating film 18 to reach the source region 12 and the drain region 13 are formed. Next, after forming an n-type polysilicon film in the contact hole and on the first interlayer insulating film 18,
By planarizing by CMP, the polysilicon film is buried in each contact hole to form the lower layer memory cell plug 20a and the bit line plug 20b.

Next, W / Ti is formed on the first interlayer insulating film 18.
After the laminated film is deposited, the W / Ti laminated film is patterned by etching to form the bit line 21a connected to the bit line plug 20b and the local wiring 21b which is not connected to other members at this stage and is isolated. To form. At this time, when patterning the W film, the time when the surface of the Ti film is exposed is detected to determine the end time of the etching of the W film.
At the time of patterning the i film, etching is performed under the condition that a high selection ratio is obtained for the first memory cell plug 20a made of polysilicon.

Next, after depositing an NSG (non-doped silicate glass) film on the substrate, planarization is performed by CMP (chemical mechanical polishing) to form a second interlayer insulating film 22. Further, contact holes penetrating the second interlayer insulating film 22 to reach the lower layer memory cell plug 20a and the local wiring 21b (two places) are formed. Next, after forming a W film in the contact holes, the W film is embedded in each contact hole by performing planarization by CMP, and the upper layer memory cell plugs 30a connected to the lower layer memory cell plugs 20a and 2 The dummy cell plug 30b and the wiring plug 3 which respectively come into contact with the local wiring 21b at some points.
And 0c.

Next, a TiAlN film having a thickness of about 30 nm and a Pt having a thickness of about 50 nm are formed on the second interlayer insulating film 22.
And a film are sequentially deposited. Then, by patterning the TiAlN film and the Pt film, a lower barrier metal 32a connected to the memory cell plug 30a on the second interlayer insulating film 22 and a lower electrode 33a made of Pt on the lower barrier metal 32a.
And a dummy barrier metal 32b connected to the dummy cell plug 30b and a dummy lower electrode 33b thereon are formed. Here, when the Pt film is patterned, etching is performed under the condition that a high selection is obtained with respect to the underlying TiAlN film, and when the TiAlN film is patterned, the upper layer memory cell plug 3 made of W that is the underlying layer.
Etching is performed under conditions with a high selection ratio so that 0a is not dug down.

Next, in the step shown in FIG. 2B, the second interlayer insulating film 22, the lower electrode 33a and the dummy lower electrode 33b are formed.
BST film ((BaSr) Ti) with a thickness of about 30 nm
After the formation of the O ₃ film), the BST film is patterned so as to expose the dummy lower electrode 33b, and the BST film 34 which will be the capacitance insulating film 34a covering the lower electrode 33a is formed.

Then, a Pt film having a thickness of about 50 nm and a thickness of about 6 are formed on the BST film 34 and the dummy lower electrode 33b.
nm TiAlN film and SiO ₂ film are sequentially deposited.
Then, the hard mask 3 is formed by patterning the SiO ₂ film.
After forming 7, the TiAlN film and the Pt film are sequentially patterned by dry etching using the hard mask 37 to form the upper barrier metal 36 covering the effective memory cell region Rec and the dummy cell region Rdc, the upper electrode 35a and the upper portion. The Pt film 35 including the electrode extension 35b is formed.

Next, in the step shown in FIG. 2C, after the hard mask 37 is removed by wet etching with a dilute hydrofluoric acid solution, a TEOS film is deposited on the substrate and planarized by CMP. The interlayer insulating film 41 of No. 3 is formed. Next, a trench reaching the wiring plug 30c is formed in the third interlayer insulating film 41, and then the Cu wiring 42 is embedded in the trench (damascene method) or the like, whereby the memory cell shown in FIG. The cross-sectional structure of

According to the manufacturing method of the present embodiment, the Pt film 35 is penetrated through the third interlayer insulating film 41 without increasing the photolithography process in the conventional process.
It is possible to avoid the step of forming a contact hole reaching the upper barrier metal 36. That is, in the case of forming a wiring burying trench in the third interlayer insulating film 41, generally, annealing in a reducing atmosphere is often used in the Cu wiring forming step. Therefore,
When the contact hole is formed on the upper barrier metal 36, hydrogen directly contacts the Pt film 35 through the thin upper barrier metal 36 or when the Pt film 35 is exposed by overetching. Is Pt film 3
5 may reach the BST film 34. In that case, the oxygen in the BST film 34 may be lost to cause oxygen deficiency, which may lead to deterioration of the characteristics of the capacitive insulating film 34a. On the other hand, by avoiding the step of forming the contact hole reaching the Pt film 35 as in the present embodiment, it is possible to reliably suppress the deterioration of the characteristics of the capacitance insulating film 34a due to such a cause. And the Cu wiring 4
The step of forming 2 corresponds to the step of forming the plug on the conventional upper electrode, and the formation of the local wiring 21b and the wiring plug 30c can be performed by using the step of forming the memory cell. The number of photolithography steps is not increased as compared with the process of directly providing the plug on the Pt film (upper barrier metal).

In the present embodiment, the upper electrode 3
Although 5a and the lower electrode 33a are made of Pt and the upper barrier metal 36 is made of TiAlN, these members may be made of another conductive material having oxidation resistance. Although the capacitor insulating film 34a is made of BST, it may be made of other high dielectric material. In particular, in the case of a dielectric film having a perovskite structure whose structural formula is represented by ABO ₃ , oxygen atoms are likely to be lost by reduction. Therefore, the present invention is applied to obtain a great effect.

Further, the present invention is not limited to the mixed device as in the present embodiment, but may be a general-purpose DRAM or FeRA.
It goes without saying that the present invention can also be applied to a semiconductor memory device having a capacitor using a metal electrode such as M.

(Second Embodiment) FIG. 3 is a sectional view showing a method of manufacturing a semiconductor memory device according to the second embodiment. The method of this embodiment is another method for manufacturing the semiconductor memory device of the first embodiment shown in FIG.

In the step shown in FIG. 3A, the steps similar to those of the first embodiment are performed until the lower electrode 33a and the dummy lower electrode 33b are formed.

Next, in the step shown in FIG. 3B, the second interlayer insulating film 22, the lower electrode 33a and the dummy lower electrode 33b are formed.
BST film ((BaSr) Ti) with a thickness of about 30 nm
O ₃ film), a Pt film with a thickness of about 50 nm, and a thickness of about 6
nm TiAlN film and SiO ₂ film are sequentially deposited.
Then, the hard mask 3 is formed by patterning the SiO ₂ film.
After forming 7, the TiAlN film, the Pt film, and the BST film are sequentially patterned by dry etching using the hard mask 37, and the upper barrier metal 36 that covers the effective memory cell region Rec and the dummy cell region Rdc, Pt film 3 including upper electrode 35a and upper electrode extension 35b
5 and the BST film 34 are formed respectively.

Next, in the step shown in FIG. 3C, the hard mask 37 is removed by wet etching with a diluted hydrofluoric acid solution. At this time, since BST is also dissolved by the dilute hydrofluoric acid solution, the portion of the BST film 34 above the dummy barrier metal 32b is also removed. As a result, the inter-electrode space 8
To form.

Subsequently, in the step shown in FIG. 3D, the upper electrode extension 35b located above the inter-electrode space 8 is deformed by heat-treating the substrate in an oxygen atmosphere at 500 ° C. for 1 minute, for example. Then, the dummy lower electrode 33b and the upper electrode extension 35b are brought into contact with each other. Platinum has a high fluidity when heated and can be easily deformed. At this time, pressure may be applied to the substrate to ensure the contact between the dummy lower electrode 33b and the upper electrode extension 35b.

Thereafter, although not shown, a fourth interlayer insulating film 41 and a Cu wiring 42 are formed as in the first embodiment.

According to the manufacturing method of the present embodiment, the photolithography process for patterning the BST film 34 is not necessary and the BST film is etched simultaneously with the removal of the hard mask 37. Thus, the number of manufacturing steps can be reduced, and the manufacturing can be easily performed. Further, by not forming the plug on the upper electrode, the BST film 34 serving as the capacitance insulating film 34a is not exposed to the reducing atmosphere as in the first embodiment, and the deterioration of the film quality of the BST film 34 is prevented. be able to.

In the present embodiment, the upper electrode 3
Although 5a and the lower electrode 33a are made of Pt and the upper barrier metal 36 is made of TiAlN, these members may be made of another conductive material having oxidation resistance. Although the capacitor insulating film 34a is made of BST, it may be made of other high dielectric material. In particular, in the case of a dielectric film having a perovskite structure whose structural formula is represented by ABO ₃ , oxygen atoms are likely to be lost by reduction, so that applying the present invention provides a great effect.

Further, the present invention is not limited to the mixed device as in the present embodiment, but may be a general-purpose DRAM or FeRA.
It goes without saying that the present invention can also be applied to a semiconductor memory device having a capacitor using a metal electrode such as M.

(Third Embodiment) As a third embodiment of the present invention, a semiconductor memory device in which the dummy lower electrode 33b and the dummy barrier metal 32b are not formed in the semiconductor memory device of the first embodiment will be described. .

FIG. 4 is a sectional view showing the semiconductor memory device of this embodiment. The same members as those in FIG. 1 are designated by the same reference numerals.

As shown in FIG. 4, the semiconductor memory device of this embodiment includes a Si substrate 10, a source region 12, a drain region 13, a channel region, and a source region 12 provided on the Si substrate 10.
The memory cell transistor TR having the gate insulating film 14 and the gate electrode 15 and the dielectric capacitor connected to the source region 12 of the memory cell transistor TR by the upper layer memory cell plug 30a are provided. This dielectric capacitor includes a lower barrier metal 32a provided on the upper layer memory cell plug 30a and a lower barrier metal 3a.
Lower electrode 33a and BST film 3 which are sequentially provided on 2a.
4, the Pt film 35 and the upper barrier metal 36. A portion of the Pt film 35 facing the lower electrode 33a is defined as an upper electrode 35a, and a portion of the BST film 34 lower electrode 33a
A portion between a and the upper electrode 35a is used as a capacitance insulating film 34a.

Further, the Pt film 35 and the upper barrier metal 3
Reference numeral 6 extends to the side of the lower electrode 33a, and the portion extending above the second interlayer insulating film 22 is used as an upper electrode extension 35b. First provided on the memory cell transistor TR
The local wiring 21b is provided on the interlayer insulating film 18, and the third interlayer insulating film 41 provided on the second interlayer insulating film 22.
And a Cu wiring 42 is provided. The upper electrode extension 35b and the local wiring 21b are connected to each other by the dummy cell plug 30b, and the local wiring 21b and the local wiring 21b are connected to each other.
The u wiring 42 is connected to each other by a wiring plug 30c. That is, the upper electrode 35a is electrically connected to the Cu wiring 42 via the upper electrode extension 35b and the dummy conductor member. Here, the dummy conductor member means the dummy cell plug 30b, the local wiring 21b, and the wiring plug 30c, which are each made of a conductor.

Even if the dummy lower electrode and the dummy barrier metal are not provided as in the semiconductor memory device of the present embodiment, the plug contacting the Pt film 35 can be eliminated, so that the upper electrode 35a and the Cu wiring 42 are formed. It is possible to reliably avoid the oxygen deficiency of the capacitive insulating film 34a due to the exposure of the Pt film to the reducing atmosphere while ensuring the connection.

Further, since the Pt film 35 is not exposed in the step of opening the contact hole in the third interlayer insulating film 41, the etching for forming the contact hole, the process for forming the logic circuit element, etc. Can be performed in the same device (chamber, etc.) The formation of the lower electrode 33a made of Pt and the upper electrode 35a itself is
Since the dedicated equipment for forming the Pt film is used, the possibility of contaminating the device for forming the logic circuit element does not inherently occur in the semiconductor memory device of this embodiment.

Next, the manufacturing process of the memory cell of the semiconductor memory device in this embodiment will be described.

5A to 5C are sectional views showing a method of manufacturing the semiconductor memory device of this embodiment.

The following processing is performed in the step shown in FIG. First, the element isolation insulating film 11 surrounding the active region is formed on the p-type Si substrate 10, and the source region 12 and the drain region 13, the gate insulating film 14, the gate electrode 15, and the oxide film are formed in the active region. A memory cell transistor including the sidewall 16 is formed. This memory cell transistor formation process is performed by a well-known procedure using well-known techniques such as thermal oxidation, formation and patterning of a polysilicon film, and ion implantation.

Next, B on the memory cell transistor
After depositing the PSG film, annealing and planarization by CMP (chemical mechanical polishing) are performed to form the first interlayer insulating film 18. Further, contact holes penetrating the first interlayer insulating film 18 to reach the source region 12 and the drain region 13 are formed. Next, after forming an n-type polysilicon film in the contact hole and on the first interlayer insulating film 18,
By planarizing by CMP, the polysilicon film is buried in each contact hole to form the lower layer memory cell plug 20a and the bit line plug 20b.

Next, W / Ti is formed on the first interlayer insulating film 18.
After the laminated film is deposited, the W / Ti laminated film is patterned by etching to form the bit line 21a connected to the bit line plug 20b and the local wiring 21b. At that time, when patterning the W film, the time when the surface of the Ti film is exposed is detected to determine the etching end time of the W film,
At the time of patterning the Ti film, etching is performed under the condition that a high selection ratio is obtained for the first memory cell plug 20a made of polysilicon.

Next, after depositing the NSG film on the substrate,
Secondly after planarization by CMP (Chemical Mechanical Polishing)
The interlayer insulating film 22 is formed. Further, the second interlayer insulating film 2
Contact holes penetrating 2 to reach the lower layer memory cell plug 20a and the local wiring 21b (two places) are formed. Next, after forming a W film in the contact hole,
By flattening by CMP, the W film is embedded in each contact hole, and the upper layer memory cell plug 30a connected to the lower layer memory cell plug 20a and the dummy cell plugs 30 contacting the local wiring 21b at two locations respectively.
b and the wiring plug 30c are formed.

Next, a TiAlN film having a thickness of about 30 nm and a Pt having a thickness of about 50 nm are formed on the second interlayer insulating film 22.
And a film are sequentially deposited. Then, by patterning the TiAlN film and the Pt film, the lower barrier metal 32a connected to the memory cell plug 30a and the lower electrode 33a made of Pt thereon are formed on the second interlayer insulating film 22. Here, when patterning the Pt film,
Etching is performed under the condition that a high selection is obtained with respect to the underlying TiAlN film, and when patterning the TiAlN film, etching is performed under a high selection ratio condition so that the upper layer memory cell plug 30a made of W that is the underlying is not dug down. Do.

Next, in the step shown in FIG. 5B, the thickness covering the second interlayer insulating film 22 and the lower electrode 33a is about 30 nm.
After forming the BST film ((BaSr) TiO ₃ film) of
The BST film is patterned so that the interlayer insulating film 22 is exposed, and the BST film 34 which will be the capacitance insulating film 34a covering the lower electrode 33a is formed.

Next, the BST film 34 and the second interlayer insulating film 2
2 and the dummy cell plug 30b has a thickness of about 50 nm.
Pt film, a TiAlN film with a thickness of about 6 nm, and SiO
_Two films are sequentially deposited. Then, after patterning the SiO ₂ film to form the hard mask 37, the TiAlN film and the Pt film are sequentially patterned by dry etching using the hard mask 37 to cover the effective memory cell region Rec and the dummy cell region Rdc. Upper barrier metal 3
6 and the Pt film 35 including the upper electrode 35a and the upper electrode extension 35b are formed.

Next, in the step shown in FIG. 5C, after the hard mask 37 is removed by wet etching with a dilute hydrofluoric acid solution, a TEOS film is deposited on the substrate and planarized by CMP. The interlayer insulating film 41 of No. 3 is formed. Next, a trench is formed on the third interlayer insulating film 41, and then the Cu wiring 42 is embedded in the trench (damascene method), so that the semiconductor memory device of this embodiment is obtained. In the step shown in FIG. 5B, the upper electrode extension 35a and the upper barrier metal 36 do not have to completely overlap the dummy cell plug 30b, and a part thereof is formed so as to overlap the dummy cell plug 30b. It should have been done.

In this embodiment, the semiconductor memory device according to the first embodiment is the dummy barrier metal 32b.
Although the case where the dummy lower electrode 33b is not provided has been described, the dummy barrier metal 32b and the dummy lower electrode 33b are also applied to the semiconductor memory device according to the following embodiments.
There is no problem even if it does not form.

(Fourth Embodiment) FIG. 6 shows a fourth embodiment of the present invention.
3 is a cross-sectional view showing the structure of a part of the memory portion of the semiconductor memory device in the embodiment of FIG.

As shown in the figure, the structure of the memory portion of this embodiment is different from that of the first embodiment in that the local wiring 21b made of the W / Ti film, the dummy cell plug 30b and the dummy in the first embodiment are different. This is that the lower electrode 33b is not provided and the local wiring 23 made of W filling the trench formed in the second interlayer insulating film 22 is provided. The local wiring 23 is connected to the upper layer memory cell plug 30a.
Formed at the same time. Other members are shown in FIG.
It is the same as the member shown in FIG.
The same reference numerals as in (a) are attached.

According to this embodiment, the local wiring 23 made of W, the dummy barrier metal 32b, and the dummy lower electrode 3 are formed.
The upper electrode 35a and the Cu wiring 42 are electrically connected via 3b. Also in this embodiment, the Pt film 35 forming the upper electrode 35a is formed on the third interlayer insulating film 41.
It is not necessary to form a contact hole reaching (upper barrier metal 36). Therefore, according to the present embodiment, similar to the first embodiment, it is possible to achieve the effects of preventing the deterioration of the characteristics of the capacitive insulating film 34a and eliminating the need for dedicated equipment for forming memory cells.

(Fifth Embodiment) FIG. 7 is a sectional view showing the structure of a part of a memory portion of a semiconductor memory device according to the fifth embodiment.

As shown in the figure, the structure of the memory portion of this embodiment is different from that of the first embodiment in that instead of the local wiring 21b made of the W / Ti film in the first embodiment, element isolation is performed. A local wiring 24 made of polysilicon is provided on the insulating film 11 for insulation, and further, the first interlayer insulating film 18 is formed.
The lower layer dummy cell plug 20c that penetrates through the first interlayer insulating film 18 and the local wiring 2
That is, the lower layer wiring plug 20d that comes into contact with the wiring 4 is provided. In the present embodiment, the dummy cell plug 30b is connected to the lower layer dummy cell plug 20c, and the wiring plug 30c is connected to the lower layer wiring plug 20d. The local wiring 24 is formed at the same time as the gate electrode 15. Other members are the same as the members shown in FIG. 1A, and those members are denoted by the same reference numerals as those in FIG. 1A.

According to the present embodiment, the dummy lower electrode 33
b, dummy barrier metal 32b, dummy cell plug 30
b, the lower layer dummy cell plug 20c, the local wiring 24, the lower layer wiring plug 20d, and the wiring plug 30c, the upper electrode 35a and the Cu wiring 42 are electrically connected. Also in the present embodiment, the third interlayer insulating film 41 is
It is not necessary to form a contact hole reaching the Pt film 35 (upper barrier metal 36) forming the upper electrode 35a. Therefore, according to the present embodiment, similar to the first embodiment, it is possible to achieve the effects of preventing the deterioration of the characteristics of the capacitive insulating film 34a and eliminating the need for dedicated equipment for forming memory cells.

(Sixth Embodiment) FIG. 8 is a sectional view showing the structure of a part of a memory portion of a semiconductor memory device according to the sixth embodiment.

As shown in the figure, the structure of the memory portion of this embodiment is different from that of the first embodiment in that instead of the local wiring 21b made of the W / Ti film in the first embodiment, the Si substrate is used. Local wiring 2 consisting of an impurity diffusion layer in 10
5, the lower dummy cell plug 20c penetrating the first interlayer insulating film 18 and contacting the local wiring 25.
And a lower layer wiring plug 20d which penetrates the first interlayer insulating film 18 and contacts the local wiring 25. In the present embodiment, the dummy cell plug 30b is connected to the lower layer dummy cell plug 20c and the wiring plug 3
0c are respectively connected to the lower layer wiring plugs 20d. The local wiring 25 includes the source / drain regions 12, 13
Formed at the same time. Other members are shown in FIG.
It is the same as the member shown in FIG.
The same reference numerals as in (a) are attached.

According to the present embodiment, the dummy lower electrode 33
b, dummy barrier metal 32b, dummy cell plug 30
The upper electrode 35a and the Cu wiring 42 are electrically connected to each other through the b, the lower layer dummy cell plug 20c, the local wiring 25, the lower layer wiring plug 20d, and the wiring plug 30c. Also in the present embodiment, the third interlayer insulating film 41 is
It is not necessary to form a contact hole reaching the Pt film 35 (upper barrier metal 36) forming the upper electrode 35a. Therefore, according to the present embodiment, similar to the first embodiment, it is possible to achieve the effects of preventing the deterioration of the characteristics of the capacitive insulating film 34a and eliminating the need for dedicated equipment for forming memory cells.

(Seventh Embodiment) In the first to sixth embodiments, the present invention is a bit line lower type DRAM.
The example applied to the memory cell structure has been described. However, in the present embodiment, an example applied to the bit line top type DRAM memory cell structure in which the bit line is provided above the storage capacitor portion will be described. To do. FIG. 9 is a sectional view showing the structure of a part of the memory portion of the semiconductor memory device according to the seventh embodiment. 10 (a) to (c)
FIG. 13A is a sectional view showing a manufacturing process of the semiconductor memory device according to the seventh embodiment. Hereinafter, the structure and manufacturing method of the semiconductor memory device according to the present embodiment will be described in order.
Here, in each of the drawings of the present embodiment, only the structure of the memory section is shown, but the semiconductor memory device of the present embodiment is similar to the first embodiment in that a logic circuit element in a logic circuit section not shown is shown. Embedded device. However, since the structure itself of the logic circuit element is not directly related to the essence of the present invention, the illustration is omitted.

As shown in FIG. 9, the memory portion of the present embodiment is similar to the fifth embodiment in that instead of the local wiring 21b made of the W / Ti film in the first embodiment, isolation for element isolation is used. Local wiring 2 made of polysilicon on the film 11
4 is provided, and further, the lower layer dummy cell plug 20c penetrating the first interlayer insulating film 18 and contacting the local wiring 24.
And a lower layer wiring plug 20d penetrating the first interlayer insulating film 18 and contacting the local wiring 24.

Further, in the present embodiment, the storage capacitor portion MC and the dummy cell are provided on the first interlayer insulating film 18, and the dummy lower electrode 33b (dummy barrier metal 3) is formed.
2b) is directly connected to the lower layer dummy cell plug 20c, and the Cu wiring 42 is directly connected to the lower layer wiring plug 20d. The local wiring 24 is formed of the same polysilicon film as the gate electrode 15.

Furthermore, on the bit line plug 20b,
An upper layer bit line plug 51 that penetrates the second interlayer insulating film 22 and reaches the bit line plug 20b, an insulator film 52 that covers a side surface of the upper layer bit line plug 51, and a third interlayer insulating film 4
1 and a bit line 53 formed of a Cu film. That is, it has a structure of the bit line top type DRAM memory cell in which the bit line is provided above the storage capacitor portion MC.

Other members in FIG. 9 are the same as those in FIG.
1 (a) are the same as those shown in FIG.
The same reference numeral is attached.

According to the present embodiment, the dummy lower electrode 33
b, dummy barrier metal 32b, dummy cell plug 30
The upper electrode 35a and the Cu wiring 42 are electrically connected to each other through the b, the lower dummy cell plug 20c, the local wiring 24, and the lower wiring plug 20d. Also in this embodiment, it is not necessary to form a contact hole reaching the Pt film 35 (upper barrier metal 36) forming the upper electrode 35a in the third interlayer insulating film 41. Therefore, according to the present embodiment, while adopting the structure of the bit line placed type, the deterioration of the characteristics of the capacitance insulating film 34a is prevented as in the first embodiment, and the dedicated equipment for forming the memory cell is unnecessary. It can be effective.

Next, the manufacturing process of the memory cell of the semiconductor memory device in this embodiment will be described with reference to FIGS.
This will be described with reference to (c).

In the step shown in FIG. 10A, the following processing is performed. First, an element isolation insulating film 11 surrounding an active region is formed on a p-type Si substrate 10, and a source region 12 and a drain region 13 and a gate insulating film 14 are formed in the active region.
A memory cell transistor including the gate electrode 15 and the oxide film sidewall 16 is formed. This memory cell transistor formation process is performed by a well-known procedure using well-known techniques such as thermal oxidation, formation and patterning of a polysilicon film, and ion implantation. At this time, when forming the gate electrode 15, the local wiring 24 made of polysilicon is simultaneously formed on the element isolation insulating film 11.

Next, B on the memory cell transistor
After depositing the PSG film, annealing and planarization by CMP (chemical mechanical polishing) are performed to form the first interlayer insulating film 18. Further, contact holes penetrating the first interlayer insulating film 18 to reach the source region 12, the drain region 13 and the local wiring 24 are formed. next,
After forming an n-type polysilicon film in the contact hole and on the first interlayer insulating film 18, the polysilicon film is buried in each contact hole by performing planarization by CMP to form the lower layer memory cell plug 20a, A bit line plug 20b, a lower layer dummy cell plug 20c, and a lower layer wiring plug 20d are formed.

Next, a TiAlN film having a thickness of about 30 nm and a Pt having a thickness of about 50 nm are formed on the first interlayer insulating film 18.
And a film are sequentially deposited. By patterning the TiAlN film and the Pt film, a barrier metal 32a connected to the lower memory cell plug 20a on the first interlayer insulating film 18 and a lower electrode 33a made of Pt on the barrier metal 32a.
And the dummy barrier metal 32b connected to the lower layer dummy cell plug 20b and the dummy lower electrode 33b thereon are formed. Here, when patterning the Pt film, etching is performed under the condition that a high selection is obtained with respect to the underlying TiAlN film, and when patterning the TiAlN film, the upper layer memory cell plug 30a made of W that is the underlying layer is not dug down. As described above, etching is performed under the condition of high selectivity.

Next, the first interlayer insulating film 18 and the lower electrode 33.
After forming a BST film ((BaSr) TiO ₃ film) having a thickness of about 30 nm covering the a and the dummy lower electrode 33b, the BST film is patterned to expose the dummy lower electrode 33b, and the capacitive insulating film covering the lower electrode 33a is formed. A BST film 34 to be 34a is formed.

Next, a Pt film having a thickness of about 50 nm and a thickness of about 6 are formed on the BST film 34 and the dummy lower electrode 33b.
nm TiAlN film and SiO ₂ film are sequentially deposited.
Then, the hard mask 3 is formed by patterning the SiO ₂ film.
After forming 7, the TiAlN film and the Pt film are sequentially patterned by dry etching using the hard mask 37 to form the upper barrier metal 36 covering the effective memory cell region Rec and the dummy cell region Rdc, the upper electrode 35a and the upper portion. The Pt film 35 including the electrode extension 35b is formed. At this time, the portion of the hard mask 37 located above the bit line plug 20b is also removed and the opening 59 is formed.

Next, in the step shown in FIG. 10B, after depositing the second interlayer insulating film 22, the second interlayer insulating film 22 is planarized by CMP until the hard mask 37 is exposed. Then, a contact hole 60 penetrating the hard mask 37 and reaching the bit line plug 20b is formed. At this time, by making the contact hole 60 sufficiently smaller than the inner diameter of the opening 59 formed in the step shown in FIG. 10A, the insulating film 5 is formed on the side surface of the contact hole 60.
2 is formed.

Next, in the step shown in FIG. 10C, a trench penetrating the second interlayer insulating film 22 and reaching the lower layer wiring plug 20d is formed. Then, Cu film deposition and CMP
And the contact hole 60 and the lower layer wiring plug 2
By embedding the Cu film in the trench above 0d, the upper layer bit line plug 51 and the Cu wiring 42 are formed.

Thereafter, the bit line is formed by depositing and planarizing the third interlayer insulating film 41, forming a contact hole and a trench in the third interlayer insulating film 41, and burying a Cu film in the contact hole and the trench. 53 is formed (dual damascene method). As a result, the structure of the memory cell shown in FIG. 9 is obtained.

According to the manufacturing method of this embodiment, the Pt film 3 forming the upper electrode 35a is formed on the hard mask 37.
5 can avoid the step of forming the contact hole reaching the upper part (upper barrier metal 36), and therefore, like the manufacturing method in the first embodiment, the capacitive insulation caused by the exposure to the reducing atmosphere. It is possible to reliably suppress the deterioration of the characteristics of the film 34a.

Further, in the present embodiment, since the bit line is arranged above the storage capacity portion, the bit line is formed in a separate process in the DRAM mixed process as compared with the structure in which the bit line is arranged below the storage capacity portion. Manufacturing is easy. Therefore, the semiconductor memory device of this embodiment is also advantageous in cost.

In the present embodiment, the upper electrode 3
Although 5a and the lower electrode 33a are made of Pt and the upper barrier metal 36 is made of TiAlN, these members may be made of another conductive material having oxidation resistance. Although the capacitor insulating film 34a is made of BST, it may be made of other high dielectric material. In particular, in the case of a dielectric film having a perovskite structure whose structural formula is represented by ABO ₃ , oxygen atoms are likely to be lost by reduction. Therefore, the present invention is applied to obtain a great effect.

Further, the present invention is not limited to the mixed device as in this embodiment, but may be a general-purpose DRAM or FeRA.
It goes without saying that the present invention can also be applied to a semiconductor memory device having a capacitor using a metal electrode such as M.

(Eighth Embodiment) In this embodiment as well, as in the case of the seventh embodiment, the present invention is applied to a bit-line-mounted type D in which the bit line is provided above the storage capacitor portion.
An example applied to the RAM memory cell structure will be described.
FIG. 11 is a sectional view showing the structure of a part of the memory portion of the semiconductor memory device according to the eighth embodiment. 12
(A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor memory device in 8th Embodiment. Hereinafter, regarding the structure and manufacturing method of the semiconductor memory device in the present embodiment,
This will be explained in order. Here, in each drawing of the present embodiment,
Although only the structure of the memory section is shown, the semiconductor memory device of the present embodiment is a mixed-type device in which a logic circuit element is provided in a logic circuit section (not shown) as in the first embodiment. However, since the structure itself of the logic circuit element is not directly related to the essence of the present invention, the illustration is omitted.

As shown in FIG. 11, the memory portion of this embodiment is similar to the fifth embodiment in that instead of the local wiring 21b made of the W / Ti film in the first embodiment, the element isolation insulation is used. A local wiring 24 made of polysilicon is provided on the film 11, and a lower dummy cell plug 20c penetrating the first interlayer insulating film 18 and contacting the local wiring 24.
And a lower layer wiring plug 20d penetrating the first interlayer insulating film 18 and contacting the local wiring 24.

Further, a lower barrier metal 54a made of TiAlN and a lower electrode 33a are provided on the entire bottom surface and side surface of one opening provided in the second interlayer insulating film 22 in the figure. On the other hand, in a part of another opening provided in the second interlayer insulating film 22, a dummy lower barrier metal 54b made of TiAlN and a dummy lower electrode 33b are provided from the side surface to the bottom surface of the opening. Then, the BST film 34 is provided on the lower electrode 33a, and the BST film 3 is formed.
4 and a dummy lower electrode 33b, a Pt film 35 and an upper barrier metal 36 are provided. BST film 3
4 of the capacitor insulating film 34 is in contact with the lower electrode 33a.
The portion of the Pt film 35 that faces the lower electrode 33a is the upper electrode 35a, and the portion of the Pt film 35 that contacts the dummy lower electrode 33b is the upper electrode extension portion 35b. That is, the cylindrical storage capacitor MC and the dummy cell are provided so as to extend from the first interlayer insulating film 18 to the second interlayer insulating film 22, and the dummy lower electrode 33b (dummy lower barrier metal 54b) is directly connected to the lower dummy cell plug 20c. To
The Cu wirings 42 are directly connected to the lower layer wiring plugs 20d, respectively. The local wiring 24 is formed of the same polysilicon film as the gate electrode 15. It should be noted that the planar shape of the cylindrical storage capacity section MC may be any of a circle, a quadrangle, and other polygons.

Furthermore, on the bit line plug 20b,
The upper layer bit line plug 5 that reaches the bit line plug 20b through the second interlayer insulating film 22 and the third interlayer insulating film 41.
1 and an insulator film 5 covering the side surface of the upper bit line plug 51.
2 and a bit line 53 made of a Cu film embedded in the third interlayer insulating film 41. That is, it has a structure of the bit line top type DRAM memory cell in which the bit line is provided above the storage capacitor portion MC.

Other members in FIG. 11 are the same as those in FIG.
It is the same as the member shown in FIG.
The same reference numerals as in (a) are attached.

According to the present embodiment, the dummy lower electrode 33
The upper electrode 35a and the Cu wiring 42 are electrically connected to each other via b, the dummy lower barrier metal 54b, the lower dummy cell plug 20c, the local wiring 24 and the lower wiring plug 20d. Also in this embodiment, it is not necessary to form a contact hole reaching the Pt film 35 (upper barrier metal 36) forming the upper electrode 35a in the third interlayer insulating film 41. Therefore, according to the present embodiment, while adopting the structure of the bit line placed type, the deterioration of the characteristics of the capacitance insulating film 34a is prevented and the dedicated equipment for forming the memory cell is not required as in the first embodiment. The effect of can be exhibited.

Next, the manufacturing process of the memory cell of the semiconductor memory device in this embodiment will be described with reference to FIGS.
This will be described with reference to (c).

The following processing is performed in the step shown in FIG. First, an element isolation insulating film 11 surrounding an active region is formed on a p-type Si substrate 10, and a source region 12 and a drain region 13 and a gate insulating film 14 are formed in the active region.
A memory cell transistor including the gate electrode 15 and the oxide film sidewall 16 is formed. This memory cell transistor formation process is performed by a well-known procedure using well-known techniques such as thermal oxidation, formation and patterning of a polysilicon film, and ion implantation. At this time, when forming the gate electrode 15, the local wiring 24 made of polysilicon is simultaneously formed on the element isolation insulating film 11.

Next, on the memory cell transistor, B
After depositing the PSG film, annealing and planarization by CMP (chemical mechanical polishing) are performed to form the first interlayer insulating film 18. Further, contact holes penetrating the first interlayer insulating film 18 to reach the source region 12, the drain region 13 and the local wiring 24 are formed. next,
An n-type polysilicon film is formed in the contact holes and on the first interlayer insulating film 18, and then planarized by CMP to fill the contact holes with the polysilicon film.

Next, on the first interlayer insulating film 18, NSG is formed.
After depositing the film, planarization by CMP is performed to
The interlayer insulating film 22 is formed. Then, the second interlayer insulating film 2
2, the lower layer memory cell plug 20a and the dummy cell plug 2
Openings exposing 0c are formed at two locations in the figure.

Next, on the substrate, TiA having a thickness of about 6 nm is formed.
After the 1N film and the Pt film having a thickness of about 30 nm are deposited, CMP is performed until the upper surface of the second interlayer insulating film 22 is exposed, so that Ti is formed on the bottom surface and the side surface of the two openings in the figure.
Lower barrier metal 54a, leaving AlN film and Pt film
Then, the lower electrode 33a, the lower dummy barrier metal 54b, and the dummy lower electrode 33b are formed. Next, a BST film ((BaSr) TiO ₃ having a thickness of about 30 nm was formed on the substrate.
After the film is deposited, the portion of the dummy cell region is removed by etching to form the BST film 34 including the capacitive insulating film 34a. Next, the BST film 34 and the second interlayer insulating film 2
2 and the dummy lower electrode 33b and a Pt film 35A having a thickness of about 30 nm and a TiAlN film 36A having a thickness of about 6 nm.
And are sequentially deposited.

Next, in the step shown in FIG. 12B, a hard mask 37 is formed which covers the effective memory cell region Rec and the dummy cell region Rdc and opens the other regions. At this time, the hard mask 37 has an opening 61 in a region located above the lower layer bit line plug 20b. afterwards,
The TiAlN film 36A and the Pt film 35 are dry-etched by using the hard mask 37 as an etching mask.
A and S are sequentially patterned to form an effective memory cell region Rec.
And the upper barrier metal 36 covering the dummy cell region Rdc
And P including the upper electrode 35a and the upper electrode extension 35b
The t-film 35 is formed. At this time, in a region other than the effective memory cell region Rec and the dummy cell region Rdc, T
The iAlN film and the Pt film are removed.

Next, in the step shown in FIG. 12C, after depositing the third interlayer insulating film 41, the third interlayer insulating film 41 is planarized by CMP. At this time, the opening 61 is temporarily filled with the insulator.

Then, by anisotropic etching, an opening 61 'penetrating the third interlayer insulating film 41 and the second interlayer insulating film 22 to reach the bit line plug 20b is opened. At this time, the inner diameter of the opening 61 ′ is made sufficiently smaller than that of the opening 61, so that the insulator film 52 is formed on the side surface of the opening 61 ′.

Next, although not shown, the third interlayer insulating film 41
And the lower layer wiring plug 20 penetrating the second interlayer insulating film 22.
A contact hole reaching d is formed. Then, a Cu film is deposited and CMP is performed to embed the Cu film in each contact hole, thereby forming the upper bit line plug 51 and the Cu film.
The wiring 42 is formed.

Then, the bit line is formed by depositing and planarizing the fifth interlayer insulating film 55, forming a contact hole and a trench in the fifth interlayer insulating film 55, and burying a Cu film in the contact hole and the trench. 53 is formed (dual damascene method). As a result, the structure of the memory cell shown in FIG. 11 is obtained.

According to the manufacturing method of this embodiment, avoiding the step of forming a contact hole reaching the Pt film 35 (upper barrier metal 36) forming the upper electrode 35a in the third interlayer insulating film 41. Because you can
Similar to the manufacturing method in the above embodiment, it is possible to reliably suppress deterioration of the characteristics of the capacitive insulating film 34a due to exposure to the reducing atmosphere.

Further, since the storage capacitor portion MC has a cylindrical structure, the capacity per unit area of the substrate increases, so that a DRAM in which memory cells are arranged at a high density can be obtained.

In this embodiment, the upper electrode 3
Although 5a and the lower electrode 33a are made of Pt and the upper barrier metal 36 is made of TiAlN, these members may be made of another conductive material having oxidation resistance. Although the capacitor insulating film 34a is made of BST, it may be made of other high dielectric material. In particular, in the case of a dielectric film having a perovskite structure whose structural formula is represented by ABO ₃ , oxygen atoms are likely to be lost by reduction. Therefore, the present invention is applied to obtain a great effect.

The present invention is not limited to the mixed device as in the present embodiment, but may be a general-purpose DRAM or FeRA.
It goes without saying that the present invention can also be applied to a semiconductor memory device having a capacitor using a metal electrode such as M.

In the present embodiment, an example in which the structure of the cylindrical storage capacitor section is applied to the bit line top type memory cell has been described. However, the structure of the cylindrical storage capacitor section shown in FIG. It is also possible to apply to a line-down type memory cell.

(Other Embodiments) In the seventh and eighth embodiments, the polysilicon film to be the gate wiring is used as the local wiring. However, the bit line is placed on the bit line like the seventh and eighth embodiments. A DRAM memory cell having a die structure can also have the same structure as that of the fourth and sixth embodiments. That is, in the DRAM memory cell having the bit line overlaid structure, the local wiring 23 made of the embedded W film shown in FIG. 6 and the local wiring 25 made of the impurity diffusion layer shown in FIG. 8 may be provided.

Further, the structure may be such that the dummy lower electrode is in direct contact with the Cu wiring.

In each of the above-mentioned embodiments, the present invention is applied to the DR.
Although the example applied to the embedded semiconductor memory device including the AM and the logic circuit has been shown, the present invention is not limited to this embodiment and can be applied to a general-purpose DRAM.

The present invention can also be applied to a semiconductor memory device using a ferroelectric film such as FeRAM as a capacitance insulating film. In that case, either the general-purpose memory type or the memory / logic mixed type may be used.

Although the hard mask is formed on the upper electrode in the above embodiment, a resist mask may be formed instead of the hard mask depending on the kind of the conductor material of the upper electrode and the lower electrode. Good. However, by using the hard mask, it is possible to suppress the collapse of the mask pattern during etching, and thus it is possible to improve the patterning accuracy.

Although the dummy lower electrode is provided in the first, second, and fourth to eighth embodiments of the present invention, it may not be necessarily provided. Therefore, the dummy conductor member connecting the upper electrode and the Cu wiring includes at least one of the dummy lower electrode, the dummy cell plug, and the local wiring.

[0137]

According to the present invention, since the upper electrode and the upper wiring can be surely electrically connected to each other without exposing the upper electrode, a semiconductor memory device in which the characteristic of the capacitance insulating film is less deteriorated is provided. Can be realized.

[Brief description of drawings]

1A and 1B are, respectively, in order of the first aspect of the present invention.
FIG. 3 is a cross-sectional view showing a structure of a part of a memory portion of the semiconductor memory device according to the embodiment and a plan view showing a structure of an upper electrode / dummy electrode.

2A to 2C are process cross-sectional views showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

3A to 3D are process cross-sectional views showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a semiconductor memory device according to a third embodiment of the present invention.

5A to 5C are process cross-sectional views showing the method for manufacturing the semiconductor memory device according to the third embodiment.

FIG. 6 is a cross-sectional view showing a structure of a part of a memory portion of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a structure of a part of a memory portion of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a structure of a part of a memory portion of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a structure of a part of a memory portion of a semiconductor memory device according to a seventh embodiment of the present invention.

10A to 10C are process cross-sectional views showing the manufacturing process of the semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a structure of a part of a memory portion of a semiconductor memory device according to an eighth embodiment of the present invention.

12A to 12C are process cross-sectional views showing the manufacturing process of the semiconductor memory device according to the eighth embodiment of the present invention.

[Explanation of symbols]

Space between 8 electrodes 10 Si substrate 11 Insulation film for element isolation 12 Source area 13 Drain region 14 Gate insulating film 15 Gate electrode 16 Oxide film sidewall 18 First interlayer insulating film 20a Lower layer memory cell plug 20b bit line plug 20c Lower layer dummy cell plug 20d lower layer wiring plug 21a bit line 21b Local wiring 22 Second interlayer insulating film 30a Upper layer memory cell plug 30b Dummy cell plug 30c wiring plug 32a Lower barrier metal 32b Dummy barrier metal 33a lower electrode 33b Dummy lower electrode 34 BST film 34a Capacitance insulating film 35,35A Pt film 35a upper electrode 35b Upper electrode extension 36 Upper barrier metal 36A TiAlN film 37 Hard Mask 41 Third interlayer insulating film 42 Cu wiring 51 Upper layer bit line plug 52 Insulator film 59,61,61 'aperture 60 contact holes

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akihiko Sabutani             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5F083 AD21 AD24 AD48 AD49 AD56                       FR02 GA27 JA13 JA14 JA17                       JA36 JA37 JA38 JA39 JA40                       MA06 MA16 MA18 MA19 MA20                       PR40 ZA12

Claims (21)

[Claims] 1. Provided on an insulating layer on a semiconductor substrate,
A storage capacitor portion composed of a lower electrode, an upper electrode, and a capacitive insulating film interposed between the lower electrode and the upper electrode; and an upper electrode extension portion continuously provided to the upper electrode of the storage capacitor portion, A semiconductor memory device comprising: a dummy conductor member provided so as to contact at least a portion under the upper electrode extension; and an upper layer wiring electrically connected to the dummy conductor member. 2. The semiconductor memory device according to claim 1, wherein the dummy conductor member includes a dummy lower electrode formed of the same conductor film as the lower electrode. 3. The semiconductor memory device according to claim 1, wherein the dummy conductor member includes a conductor film that fills a trench provided in the insulating layer. 4. The semiconductor memory device according to claim 1, wherein the dummy conductor member penetrates the local wiring provided on the semiconductor substrate below the insulating layer and the insulating layer to form the upper portion. The semiconductor memory device further comprising a plug electrically connecting the electrode extension and the local wiring. 5. The semiconductor memory device according to claim 4, further comprising a bit line formed below the storage capacitor portion with the insulating layer interposed therebetween, wherein the local wiring is the same conductor film as the bit line. A semiconductor memory device characterized by being formed from. 6. The semiconductor memory device according to claim 4, wherein at least a part of the upper electrode extension is planarly viewed.
A semiconductor memory device characterized in that it overlaps with the conductor plug. 7. The semiconductor memory device according to claim 1, wherein the element isolation insulating film provided on the semiconductor substrate below the insulating layer and the element isolation insulating film of the semiconductor substrate surrounds the element isolation insulating film. A memory cell transistor having a gate electrode and an impurity diffusion layer provided on both sides of the gate electrode in the semiconductor substrate, and a gate electrode provided on the element isolation insulating film. A semiconductor memory device further comprising: a local wiring formed of the same conductor film as the electrode; and a conductor plug penetrating the insulating layer to connect the local wiring. 8. The semiconductor memory device according to claim 1, wherein the memory cell is provided on the semiconductor substrate and has a gate electrode and impurity diffusion layers provided on both sides of the gate electrode in the semiconductor substrate. A transistor; a local wiring formed from another impurity diffusion layer provided apart from the impurity diffusion layer of the semiconductor substrate; and a conductor plug penetrating the insulating layer and connected to the local wiring. A semiconductor memory device further comprising: 9. The semiconductor memory device according to claim 2, wherein the upper layer wiring is in contact with the dummy lower electrode. 10. The semiconductor memory device according to claim 1, wherein the storage capacitor section has a cylindrical lower electrode, a capacitive insulating film, and an upper electrode. And semiconductor memory device. 11. The semiconductor memory device according to claim 1, wherein the capacitance insulating film is a high dielectric film or a ferroelectric film. 12. A storage capacitor portion including a lower electrode, an upper electrode, and a capacitance insulating film interposed between the lower electrode and the upper electrode, and an upper layer electrically connected to the upper electrode of the storage capacitor portion. A method of manufacturing a semiconductor memory device, comprising: a step (a) of forming local wiring on a semiconductor substrate; and a first conductor film on the semiconductor substrate after the step (a). And (b) forming the first conductor film to form at least the lower electrode, and forming a dielectric film serving as the capacitive insulating film that covers the lower electrode. Step (d), step (e) of forming a second conductor film on the semiconductor substrate after the step (d), and patterning the second conductor film to form the entire lower electrode. At least the electrode covering the local wiring and the local wiring. A step (f) of integrally forming an upper electrode extension that covers the upper electrode and is continuous with the upper electrode, and after the step (f), at least the local wiring and the upper electrode extension are provided on the semiconductor substrate. And (g) forming the upper layer wiring electrically connected to the upper electrode. 13. The method of manufacturing a semiconductor memory device according to claim 12, wherein after the step (a) and before the step (b), a first insulating film is formed on the semiconductor substrate including the local wiring. A step (a2) of forming a film, and a step (a3) of forming a first conductor plug and a second conductor plug which penetrate the first insulating film and are both electrically connected to the local wiring. Further, in the step (f), the upper electrode extension is formed so as to cover at least a part of the first conductor plug, and in the step (g), a second insulating layer is formed on the semiconductor substrate. After forming a film, a wiring embedding trench reaching the second conductor plug is formed in the second insulating film, and a conductive film is embedded in the trench to form the upper layer wiring. Storage device manufacturing method. 14. The method of manufacturing a semiconductor memory device according to claim 12, wherein in the step (a), the local wiring is made of the same conductor film as a bit line and is formed simultaneously with the bit line. A method for manufacturing a semiconductor memory device having a feature. 15. The method of manufacturing a semiconductor memory device according to claim 12, wherein in the step (a), the local wiring is formed of the same conductive film as a gate electrode of a memory transistor, and the gate electrode is formed. A method of manufacturing a semiconductor memory device, which is formed simultaneously with the above. 16. The method of manufacturing a semiconductor memory device according to claim 12, wherein in the step (a), the local wiring is formed of the same impurity diffusion layer as a source / drain region of a memory transistor, A method for manufacturing a semiconductor memory device, characterized in that it is formed separately from the source / drain regions at the same time when the drain regions are formed. 17. The method of manufacturing a semiconductor memory device according to claim 12, wherein in the step (a), the first insulating film formed on the semiconductor substrate is electrically connected to a source region of a memory cell transistor. A method of manufacturing a semiconductor memory device, characterized in that the local wiring is formed at the same time as forming a memory cell plug connected to the. 18. The method of manufacturing a semiconductor memory device according to claim 12, wherein in the step (c), at least a part of the local wiring is separated from the lower electrode. A semiconductor including a step of forming a dummy lower electrode made of the first conductive film to cover, the local wiring and the upper electrode extension being electrically connected via the dummy lower electrode. Storage device manufacturing method. 19. The method of manufacturing a semiconductor memory device according to claim 18, wherein in the step (d), the dielectric film covering the lower electrode and the dummy lower electrode is formed, and in the step (e), Forming the second conductor film covering the dielectric film, and performing the same etching as in forming the upper electrode and the upper electrode extension after the step (f) and before the step (g). Patterning the dielectric film using a mask to form a dielectric film for a capacitive insulating film; and between at least the dummy lower electrode and the upper electrode extension of the dielectric film for a capacitive insulating film. A step of forming a space between electrodes by etching a portion located at the same time and forming the capacitive insulating film; and a step of heat-treating the upper electrode extension on the space between electrodes to deform the upper electrode extension. And a step of bringing the dummy lower electrode into contact with the dummy lower electrode. 20. The method of manufacturing a semiconductor memory device according to claim 12, wherein after the step (a) and before the step (b), a first insulating film is formed on the semiconductor substrate including the local wiring. With the step (a4) of forming a film, both the first conductor plug and the second conductor plug that penetrate through the first insulating film and are electrically connected to the local wiring.
Step (a5) of forming a conductor plug of
After 5), a step (a6) of forming a step insulating film on the semiconductor substrate, and a first opening for forming the lower electrode of the storage capacitor section in the step insulating film. And a step (a7) of forming a second opening for forming a dummy lower electrode connected to the first conductor plug, the step (c) further comprising: Forming the lower electrode on the side surface and the bottom surface and forming the dummy lower electrode on the side surface and the bottom surface of the second opening; and, in the step (f), the upper electrode extension portion is the dummy lower electrode. The electrode is formed to cover at least a part of the electrode, and in the step (g), the second insulating film is formed on the semiconductor substrate, and then the second insulating film and the step insulating film are formed on the second insulating film. A trench for wiring embedding that reaches the conductor plug of Form, method of manufacturing a semiconductor memory device characterized by forming the upper layer wiring by burying a conductive film on the trench. 21. The method of manufacturing a semiconductor memory device according to claim 12, wherein the dielectric film is a high dielectric film or a ferroelectric film. Storage device manufacturing method.