JP2003100880A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the latching up in an outside device region due to a surge between pads and a power supply or a ground in a semiconductor device which has a device region (outside device region) outside the position of pads on a chip. SOLUTION: An n-well 10 having no p-type diffusion layer inside is formed between pads 5 and the outside device region 4 on a chip formed by a p-type substrate 1. The n-well 10 is brought into contact with the power supply and is at the power supply potential. With this structure, when a surge occurs between the pads 5 and the power supply, the electrical charge which may be a trigger of latching up of the outside device region 4 can be absorbed through the n-well 10. Accordingly, the latching up by the surge in the outside device region 4 hardly occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique for improving the latch-up withstand capability.

[0002]

2. Description of the Related Art In recent years, the performance of semiconductor devices has been remarkably improved.
In addition, the demand is increasing. Therefore, development of a semiconductor device with higher reliability is desired.

For example, a semiconductor device having a CMOS (complementary MOS) structure has a parasitic thyristor because of its structure. When a momentary abnormal voltage (surge) occurs in such a semiconductor device, it triggers and the parasitic thyristor operates, causing a so-called latch-up, in which a current continues to flow from the power supply to the ground. There is. When latch-up occurs, it may cause a malfunction of the device, and the device itself may be destroyed by it.

The above parasitic thyristor becomes easier to operate as the degree of integration of the device increases, and is considered to be one of the important issues as the integration of semiconductor devices increases in the future.

It is also possible to improve the latch-up resistance of the semiconductor device by using, for example, an epitaxial wafer as a material. However, the epitaxial wafer is overwhelmingly expensive as compared with a normal single-concentration substrate wafer (mirror wafer), and is not practical. Therefore, it is very important to improve the latch-up resistance of the device by devising the layout of the semiconductor device.

Conventionally, as a method of preventing latch-up, there is a method of using a substrate contact or a well contact. FIG. 5 is a diagram showing a method of preventing latch-up using a substrate contact and a well contact in a conventional semiconductor device. In this figure, 101 is a P-type region on a P-type substrate, 111 and 112 are N-wells, 12
1, 122, 123 are P-type diffusion layers, 131, 132, 1
Reference numeral 33 represents an N-type diffusion layer.

As shown in the figure, the N well 111 is contacted with the power source Vcc through the N type diffusion layer 131, and P
The mold region 101 is in contact with the ground via the P-type diffusion layer 122. That is, N well 111 and P
Well contacts and substrate contacts are provided in the mold region 101, respectively. Thereby, the P-type diffusion layer 12
1 and the N well 111, the P-type region 101, and the N-type diffusion layer 132 can prevent the parasitic thyristor formed between the power supply Vcc and the ground from operating and prevent latch-up.

Ideally, it is desirable that all the substrate and well regions are surrounded by the substrate contact and the well contact, and all of them are set to the power supply potential or the ground potential. However, it is difficult to arrange the contacts all around the substrate and the well due to the circuit configuration in an actual product, and it is often impossible to sufficiently prevent latch-up. FIG. 6 is a diagram showing an example of such a case. In this figure, the same elements as those shown in FIG. 5 are designated by the same reference numerals, and the description thereof is omitted here.

In FIG. 6, a well contact and a substrate contact are not formed between the P type diffusion layer 121 and the N type diffusion layer 132. Therefore, when a negative surge occurs on the pad with the potential of the power supply Vcc as a reference, it triggers, and as shown in FIG. 7, the P-type diffusion layer 121 and the N well 111, the P-type region 101, and the N-type diffusion layer 132.
As a result, the parasitic thyristor operates, causing latch-up in which a current continues to flow from the power supply Vcc to the ground.

As described above, it is an important subject to suppress the latch-up caused by the surge in the semiconductor device. Therefore, a semiconductor device that suppresses the occurrence of such latch-up has been proposed.

For example, FIG. 8 is a sectional view showing the structure of a conventional semiconductor device which suppresses the occurrence of latch-up due to a surge. In this figure, elements having the same functions as those in FIGS. 5 and 6 are designated by the same reference numerals, and detailed description thereof will be omitted. Further, 50 is an N well and 51 is an N type diffusion layer. N as shown in this figure
The well 50 is in contact with the power supply Vcc via the N-type diffusion layer 51. Further, the N well 50 does not have a P type diffusion layer inside. It is desirable that the N well 50 be arranged around the location where the surge occurs. However, in general, the surge is likely to occur at a pad portion for inputting / outputting a signal to / from a semiconductor device. It is provided between the element region where the element is formed and the pad.

FIG. 9 is a plan view showing a more specific example of the structure of the semiconductor device shown in FIG. In this figure, elements having the same functions as those shown in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 9, an N well 50 is formed so as to surround a circuit including a PMOS transistor formed in the N well 122 and an NMOS transistor in the P-type region 101, such as a port buffer. Although not shown, the N well 50 is in contact with the power source and has the power source potential as described above.

According to this structure, when a surge occurs between the pad and the power supply, the charge that triggers latch-up can be absorbed through the N well 50 that is in contact with the power supply. That is, latch-up due to surge is less likely to occur. Therefore, even when the well contact and the substrate contact cannot be arranged well due to the circuit configuration of the device, the latch-up resistance can be improved.

[0015]

In the structure of the conventional semiconductor device, the pad is usually arranged along the outer periphery of the chip on which the semiconductor device is formed, and the semiconductor element is formed inside the pad. Therefore, the N well contacted with the power supply as described above for the purpose of preventing latch-up is provided between the pad and the element region inside thereof.

Incidentally, with the recent increase in the size of LSI chips, it is becoming difficult to form all the element regions inside the conventional pad positions. At this time, if the size of the chip is increased and the pads are arranged on the outer periphery of the chip, the positions of the pads will be different from those of the conventional chip. However, changing the position of the pads on the chip involves changing the design of the measurement jig in the manufacturing process of the semiconductor device, such as the arrangement of the probe needles of the probe card used in the wafer test. Will increase the production cost.

Therefore, it is conceivable that the element region is formed further outside the position of the pad on the chip without changing the position of the pad depending on the size of the chip. But,
In the conventional semiconductor device, since the element region outside the pad is not assumed, latch-up may easily occur in the element region outside the pad.

In the present specification, an element region formed inside the pad on the chip is called an inner element region, and an element region formed outside is called an outer element region.

The present invention has been made to solve the above problems, and in a semiconductor device having an element region (outer element region) further outside the position of the pad on the chip, the pad and the power source are provided. Alternatively, it is an object of the present invention to provide a semiconductor device capable of suppressing the occurrence of latch-up in the outer element region due to a surge generated with the ground.

[0020]

According to another aspect of the present invention, there is provided a semiconductor device comprising: a chip formed of a P-type semiconductor substrate;
A semiconductor device having a pad arranged at a predetermined position for inputting / outputting a signal to / from a semiconductor element and an outer element region formed outside the position of the pad and in which the semiconductor element is formed A first N well or a first N type diffusion layer having no P type diffusion layer is provided between the pad and the outer element region, and the first N well or the first N well is provided. The N-type diffusion layer is in contact with the power supply.

The semiconductor device according to claim 2 is the semiconductor device according to claim 1.
The semiconductor device according to the item [1], wherein P is provided between the pad and the inner element region and an inner element region that is arranged inside the pad and in which the semiconductor element is formed.
A second N well or a second N type diffusion layer having no type diffusion layer, the second N well or the second N well.
The type diffusion layer is contacted with a power source.

According to another aspect of the semiconductor device of the present invention, a pad for inputting / outputting a signal to / from a semiconductor element, which is arranged at a predetermined position on a chip formed of an N-type semiconductor substrate, and the pad. A semiconductor device having an outer element region in which the semiconductor element is formed, the outer element region being disposed outside the position of, and having no N-type diffusion layer between the pad and the outer element region. One P-well or a first P-type diffusion layer is provided, and the first P-well or the first P-well is provided.
The mold diffusion layer is in contact with the ground.

A semiconductor device according to a fourth aspect is the semiconductor device according to the third aspect.
The semiconductor device according to claim 1, wherein N is provided between the pad and the inner element region, the inner element region being provided inside the pad, where the semiconductor element is formed.
A second P well having no type diffusion layer or a second P type diffusion layer, wherein the second P well or the second P well is provided.
The mold diffusion layer is in contact with the ground.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Preferred Embodiment> FIG. 1 is a plan view showing a structure of a semiconductor device according to a first preferred embodiment. In this figure, 1 is a P-type substrate forming a chip of a semiconductor device, and the broken line shown by 2 indicates the end of the chip. Reference numeral 3 denotes an inner element region formed inside the pad 5, and 4 denotes an outer element region formed outside the pad 5. Reference numeral 10 denotes an N well having no P-type diffusion layer therein, and although not shown, the N well 10 is in contact with a power source and has a power source potential. As described above, the semiconductor device according to the present embodiment has the outer element region 4
N-well 1 in contact with the power supply between the pad and the pad 5
The configuration has 0.

According to this structure, when a negative surge occurs on the pad 5 with the power supply as a reference, the charge that triggers the latch-up of the outer element region 4 is supplied to the N well 10.
Can be absorbed through. Therefore, the latch-up due to the surge hardly occurs in the outer element region 4. That is, it is possible to improve the latch-up withstand amount in the semiconductor device having the element region outside the pad.

Although FIG. 1 shows the structure in which the N well 10 is arranged along the outside of the pad 5, the arrangement of the N well is not limited to this. It suffices if the N well 10 is arranged between the outer element region 4 and the pad 5, and it is obvious that the same effect can be obtained even if the N well 10 is arranged so as to surround the outer element region 4. .

In particular, in the case of a layout in which the power supply for the outer element region 4 is wired along the outside of the pad 5,
The N well 10 may be formed along the power supply wiring path and contacted with the power supply. That is, it is not necessary to reserve a region for forming the N well 10. Therefore, in the case of such a layout, the size of the semiconductor chip is not increased by forming the N well 10.

Further, in the structure shown in FIG. 1, the inner element region 3 is further provided by providing the N well 10 which is in contact with the power source between the pad 5 and the inner element region 3 as in the conventional semiconductor device. It is obvious that the effect of preventing the occurrence of latch-up can be obtained for both the outer element region 4 and the outer element region 4.

<Second Embodiment> FIG. 2 is a plan view showing the structure of a semiconductor device according to a second embodiment. In this figure, elements having the same functions as those shown in FIG. 1 are designated by the same reference numerals. As shown in the figure, also in the present embodiment, the inner element region 3 is formed inside the pad 5, and the outer element region 4 is formed outside. Also, 15 is N
Although not shown, the N-type diffusion layer 1 is a type diffusion layer.
Reference numeral 5 is in contact with the power supply and has a power supply potential. As described above, the semiconductor device according to the present embodiment is configured to have the N-type diffusion layer 15 in contact with the power supply between the outer element region 4 and the pad 5. That is, the N-type diffusion layer 15 is formed instead of the N-well 10 in FIG.

According to this structure, when a negative surge occurs on the pad 5 with the power source as a reference, the charge that triggers the latch-up of the outer element region 4 is charged with the N-type diffusion layer 1.
5 can be absorbed. Therefore, the latch-up due to the surge hardly occurs in the outer element region 4. That is,
It is possible to improve the latch-up resistance in a semiconductor device having an element region outside the pad as well.

In general, the N-type diffusion layer is easier to form than the N-well, so that this embodiment can be easily implemented as compared with the first embodiment. Therefore, it can contribute to simplification of the process for manufacturing a semiconductor device.

Although the N-type diffusion layer 15 is arranged along the outside of the pad 5 in FIG. 2, the arrangement of the N well is not limited to this. N-type diffusion layer 1
It suffices that 5 is arranged between the outer element region 4 and the pad 5, and it is apparent that the same effect can be obtained even if it is arranged so as to surround the outer element region 4.

In particular, in the case of a layout in which the power supply for the outer element region 4 is wired along the outside of the pad 5,
The N-type diffusion layer 15 may be formed along the power supply wiring path and contacted with the power supply. That is, the N-type diffusion layer 15
It is not necessary to reserve a special area for forming the. Therefore, in the case of such a layout, the size of the semiconductor chip is not increased by forming the N-type diffusion layer 15.

Further, in the structure shown in FIG. 2, an N-type diffusion layer 15 which is in contact with the power source is further provided between the pad 5 and the inner element region 3 so that the inner element region 3 and the outer element region 4 are separated from each other. It is obvious that the effect of preventing the occurrence of latch-up can be obtained for both.

<Third Embodiment> In the first and second embodiments, the case where the P-type substrate is used has been described, but the present invention is applicable to the case where the N-type substrate is used.

FIG. 3 is a plan view showing the structure of the semiconductor device according to the third preferred embodiment. In this figure, reference numeral 21 is an N-type substrate forming a chip of a semiconductor device, and a broken line indicated by 22 indicates an end of the chip. 23 is a pad 25
Is an inner element region formed inside the pad, and 24 is an outer element region formed outside the pad 25. Again 30
Is a P-well having no N-type diffusion layer therein, and although not shown, the P-well 30 is in contact with the ground and has a ground potential. As described above, the semiconductor device according to the present embodiment is configured to have the P well 30 in contact with the ground between the outer element region 24 and the pad 25.

According to this structure, when a positive surge occurs with respect to the pad 25 with respect to the ground, the charge that triggers the latch-up of the outer element region 24 can be absorbed through the P well 30. Therefore, the outer element region 2
In No. 4, latchup due to surge is less likely to occur.
That is, it is possible to improve the latch-up withstand amount in the semiconductor device having the element region outside the pad.

Although the P well 30 is arranged along the outside of the pad 25 in FIG. 1, the arrangement of the N well is not limited to this. P well 30
Need only be arranged between the outer element region 24 and the pad 25, and it is clear that the same effect can be obtained even if it is arranged so as to surround the outer element region 24, for example.

In particular, in the case of a layout in which the ground for the outer element region 24 is wired along the outside of the pad 25, the P well 30 may be formed along the ground wiring path and contacted with the ground. . That is,
It is not necessary to reserve a region for forming the P well 30. Therefore, in such a layout, the size of the semiconductor chip is not increased by forming the P well 30.

Further, in the structure shown in FIG. 1, by further providing a P well 30 which is in contact with the ground between the pad 25 and the inner element region 23, both the inner element region 23 and the outer element region 24 are provided. On the other hand, it is obvious that the effect of preventing the occurrence of latch-up can be obtained.

<Fourth Preferred Embodiment> FIG. 4 is a plan view showing a structure of a semiconductor device according to a fourth preferred embodiment. In this figure, elements having the same functions as those shown in FIG. 3 are designated by the same reference numerals. As shown in the figure, also in the present embodiment, the inner element region 2 is formed inside the pad 25.
3, the outer element region 24 is formed on the outer side. Also,
Reference numeral 35 denotes a P-type diffusion layer, which is not shown in the drawing, but the P-type diffusion layer 35 is in contact with the ground and has a ground potential. As described above, the semiconductor device according to the present embodiment is configured to have the P-type diffusion layer 35 in contact with the ground between the outer element region 24 and the pad 25. That is, the P-type diffusion layer 35 is formed instead of the P-well 30 in FIG.

According to this structure, when a positive surge occurs with respect to the pad 25 with respect to the ground, the charge that triggers the latch-up of the outer element region 4 can be absorbed through the P-type diffusion layer 35. Therefore, the outer element region 4
The latch-up due to the surge is unlikely to occur. That is, it is possible to improve the latch-up withstand amount in the semiconductor device having the element region outside the pad.

In addition, since the P-type diffusion layer is generally easier to form than the P-well, this embodiment can be easily implemented as compared with the third embodiment. Therefore, it can contribute to simplification of the process for manufacturing a semiconductor device.

Although the P-type diffusion layer 35 is arranged along the outside of the pad 25 in FIG. 4, the arrangement of the P-well is not limited to this. It suffices that the P-type diffusion layer 35 be arranged between the outer element region 4 and the pad 5, and it is apparent that the same effect can be obtained even if it is arranged so as to surround the outer element region 4. Is.

In particular, in the case of a layout in which the ground for the outer element region 24 is wired along the outside of the pad 25, the P-type diffusion layer 35 is formed along the ground wiring path.
Should be formed and contacted with the ground. That is, it is not necessary to reserve a region for forming the P-type diffusion layer 35. Therefore, in the case of such a layout, the size of the semiconductor chip is not increased by forming the P type diffusion layer 35.

Further, in the structure shown in FIG. 4, by further providing a P-type diffusion layer 35 in contact with the ground between the pad 25 and the inner element region 3, the inner element region 3 and the outer element region 4 are separated. It is obvious that the effect of preventing the occurrence of latch-up can be obtained for both.

[0047]

According to the semiconductor device of the first aspect,
In a semiconductor device having an outer element region, a first N having no P-type diffusion layer between the pad and the outer element region.
The well or the first N-type diffusion layer is provided, and the first N-well or the first N-type diffusion layer is contacted with the power source. Therefore, when a surge occurs between the pad and the power source, the outer element region is formed. Can be absorbed through the first N well or the first N type diffusion layer. Therefore, latch-up due to surge is less likely to occur in the outer element region. That is, it is possible to improve the latch-up withstand amount in the semiconductor device having the element region outside the pad.

According to the semiconductor device of the second aspect, in the semiconductor device of the first aspect, the inner element region and
A second N well or a second N type diffusion layer having no P type diffusion layer is further provided between the pad and the inner element region,
Since the second N well or the second N type diffusion layer is brought into contact with the power supply, it is possible to obtain an effect of preventing the latch-up from occurring in both the inner element region and the outer element region.

According to the semiconductor device of the third aspect, in the semiconductor device having the outer element region, the first P well or the first P well having no N-type diffusion layer is provided between the pad and the outer element region. Since the first P-type diffusion layer is provided and the first P-type well or the first P-type diffusion layer is brought into contact with the ground, when the surge occurs between the pad and the ground, the outer element region is latched up. Can be absorbed through the first P-well or the first P-type diffusion layer. Therefore, latch-up due to surge is less likely to occur in the outer element region. That is, it is possible to improve the latch-up withstand amount in the semiconductor device having the element region outside the pad.

According to a fourth aspect of the semiconductor device, there is provided the semiconductor device according to the third aspect, wherein the inner element region and
A second P well or a second P type diffusion layer having no N type diffusion layer is further provided between the pad and the inner element region,
Since the second P-well or the second P-type diffusion layer is in contact with the ground, it is possible to obtain the effect of preventing the latch-up from occurring in both the inner element region and the outer element region due to the surge.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment.

FIG. 2 is a plan view showing a configuration of a semiconductor device according to a second embodiment.

FIG. 3 is a plan view showing a configuration of a semiconductor device according to a third embodiment.

FIG. 4 is a plan view showing a configuration of a semiconductor device according to a fourth embodiment.

FIG. 5 is a diagram showing a method of preventing latch-up using a substrate contact and a well contact in a conventional semiconductor device.

FIG. 6 is a diagram for explaining a problem in a conventional semiconductor device.

FIG. 7 is a diagram for explaining a problem in a conventional semiconductor device.

FIG. 8 is a sectional view showing a configuration of a conventional semiconductor device.

FIG. 9 is a plan view showing a more specific example of the configuration of a conventional semiconductor device.

[Explanation of symbols]

1 P-type substrate, 2,22 chip edge, 3,23 inner element region, 4,24 outer element region, 5,25 pad,
10 N well, 15 N type diffusion layer, 21 N type substrate, 3
0 P well, 35 P type diffusion layer.

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Claims (4)

[Claims] 1. A pad formed on a chip formed of a P-type semiconductor substrate for inputting and outputting a signal to and from a semiconductor element, which is arranged at a predetermined position, and arranged outside the position of the pad. A semiconductor device having an outer element region in which the semiconductor element is formed, the first N well or the first N well having no P-type diffusion layer between the pad and the outer element region. A semiconductor device comprising an N-type diffusion layer, wherein the first N-well or the first N-type diffusion layer is contacted with a power supply. 2. The semiconductor device according to claim 1, wherein an inner element region in which the semiconductor element is formed, which is arranged inside a position of the pad, and the pad and the inner element region. A second N well or a second N type diffusion layer having no P type diffusion layer is further provided between the second N well and the second N type diffusion layer, and the second N well or the second N type diffusion layer is contacted with a power source. A semiconductor device characterized by: 3. A chip formed of an N-type semiconductor substrate, which is arranged at a predetermined position for inputting and outputting a signal to and from a semiconductor element, and arranged outside the position of the pad. A semiconductor device having an outer element region in which the semiconductor element is formed, the first P well or the first P well having no N-type diffusion layer between the pad and the outer element region. A semiconductor device comprising a P-type diffusion layer, wherein the first P-well or the first P-type diffusion layer is in contact with the ground. 4. The semiconductor device according to claim 3, wherein an inner element region in which the semiconductor element is formed is arranged inside a position of the pad, and the pad and the inner element region. A second P-well or a second P-type diffusion layer having no N-type diffusion layer between them, the second P-well or the second P-type diffusion layer being in contact with the ground. A semiconductor device characterized by: