JP2003100099A - Semiconductor circuit system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit system for extending a lifetime and reducing a manufacturing cost of an one chip microcomputer. SOLUTION: This system is provided with a nonvolatile memory from which data stored by an operation power source controlled by a power source control circuit incorporated in an one chip microcomputer is read out and which has possibility of data retention being defect cause, a defect detecting means for detecting defective read-out of the nonvolatile memory caused by the data retention, a compensating means for generating compensation data for compensating normal potential data for deteriorated read-out potential, and a potential change means for changing a potential level of the operation power source based on the compensation data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit system such as a one-chip microcomputer (hereinafter referred to as a microcomputer) having a built-in non-volatile memory, and more particularly to data retention of the non-volatile memory. The present invention relates to a semiconductor circuit system provided with a read failure countermeasure.

[0002]

2. Description of the Related Art A one-chip microcomputer is at least a microprocessor or a central processing unit (hereinafter, CPU-Cent
Abbreviated as ral Processing Unit. ) And the like, and a non-volatile memory. Non-volatile memory is a memory that does not lose its stored contents even when the power supply is cut off, and can read the stored contents by applying a read potential after the power is turned on again, but it is stressed by repeated reading. When,
In some cases, the potential of the bit line may deteriorate and the normal potential may not be maintained. Retention (re
tention-retention / stagnation-) means that the data read operation is delayed and the data cannot be read.

For example, a conventional semiconductor circuit system including a one-chip microcomputer will be described with reference to FIG. In FIG. 7, a semiconductor circuit system 70 includes a flash EEPROM (Electr) including an error correction code (ECC-Error Correct Code-) circuit 72.
icaly Erasable and Programmable Read Only Memory)
A cell 75, a data bus 73 for transmitting data in the system 70, a control bus 74 for transmitting a microcomputer control signal, and an EC output from the ECC circuit 72.
The comparison circuit 76 for comparing C with the cell data read from the memory cell 75, the correction circuit 77 for outputting the correction data to the data bus 73 when the comparison result of the comparison circuit 76 does not match, and the power supply terminal 79 A regulator 78 for fixing a power supply potential input via the power supply potential to a predetermined read potential is provided.

The operation of the comparison circuit 76 and the correction circuit 77 will be described. The ECC output from the ECC circuit 72 is described.
And the cell data read from the cell 75 match, the cell data read from the cell 75 by the comparison circuit 76 is directly output to the data bus 73 as described above, and the ECC and the cell data are unified. If not, the output from the comparison circuit 76 to the data bus 73 is stopped and the correction data is output from the correction circuit 77 to the data bus 73.

In the above-described conventional semiconductor circuit system, if data retention occurs when reading the data stored in the memory cell 75, the bit line potential of a specific cell in the memory fluctuates. When reading, the threshold potential inside the chip (“0”)
Or "1" determination level) and the bit line potential are deviated. ECC output from the ECC circuit 72
Contains the original read level of a particular cell,
As a result of comparison by the comparison circuit 76, if there is a mismatch between the ECC and the cell data, the correction circuit 77 inverts the erroneous bit to correct it,
The correction data is used as correct cell data in the data bus 7
It is output to 3.

The comparison operation of the comparison circuit 76 and the correction operation of the correction circuit 77 are as described above. Therefore, when the read cell data contains an error for only one bit, the error is erroneously made. The cell data can be corrected by correcting and outputting the existing bits. However,
When the cell data read from the specific cell includes an error of the second bit, if the first bit is corrected and output, the error of the second bit cannot be corrected, From that point, the entire data cannot be read accurately. Therefore, if an error of two bits occurs in the data read out for a specific cell, it is impossible to read the data accurately at that point, and the life of the product will end up.

In addition, although a product test is performed when a one-chip microcomputer is manufactured and shipped, data retention is selected as an initial defect in this test process. One such initial failure selection test
Doing this for one product adds to the cost of testing, and data retention is also a factor in this cost increase.

[0008]

As described above, according to the conventional semiconductor circuit system, the correction when the data retention occurs can be performed only for one bit, and the second bit for the same cell can be corrected. However, there was a problem in that it would not be possible to correct when an error occurred. Therefore, there is a problem that the correction using the ECC cannot be performed at the time when the error of the second bit due to the data retention occurs in the specific cell, and the life of the one-chip microcomputer is exhausted.

In addition, in the product test when shipping the one-chip microcomputer, each chip is tested, and the chip having the initial defect is selected and excluded from the shipped products. Providing the test process before shipment increases the test cost and also reflects the sales cost of the product, which raises the problem of increasing the cost of the one-chip microcomputer.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor circuit system capable of extending the life and reducing the cost of a one-chip microcomputer.

[0011]

To achieve the above object, in a semiconductor circuit system according to the basic configuration of the present invention, data stored by an operating power supply which is built in a one-chip microcomputer and controlled by a power supply control circuit is used. A non-volatile memory that is read and has a possibility of data retention as a cause of failure, a failure detection unit that detects a read failure of the nonvolatile memory due to the data retention, and a time when the read failure is detected. A correction means for generating correction data for correcting the deteriorated read potential to normal data, and a potential changing means for changing the potential level of the operating power supply based on the correction data. .

In the semiconductor circuit system according to the above-mentioned basic configuration, the threshold level is adjusted by changing the potential of the power supply control circuit such as a regulator with respect to a data read error caused by data retention in the nonvolatile memory. Or by overwriting the data for which retention has occurred, the occurrence of a read error is avoided. As a result, it is possible to prevent the occurrence of a read error due to the data retention, and as a result, it is possible to extend the life of the product such as the one-chip microcomputer equipped with the semiconductor circuit system.

[0013]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
An embodiment of a semiconductor circuit system according to the present invention will be described in detail. FIG. 1 is a block diagram showing a schematic configuration of a semiconductor circuit system according to a first embodiment corresponding to the basic configuration of the invention.

As shown in FIG. 1, the semiconductor circuit system according to the first embodiment of the present invention is configured as a one-chip microcomputer 1. This one-chip microcomputer 1 is at least a microprocessor unit (hereinafter, MPU-Mi).
Notated as cro Processor Unit. 2) and the microcomputer 1
Data bus 3 that mediates the sending and receiving of data inside the computer
And a control bus 4 that mediates transmission and reception of control signals in the microcomputer 1, and a non-volatile memory 5 having a possibility of data retention as a cause of failure.

The non-volatile memory 5 built in the one-chip microcomputer 1 is for reading the data stored therein when an operating power source controlled by the power source control circuit is applied. The one-chip microcomputer 1 further includes a defect detection unit 6 that detects a read failure of the non-volatile memory 5 caused by the data retention, and corrects a deteriorated read potential to normal data when the read failure is detected. Correction means 10 for generating correction data for
And potential changing means 20 for changing the potential level of the operating power supply based on the correction data. Reference numeral 8 is a power supply terminal for supplying operating power to the one-chip microcomputer 1.

Although not shown in the drawings, in the first embodiment, a regulator as a power supply control circuit is provided inside the potential changing means 20, and the normal power supply control operation is also performed inside the potential changing means 20. Is being processed.
The first embodiment is the most basic and conceptual embodiment of the present invention, and includes the general concept of the second to sixth embodiments described below. Therefore, when the reference numerals used in FIG. 1 are attached to FIGS. 2 to 6, the same reference numerals in each drawing are assumed to control the same functional configuration in each embodiment.

According to the semiconductor circuit system of the first embodiment, the operating power source supplied through the power source terminal 8 and controlled by the regulator as the power source control circuit provided inside the potential changing means 20 is nonvolatile. In addition to the non-volatile memory 5, the data stored in the non-volatile memory 5 is read out to the defect detecting means 6, where an error correction code (ECC) is read.
And the cell data are compared with each other, and if they match each other, the output to the correction means 7 is turned off and the read data is output to the data bus 3. If it is detected by comparison of the defect detection means 6 that the ECC and the cell data do not match, the fact that data retention has occurred is output to the correction means 10.

The correction means 10 creates correction data for changing the operating potential by the potential changing means 20 and outputs it to the potential changing means 20. The details of the creation of the correction data differ depending on the embodiment, such as correction data in which the potential is fixed and adjusted for each semiconductor circuit system according to the second to sixth embodiments, and correction data for automatically adjusting the potential. ing. The potential adjusting operation performed by the potential adjusting unit 20 based on the correction data from the correcting unit 10 may be fixed by fixing the potential or may be automatically adjusted according to the embodiment. The semiconductor circuit systems according to the second to sixth embodiments including the specific configurations of the correcting means 10 and the potential changing means 20 will be described below.

FIG. 2 is a block diagram showing a semiconductor circuit system according to the second embodiment of the present invention. In FIG. 2, the one-chip microcomputer 1 includes a nonvolatile memory 5 including a flash EEROM cell and the like, a defect detecting means 6,
The correction means 10 and the potential changing means 20 are provided, the non-volatile memory 5 has an ECC circuit 51, and the defect detecting means 6 is composed of a comparison circuit 7 for comparing an ECC code with cell data. The correcting means 10 determines whether or not the correction is necessary based on the output of the comparison circuit 7, and the potential changing means 20 is operated by the operation when it is determined that the correction is necessary. A trigger circuit 12 that triggers a potential change and a correction data circuit 13 that obtains a change amount of the potential to be changed as correction data and outputs the correction data to the potential changing unit 20 are provided.

The potential changing means 20 comprises a regulator 21 with a potential adjusting circuit and a normal regulator 22 having a fixed potential. The regulator 21 with the potential adjusting circuit is supplied with the trigger signal and the correction data of the trigger circuit 12 and the correction data circuit 13 of the correcting means 10, respectively, and the operating potential supplied through the power input terminal 8 is adjusted. ing.

In the semiconductor circuit system according to the second embodiment having the above-mentioned configuration, when the ECC circuit 51 corrects data or confirms a memory data read error during product operation, this data correction operation or error is performed. The confirmation operation is the trigger to start the ECC error correction operation, and the direction of potential change that raises or lowers the potential is determined based on the content of the data read error.
The read potential is automatically adjusted by fixing the potential as an operating power source or by using the potential of a regulator provided for adjustment.

As described above, in the semiconductor circuit system according to the second embodiment shown in FIG. 2, a code is set for data having an arbitrary number of bits, and it is determined whether the code is correct or incorrect when accessed. It is possible to correct the read error of the memory 5 by using a fixed or automatic set potential by using the ECC circuit 51 which corrects the data and outputs the corrected data when it is wrong.

Next, a semiconductor circuit system according to the third embodiment of the present invention will be described with reference to FIG. Concerning the circuit system of the third embodiment, the components corresponding to those of the circuit system of the first embodiment in FIG. 1 will be described with the same reference numerals for convenience of description. In FIG. 3, the one-chip microcomputer 1 in which the circuit system is provided includes a non-volatile memory 5 having an ECC circuit 51 inside, a defect detecting unit 6, a correcting unit 10, and a potential changing unit 20.

The defect detecting means 6 comprises a comparison circuit 7 for comparing the ECC code with the cell data. The correction means 10 includes a correction circuit 11 that determines whether or not it is necessary to perform correction based on the output of the comparison circuit 7, and the correction circuit 1.
When it is determined that the correction needs to be performed by 1, the trigger circuit 12 that outputs the monitor signal for triggering the change of the potential of the potential changing unit 20 by the operation thereof.
And a correction data circuit 13 that obtains a change amount of the potential to be changed as correction data and outputs a read signal.

The semiconductor circuit system according to the third embodiment shown in FIG. 3 differs from the second embodiment shown in FIG. 2 in that the trigger circuit 12 and the correction data circuit 1 of the correction means 10 are different.
The output of 3 is once taken out as a monitor signal and a read signal, processed by a control circuit or the like (not shown), and then supplied again to the potential changing means 20 as a rewriting signal. Due to such a difference in configuration, the configuration of the potential changing means 20 is also slightly different from that of the circuit system of the second embodiment.

That is, the potential changing means 20 is, for example, a regulator control register 23 to which the rewriting signal output from an external control signal is supplied, and a regulator with a potential adjusting circuit to which the output of the control register 23 is supplied. And 23. The regulator 21 with a potential adjusting circuit is rewritten, for example, by an external control circuit based on the monitor signal output from the trigger circuit 12 of the correction means 10 and the read signal output from the correction data output circuit 13. A signal is supplied via the regulator control register 23, and the operating potential supplied via the power input terminal 8 is adjusted.

Similarly to the circuit system according to the second embodiment, the semiconductor circuit system according to the third embodiment shown in FIG. 3 corrects data by the ECC circuit 51 during product operation.
Alternatively, when a memory data read error is confirmed, this data correction operation or error confirmation operation triggers the ECC error correction operation, and the potential is raised or lowered based on the contents of the data read error. The direction of potential change is determined, and a monitor signal and a read signal are output to the outside of the chip, for example, an external control circuit generates a rewrite signal and outputs the rewrite signal to the potential changing means 20, thereby generating a potential as an operating power supply. The potential of the regulator provided for fixing or adjustment is adjusted by software.

In the semiconductor circuit system according to the third embodiment described above, the two outputs of the correction means 10 are once taken out to the outside for signal processing, and a rewrite signal as a control signal is generated outside to generate the potential adjusting means 20. However, the present invention is not limited to this, and the rewrite signal as the control signal may be generated by the control means mounted on the chip of the one-chip microcomputer 1 as an internal element. . As a specific example of such a configuration, there is a semiconductor circuit system according to the fourth embodiment shown in FIG.

The semiconductor circuit system according to the fourth embodiment shown in FIG. 4 has basically the same configuration as the circuit system according to the third embodiment shown in FIG. That is, the non-volatile memory 5 having the ECC circuit 51, the defect detection means 6 having the comparison circuit 7, the correction circuit 11, the trigger circuit 12, and the correction means 1 having the correction data circuit 13.
0 and a potential changing means 20 having a regulator 21 with a potential adjusting circuit and a regulator control register 23 are basically provided. The characteristic configuration of the fourth embodiment is
The control means 30 receives the monitor signal output from the trigger circuit 12 of the correction means 10 and the read signal output from the correction data circuit 13, generates a rewrite signal as a control signal, and outputs the rewrite signal to the regulator control register 23. It is mounted on the chip of the one-chip microcomputer 1.

The semiconductor circuit system according to the fourth embodiment configured as described above can also obtain the same operation and effect as the circuit system according to the third embodiment shown in FIG. The control circuit 30 is provided in the chip, and an output terminal for taking out the monitor signal and the read signal from the control means 30 is provided outside the chip so that the monitor signal and the read signal are taken out. Is also good.

In each of the semiconductor circuit systems according to the second to fourth embodiments described above, a read error of data from the nonvolatile memory 5 is confirmed, and the read potential is adjusted after grasping the content of the error. Although the read error is corrected by the above, the present invention is not limited to this, and the error data portion is automatically overwritten with the corrected data by confirming the content of the data read error and its address. Such a configuration is also possible. A specific example of this is the semiconductor circuit system according to the fifth embodiment shown in FIG. 5 and the sixth embodiment shown in FIG.

First, a semiconductor circuit system according to the fifth embodiment of the present invention shown in FIG. 5 will be described. 5, the one-chip microcomputer 1 has a nonvolatile memory 5 including an ECC circuit 51, a defect detecting means 6 including a comparing circuit 7, a correction circuit 11, a trigger circuit 12, and a correction circuit, as in FIGS. Correction means 1 having data circuit 13
0 and the potential changing means 20 are basically provided. The potential changing means 20 includes an E in addition to the normal regulator 22.
When data correction by the CC circuit 51 is performed, the correction operation is used as a trigger to confirm the contents of the data read error and the cell address, and the error data portion is automatically overwritten with the corrected data. 24 are provided. The point that the cell rewriting circuit 24 is provided is a structural feature of the semiconductor circuit system according to the fifth embodiment.

In the semiconductor circuit system according to the fifth embodiment, when the data correction by the ECC circuit 51, that is, the memory data read error is confirmed during the product operation, the data correction operation is a trigger, The cell rewriting circuit 24 automatically overwrites the corrected data in the error data portion by confirming the contents of the data read error and the cell address.

According to the semiconductor circuit system of the fifth embodiment, like the circuit systems of the second to fourth embodiments, the read potential is changed with respect to the data read failure, and the threshold level is simply adjusted. It is possible to prevent further data retention in the subsequent data read by specifying the address of the data in which the data retention is occurring and overwriting the data. It has the unique effect of

In the semiconductor circuit system according to the fifth embodiment, the monitor signal output from the trigger circuit 12 constituting the correction means 10 and the read signal output from the correction data circuit 13 are directly supplied to the cell rewriting circuit 24. The address of the defective cell and the data correction are supplied to the cell rewriting circuit 24 and the ECC in the memory 5.
The circuit 51 and the circuit 51 have been described above, but the present invention is not limited to this and may be configured as the semiconductor circuit system according to the sixth embodiment shown in FIG.

That is, in the circuit system according to the sixth embodiment shown in FIG. 6, the monitor signal output from the trigger circuit 12 of the correcting means 10 is input to specify the address of the defective cell. An address control circuit 31 for outputting a control signal is provided, and by using this control circuit 31, the address of the cell in which the data read defect has occurred is specified to the cell rewrite circuit 24. In addition to specifying the address, the correction data of the correction data circuit 13 is used to rewrite the data of the defective cell in the memory 5.

With the above configuration, the address control circuit 31 can be used to specify the address of the cell in which data retention occurs and overwrite the correction data, and the same effect as the fifth embodiment. Can be achieved. Note that, also in the circuit system according to the sixth embodiment, similarly to the system according to the fourth embodiment, a terminal for taking out the output of the address control circuit 31 to the outside of the chip 1 may be provided. With this configuration, the address of the memory cell in which the data retention occurs can be used as the external data.

[0038]

As described above in detail, according to the semiconductor circuit system of the present invention, the defect detecting means for detecting the read defect of the non-volatile memory due to the data retention, and the deteriorated read potential are normally detected. Since the correction means for generating the correction data for correcting the above data and the potential changing means for changing the potential level of the operating power supply based on the correction data are provided, the read failure due to the data retention after the shipment is prevented. Even if it occurs, it can be dealt with by changing the operating potential level, and the data retention read failure after shipping can be reduced.

Further, it is possible to reduce the screening process for defect revision based on the data retention at the time of the shipping test, and it is possible to omit extra checking work at the time of shipping. The data retention in this case refers to an initial selection process when the cell potential gradually drops.

As described above, since the test process can be reduced, the test cost can be kept low.
This also has the effect of reducing the overall cost in manufacturing a semiconductor circuit system such as a one-chip microcomputer. This makes it possible to provide an inexpensive semiconductor circuit system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor circuit system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a semiconductor circuit system according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a semiconductor circuit system according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of a semiconductor circuit system according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a semiconductor circuit system according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a schematic configuration of a semiconductor circuit system according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a conventional semiconductor circuit system.

[Explanation of symbols]

1 One-chip microcomputer 3 data bus 4 Microcomputer control signal bus 5 Non-volatile memory 51 ECC circuit 6 Failure detection means 7 Comparison circuit 8 Power input terminal 10 Correction means 11 Correction circuit 12 Trigger circuit 13 Correction data circuit 20 Potential changing means 21 Regulator with potential adjustment circuit 22 Regulator 23 Regulator Control Register 24 cell rewriting circuit 30 control means 31 Address control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 16/06 G11C 17/00 632C 632Z 639C F term (reference) 5B025 AA01 AD09 AD13 AD16 AE08 AE09 5B062 CC01 HH04 JJ06 5L106 AA10 BB12 CC24 DD25 FF05 GG05

Claims (5)

[Claims] 1. A non-volatile memory built in a one-chip microcomputer and having stored data read by an operating power supply controlled by a power supply control circuit and having a possibility of data retention as a cause of failure. Defect detection means for detecting a read failure of the nonvolatile memory caused by the data retention, and correction for generating correction data for correcting a deteriorated read potential to normal data when the read failure is detected. Means for changing the potential level of the operating power supply on the basis of the correction data, and a semiconductor circuit system. 2. The non-volatile memory has a function of controlling its operating power supply by a regulator as the power supply control circuit, and a data correction for reading and reading memory data by an error correction code circuit to confirm and correct an error in the data. And a defect detection unit that detects a read defect caused by retention of the memory data during operation of the error correction code circuit, and the correction unit and the potential change unit. The semiconductor circuit system according to claim 1, wherein the corrected potential is corrected as normal data by automatically changing the potential level of the regulator. 3. The non-volatile memory has a function of controlling an operating power supply by a regulator as the power supply control circuit, and a data correction for reading and correcting memory data by an error correction coding circuit to confirm and correct an error in the data. And a built-in one-chip microcomputer having a function, the failure analysis unit senses a read failure due to retention of the memory data during operation of the error correction code circuit, and the correction unit outputs a signal to the outside. 2. The semiconductor circuit system according to claim 1, wherein the potential generated by the correcting means is corrected as normal data by changing the potential level of the regulator by software. 4. The non-volatile memory has a function of controlling its operating power supply by a regulator as the power supply control circuit, and a data correction for reading memory data by an error correction code circuit and confirming / correcting an error in the data. And a failure analysis unit that detects a read failure caused by retention of the memory data during operation of the error correction code circuit, and the correction unit and the potential change unit. By setting an operation execution flag of the error correction code circuit in a built-in register or a built-in memory and changing the potential level of the regulator by software when the operation execution flag of the error correction code circuit is detected by software. , Claims for correcting deteriorated potential as normal data The semiconductor circuit system according to 1. 5. The non-volatile memory has a function of controlling its operating power supply by a regulator as the power supply control circuit, and a data correction for reading memory data by an error correction code circuit and confirming / correcting an error in the data. And a failure analysis unit that detects a read failure caused by retention of the memory data during operation of the error correction code circuit, and the correction unit and the potential change unit. 2. The semiconductor circuit system according to claim 1, wherein the corrected potential is corrected as normal data by overwriting the data on the error address with the data corrected by the error correction code circuit.