JP2003100077A - Boosting potential generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a boosting voltage generating circuit in which of reduction of supply capability of a compensation current caused by a counter flow of a current is not caused. SOLUTION: Timing and phases of a signal XX2 and a signal YY3, timing and phases of a signal YY2 and a signal XX3 are adjusted and set by a timing circuit, a logic value of the signal YY3 is made 'L' and a logic value of the signal XX2 is made 'L' always, a logic value of the signal XX3 is made 'L' and a logic value of the signal YY2 is made 'L' always, and the reduction of current supply capability caused by the occurrence of a counter flow current to a charge pump circuit 8 from an output terminal 'to' is prevented. Therefore, current supply capability can be improved more than conventional ones by using capacitors C11-C14 of the prescribed capacity without increasing occupancy area of a capacity, the reduction of occupancy area of capacitors can be performed to satisfy conventional current supply capability, further, the capacity of the capacitors C11-C14 can be increased and high current supply capability can be provided without causing a counter flow current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boosted potential generating circuit,
In particular, it relates to a boosted potential generation circuit including a charge pump circuit.

[0002]

2. Description of the Related Art A boosted potential generating circuit (Vpp circuit) for supplying a boosted voltage higher than a power supply voltage is used in various electronic devices such as a DRAM (Dynamic Random Acc).
essMemory), and in this case, when the output voltage Vpp of the boosted potential generation circuit is used as a drive signal for the word line of the DRAM, the N-type MO of the memory cell is
The high level voltage Vd of the data line can be written in the memory cell at the time of writing without being affected by the threshold voltage Vth of the S transistor (hereinafter abbreviated as NMOS), and a sufficient signal can be obtained at the time of reading. The voltage can be taken out on the data line. Further, when the boosted potential generating circuit is applied to the data output circuit of the DRAM, the output voltage Vpp of the boosted potential generating circuit is applied to the gate of the NMOS of the data output circuit, which causes a loss of the threshold voltage Vth of the NMOS. By suppressing the decrease in the charging speed, the load driving capability of the data output circuit can be improved.

The boosted potential generating circuit 18 of this type is shown in FIG.
As shown in, a Vpp detection circuit 20 for detecting the output voltage Vpp is provided, and this Vpp detection circuit 20 causes
When a decrease in the boosted potential from a preset reference value is detected, the operation clock generation circuit 21 connected to the Vpp detection circuit 20 causes the drive signal Fd from the Vpp detection circuit 20.
Is entered. The operation clock CLK is supplied from the operation clock generation circuit 21 driven by the drive signal Fd to the charge pump circuit 10 connected to the operation clock generation circuit 21, and the operation clock CL is input.
Based on K, the charge pump circuit 10 performs a boosting operation on the output voltage of the boosted potential generating circuit 18, and the boosted potential generating circuit 18 outputs the boosted output voltage.

A case where the boosted potential generating circuit 18 is applied to the DRAM 7 will be described with reference to FIG.
M7 is provided with a memory cell array 27 in which memory cells for writing and reading data are arranged in a matrix, and a sense amplifier 28 is connected to the memory cell array 27. This sense amplifier 28 amplifies a weak read signal from the memory cell array 27 to a logic level with high quality, and also senses the memory cell array 27.
In order to perform high-quality writing with respect to, the sense amplifier 28 has a function of performing signal processing of a write signal in a high SN state, and a data input circuit 29 and a data output circuit 30 are connected to the sense amplifier 28. ing. In addition, the memory cell array 2
Reference numeral 7 denotes an X decoder 31 which inputs a selection signal of a word line WL which is a selection line in a row direction, and a Y decoder 32 which inputs a selection signal of a bit line BL (also called a data line) which is a selection line in a column direction. Are connected to each other, and the control circuit 33 for controlling the operation of the DRAM 7 is connected to the X decoder 3
1, the Y decoder 32, the data input circuit 29, and the data output circuit 30, and the boosted potential generation circuit 18 is connected to the X decoder 31.

A conventional charge pump circuit is shown in FIG.
A charge pump circuit 22 as shown in FIG. 7 is used, and a timing circuit 23 as shown in FIG. 7 is connected to the charge pump circuit 22. In the timing circuit 23 shown in FIG. 7, the NOT gate 24 is provided between the input terminal of the operation clock CLK and the output terminal of the signal A1.
a and 24b are connected in series with each other, and the operation clock CL
NOT gates 24g, 24d, and 24e are connected in series between the K input terminal and the signal B1 output terminal. Therefore, as shown in FIGS. 8A, 8B, and 8C, the signal A1 is changed with respect to the logical value of the operation clock CLK.
And the signal B1 are always output as signals having opposite phases.

Further, between the input terminal of the operation clock CLK and the output terminal of the signal A2, a level shift circuit 25a and N are provided.
The OT gates 24c are connected in series with each other, and NO is provided between the input terminal of the operation clock CLK and the output terminal of the signal B2.
The T gate 24g, the level shift circuit 25b, and the NOT gate 24f are connected in series. Therefore, as shown in FIGS. 8A, 8D, and 8E, the signal A2 and the signal B2 are always output as signals having opposite phases with respect to the logical value of the operation clock CLK. .

By the way, as shown in FIG. 6, the charge pump circuit 22 is composed of a first charge pump circuit 22a and a second charge pump circuit 22b which are basically the same in configuration, and the first charge pump circuit 22b Pump circuit 22a
Includes transistors Tr11, Tr12, Tr13 and capacitors C11, C12. The second charge pump circuit 22b includes transistors Tr14, Tr15, Tr12.
16, the first charge pump circuit 22a is driven by the inputs of the signals A1, A2, B1, and the second charge pump circuit 22b is connected to the signal A.
It is configured to be driven by 1, B1 and B2 inputs.

In the first charge pump circuit 22a of the charge pump circuit 22, when the logic value of the operation clock CLK is "L", the logic value of the signal B1 becomes "H" and the potential Vn1 of the node n1 rises. Therefore, the transistor Tr12 is turned on and the transistor Tr12 is turned on.
The potential Vn2 of the node n2 becomes Vcc by becoming N.
Becomes At this time, the logic value of the signal A1 becomes "L" and the logic value of the signal A2 becomes "H", so that the transistor Tr1
3 is OFF. Operation clock C from this state
When the logic value of LK becomes “H”, the logic value of the signal B1 becomes “L”, the transistor Tr12 is turned off, and the logic value of the signal A1 becomes “H”.
The potential Vn2 of 2 is boosted to Vcc + β, and the logical value of the signal A2 becomes “L”.
N, the compensation current is output from the node n2 through the output terminal to, and the compensation voltage for compensating the decrease in the drive voltage is supplied to the DRAM 7 based on this compensation current, and the compensated drive voltage is supplied to the X decoder 31. Selected word line WL
Is supplied to.

On the other hand, in the second charge pump circuit 22b of the charge pump circuit 22, the operation clock CL
When the logical value of K is "L", the logical value of the signal A1 is "L", the potential Vn3 of the node n3 is lowered, the transistor Tr15 is turned off, and the logical value of the signal B1 is "H". Therefore, the potential Vn4 of the node n4 is boosted to Vcc + β. At this time, since the logical value of the signal B2 becomes "L", the transistor Tr16 is turned on, a compensation current is output from the node n4 through the output terminal to, and the driving voltage of the driving voltage is supplied to the DRAM 7 based on the compensation current. A compensation voltage that compensates for the decrease is supplied, and the compensated drive voltage is supplied to the word line WL selected by the X decoder 31. When the logic value of the operation clock CLK becomes "H" from this state, the logic value of the signal A1 becomes "H", the transistor Tr15 is turned on, and the logic value of the signal B1 becomes "L". Since the potential Vn4 of n4 drops to Vcc and the logical value of the signal B2 becomes "H", the transistor Tr16 is turned off, and the compensation current is output from the second charge pump circuit 22b via the output terminal to. There is no such thing.

In this way, when the Vpp detection circuit 20 detects that the boosted potential is lower than the reference value, the operation clock CLK from the operation clock generation circuit 21 becomes
When the logic value of the operation clock CLK is input to the operation clock input terminal of the timing circuit 23 and changes from “L” to “H”, the first charge pump circuit 22a outputs a compensation current via the output terminal to. Based on this compensation current, a compensation voltage for compensating the decrease in drive voltage is supplied to the DRAM 7. Then, when the logical value of the operation clock CLK changes from “H” to “L”, the second charge pump circuit 22b outputs a compensation current via the output terminal to, and the DRAM 7 is based on this compensation current. Since the compensating voltage for compensating the decrease in the driving voltage is supplied, the compensating current supplied from the charge pump circuit 22 efficiently compensates for the decrease in the boosted potential at the leading edge position and the trailing edge position of the operation clock CLK. It

[0011]

In the above-described conventional charge pump circuit 22, capacitors C11, C12, C1 are provided in order to improve the current supply capacity of the compensation current.
When the capacitances of C3 and C14 are increased, the load capacitances C12 and C13 of the signal A1 and the load capacitance C of the signal B1 in FIG.
11 and C14 increase, and the operation clock CL
With respect to K, the signals A1 and B1 are delayed as compared with the cases of FIGS. 8B and 8C, as shown in FIGS. 9B and 9C. Therefore, in the first charge pump circuit 22a, the logic value of the signal A2 becomes "L" when the logic value of the signal B1 is "H", as shown in FIGS. 9C and 9D. A period occurs, and the transistors Tr12 and Tr13 both become O.
As a result, the reverse current Ia shown in FIG. 9 (j) and shown by the dotted line in FIG. 6 may flow from the output terminal to into the first charge pump circuit 22a. There is a problem that the current supply capacity of the circuit 22 is lowered.

Similarly, the second charge pump circuit 2
2b, as shown in FIGS. 9 (c) and 9 (d), the signal A1
When the logical value of is "H", a period in which the logical value of the signal B2 is "L" occurs, both transistors Tr15 and Tr16 are turned on, and the output terminal to the second charge pump circuit 22b, The reverse current Ib shown in FIG. 9 (j) and shown by the dotted line in FIG. 6 may flow, and this reverse current Ib may flow.
This causes a problem that the current supply capacity of the charge pump circuit 22 is reduced.

The present invention has been made in view of the current state of the operation of the boosted potential generating circuit of this type as described above.
It is an object of the present invention to provide a boosted potential generation circuit in which the compensation current supply capability is not deteriorated due to reverse current flow.

[0014]

In order to achieve the above object, the invention according to claim 1 applies a predetermined drive voltage to an electronic element and detects a decrease in the drive voltage applied to the electronic element. An operation clock from an operation clock generation circuit is supplied to a charge pump circuit including a capacitance element, and the capacitance element is charged based on the operation clock, so that the charge pump circuit outputs from the charge pump circuit via an output terminal. A boosted potential generation circuit that supplies a compensation signal for compensating for a decrease in the driving voltage to an electronic element, the boosted potential generation circuit being generated based on an increase in the capacitance value of the capacitance element and flowing from the output terminal into the charge pump circuit. It is characterized in that it has an operation timing circuit for preventing current by controlling the timing of the drive signal of the charge pump circuit.

According to such means, a predetermined drive voltage is applied to the electronic element to execute the operation of the electronic element, and the operation clock generating circuit is driven by the detection of the decrease in the drive voltage to the electronic element, thereby operating. The operation clock from the clock generation circuit is supplied to the charge pump circuit including the capacitance element, and the capacitance element of the charge pump circuit is charged on the basis of the operation clock, so that the output terminal is output from the charge pump circuit. A compensation signal for compensating for the decrease in the driving voltage is supplied to the electronic device via the compensation signal. In this case, a backflow current that is generated due to an increase in the capacitance value of the capacitive element and flows into the charge pump circuit from the output terminal is prevented by controlling the timing of the drive signal of the charge pump circuit by the operation timing circuit, and Compensation signals are supplied by using the capacitor element with a current supply capacity that is significantly improved compared to the conventional one, without increasing the occupied area of the capacitor element, and the same current supply capacity as the conventional one can be achieved. This is realized by reducing the area occupied by the capacitive element, and further, by increasing the capacitance of the capacitive element without generating a backflow current, the high current supply capability is significantly improved.

[0016] Similarly, in order to achieve the above object, the invention according to claim 2 is the invention according to claim 1, wherein the charge pump circuit has a logical value "L" of the operation clock.
And a first charge pump circuit for supplying the compensation signal when the logical value changes from "H" to a logical value "H", and a supply of the compensation signal when the logical value "H" of the operating clock changes to a logical value "L". It is characterized by comprising a second charge pump circuit for performing.

According to such means, in addition to the operation of the invention according to claim 1, in the charge pump circuit, when the operation clock changes from the logical value "L" to the logical value "H", the first A compensation signal is supplied from the charge pump circuit, and the logic value "H" to the logic value "L" of the operation clock is supplied.
The second charge pump circuit supplies the compensating signal at the time of the change to, and the compensating signal is efficiently supplied at the leading edge position and the trailing edge position of the operation clock.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to a DRAM will be described below with reference to FIGS. 1 is a circuit diagram showing a configuration of a charge pumping circuit according to the present embodiment, FIG. 2 is a circuit diagram showing a configuration of a timing setting circuit for setting a timing of a signal for driving the charge pumping circuit of FIG. 1, and FIG. 6 is a time chart showing the operation of the embodiment.

The charge pump circuit of the present embodiment includes
A charge pump circuit 8 as shown in FIG. 1 is used, and the charge pump circuit 8 is connected with timing circuits 15a and 15b having the configurations as shown in FIGS. 2 (a) and 2 (b). In the timing circuit 15a shown in FIG. 2A, the NAND gate 12b and the NOT gate 11 are provided between the input terminal of the operation clock CLK and the output terminal of the signal X.
A serial connection circuit of j and the NOT gate 11k is provided, and an output terminal of the signal X is provided at the output terminal of the NOT gate 11k. Further, the NOT gate 11g is connected between the first input terminal of the NAND gate 12b and the input terminal of the operation clock CLK, and the NAND gate 12b is connected.
Between the second input terminal and the input terminal of the operation clock CLK, the NOT gates 11a to 11d to be the delay circuit 13 are formed.
And the NOT gate 11f are connected in series with each other. Then, the input terminal of the operation clock CLK is connected to the first input terminal of the NAND gate 12a, and the NOT gates 11h and 11i are connected in series between the output terminal of the NAND gate 12a and the output terminal of the signal Y. The output terminal of the gate 11d is connected to the second input terminal of the NAND gate 12a.

The timing circuit 1 shown in FIG.
In 5b, the NOT gates 11l and 11m are connected in series between the input terminal of the signal X and the output terminal of the signal XX1, and the NOT gate 11n is connected between the input terminal of the signal X and the output terminal of the signal XX2. Between the input terminal of the signal X and the output terminal of the signal XX3, the level shift circuit 16, N
The OT gate 11p and the NOT gate 11q are connected in series with each other. Furthermore, the signal Y input terminal and the signal Y
The NOT gates 11r and 11s are connected in series between the output terminals of Y1 and the NOT gate 11t is connected between the input terminal of the signal Y and the output terminal of the signal YY2.
Of the level shift circuit 17, the NOT gate 11u, and the NOT gate 11v between the input terminal and the output terminal of the signal YY3.
Are connected in series with each other.

On the other hand, the charge pump circuit 8 of the present embodiment, as shown in FIG. 1, comprises a first charge pump circuit 8a and a second charge pump circuit 8b which are basically the same in configuration. , The first charge pump circuit 8a
Includes transistors Tr1, Tr2, Tr3 and capacitors C1, C2, and the second charge pump circuit 8b is
Transistors Tr4, Tr5, Tr6, capacitor C
3 and C4, the first charge pump circuit 8a is driven by the inputs of the signals XX2, XX1, YY3, and the second charge pump circuit 8b is the signals YY2, YY1, XX3.
Is configured to be driven by the input of.

The operation of this embodiment having such a configuration will be described. In this embodiment, the operation clock CLK is first input to the timing circuit 15a shown in FIG. 2A, and when the logic value of the operation clock CLK is “L”,
The logical value of the output signal of the NAND gate 12b is "L",
The logic value of the signal X becomes "L", and the NAND gate 12a
The output signal has a logical value "H", and the signal Y has a logical value "H". From this state, the operation clock CL
When the logical value of K becomes "H", the logical value of the output signal of the NAND gate 12b immediately becomes "H", and accordingly the logical value of the signal X becomes "H". However, since the output signal of the NAND gate 12a does not immediately change to the logical value "L" and maintains the logical value "H", the logical value of the signal Y remains "H" and the NOT gates 11a to 11d operate. After the delay time set by the configured delay circuit 13, the NAN
The output signal of the D gate 12a becomes a logical value "L", and the logical value of the signal XY2 becomes "L". At this time, the logic value of the signal at the second input terminal of the NAND gate 12b changes to "L", but the logic value of the output signal of the NAND gate 12b maintains "H" and the logic value of the signal X becomes "L". It remains H ”. In this way, the operation clock C shown in FIG.
Based on LK, the signal X shown in FIG. 7B is output as an in-phase signal, but the delayed clock CLK delayed from the operation clock CLK as shown in FIG.
Based on (d), the signal Y shown in (d) of the same figure is output as a signal with a reverse phase, and the signal Y is output with a delay in a reverse phase with respect to the signal X.

Since these signals X and Y are input to the timing circuit 15b, the signal XX1 is in phase with the signal X and the signal X
X2 has the opposite phase to signal X, signal XX3 has the same phase as signal X and is level-shifted, and signal YY1 has signal Y.
In-phase with respect to the signal X, a signal delayed in a reverse phase for a predetermined time, signal YY2 with a reverse phase with respect to the signal Y, with respect to the signal X delayed in-phase with a predetermined time, and a signal YY
3 is a signal that is level-shifted in phase with the signal Y and is the signal X
, The signal is delayed in phase by a predetermined time and is level-shifted.

In the present embodiment, the charge pump circuit 8
In the first charge pump circuit 8a, when the logical value of the operation clock CLK is “L”, the logical value of the signal X becomes “L”, so the logical value of the signal XX2 becomes “H”, The potential Vn1 of n1 rises and the transistor T
By turning on r2 and turning on the transistor Tr2, the potential Vn2 of the node n2 becomes Vcc. At this time, the logic value of the signal XX1 becomes "L", the logic value of the signal Y becomes "H", and the logic value of the signal YY3 becomes "H".
The transistor Tr3 is off.

When the logic value of the operation clock CLK becomes "H" from this state, the logic value of the signal XX2 becomes "L", so that the transistor Tr2 is turned off and the signal XX.
Since the logical value of 1 becomes "H", the potential Vn of the node n2
2 is boosted to Vcc + β and the logical value of the signal YY3 becomes “L”, so that the transistor Tr3 is turned on and a compensation current is output from the node n2 via the output terminal to, and the DRAM 7 is based on this compensation current. To the word line WL selected by the X decoder 31.

On the other hand, in the second charge pump circuit 8b of the charge pump circuit 8, when the logic value of the operation clock CLK is "L", the logic value of the signal Y becomes "H", so that the signal YY2 of the signal YY2. The logical value is "L", and the node n
The potential Vn3 of 3 decreases and the transistor Tr5 turns off.
And the logical value of the signal YY1 becomes “H”, so that the potential Vn4 of the node n4 is boosted to Vcc + β. At this time, since the logic value of the signal X is “L” and the logic value of the signal XX3 is “L”, the transistor Tr6 is turned on,
A compensation current is output from the node n4 via the output terminal to, and based on this compensation current, a compensation voltage for compensating the decrease in the driving voltage is supplied to the DRAM 7, and the compensated driving voltage is the word selected by the X decoder 31. It is supplied to the line WL.

When the logical value of the operation clock CLK becomes "H" from this state, the logical value of the signal Y becomes "L" and the logical value of the signal YY2 becomes "H", so that the transistor Tr5 is turned on. , The logical value of the signal YY1 becomes “L”, the potential Vn4 of the node n4 drops to Vcc,
At this time, the logic value of the signal X becomes "H" and the logic value of the signal XX3 becomes "H", so that the transistor Tr6 is turned off.
F, the compensation current is not output from the second charge pump circuit 7b via the output terminal to.

In this way, in the present embodiment, as shown in FIG.
In the following description, the Vpp detection circuit 20
When the decrease in the boosted potential from the reference value is detected, the operation clock CLK is output from the operation clock generation circuit 21 as shown in FIG.
When the logic value of the operation clock CLK is input to the operation clock input terminal of the timing circuit 15a of (a) and changes from "L" to "H", compensation is performed from the first charge pump circuit 8a via the output terminal to. A current is output, a compensation voltage for compensating for a decrease in driving voltage is supplied to the DRAM 7 based on this compensation current, and when the logical value of the operation clock CLK changes from “H” to “L”, the second charge pump A compensating current is output from the circuit 8b via the output terminal to, and based on this compensating current, a compensating voltage for compensating the decrease of the driving voltage is supplied to the DRAM 7, and the operating clock C
At the leading edge and the trailing edge of LK, the reduction of the driving voltage is efficiently compensated by the compensation current supplied from the charge pump circuit 8.

In the present embodiment, during the above-described drive voltage compensation operation, the in-phase signal X and the signal X in the opposite phase to the signal X delayed by a predetermined time are generated based on the operation clock CLK, and the X signal is generated. Based on the in-phase signals XX1, XX
The signal XX2 having a phase opposite to that of the signal 3 is generated based on the Y signal, and the signals YY1 and YY3 having a phase opposite to that of the signal YY2 having the same phase are generated.
In the charge pump circuit 8a of
Corresponding to the logical value "H" of LK, the logical value of the signal Y becomes "L" and the logical value of the signal YY3 becomes "L".
When the transistor Tr3 is turned on, the signal X is always output.
Since the logical value of is "H" and the logical value of the signal XX2 is "L", the transistor Tr2 is turned off, and the transistor Tr2 is turned off, as shown in FIG.
At the position indicated by the dotted line, a reverse current does not occur from the output terminal to into the first charge pump circuit 8a unlike the conventional case. Similarly, the second charge pump circuit 8
In b, the logic value of the signal X becomes "L" corresponding to the logic value "L" of the operation clock CLK, and the signal XX3
The logical value of is "L", and the transistor Tr6 is turned on.
, The logic value of the signal Y is always “H” and the signal Y is
Since the logical value of Y2 is "L", the transistor Tr5
Is turned off, and no reverse current flows from the output terminal to into the second charge pump circuit 8b.

As described above, according to the present embodiment, the timing circuit sets the timing and phase of the signal XX2 and the signal YY3 and the timing and phase of the signal YY2 and the signal XX3. When the value is "L", the logical value of the signal XX2 is always "L",
When the logic value of the signal XX3 is "L", the logic value of the signal YY2 is always "L". Therefore, it is completely prevented that the backflow current is generated and the current supply capability of the charge pump circuit 8 is deteriorated. It Therefore, according to the present embodiment, the capacitors C11 to C14 having a predetermined capacity are used to supply the compensation current with a current supply capacity which is significantly improved as compared with the conventional one, and the area occupied by the capacitors is increased. If the same current supply capacity as the conventional one is satisfied, the area occupied by the capacitor can be significantly reduced. Furthermore, according to the present embodiment, the capacitors C11 to C14 can be generated without generating a reverse current.
It is also possible to provide a boosted potential generating circuit having a high compensation current supply capability by increasing the capacity of the above.

[0031]

According to the boosted potential generating circuit of the first aspect of the present invention, a predetermined driving voltage is applied to the electronic element, the operation of the electronic element is executed, and the decrease in the driving voltage to the electronic element is detected. The operation clock generation circuit is driven, the operation clock from the operation clock generation circuit is supplied to the charge pump circuit including the capacitance element, and the capacitance element of the charge pump circuit is charged based on the operation clock. From the charge pump circuit, a compensating signal for compensating the decrease in driving voltage is supplied to the electronic element via the output terminal. In this case, the backflow current that is generated based on the increase of the capacitance value of the capacitive element and flows into the charge pump circuit from the output terminal is prevented by the operation timing circuit controlling the timing of the drive signal of the charge pump circuit. It is possible to supply a compensation signal with a current supply capacity that is significantly improved compared to the past by using a capacitive element with the same capacitance, without increasing the occupied area of the capacitive element, and with the same current as before. The supply capacity can be realized by reducing the occupied area of the capacitive element, and by increasing the capacity of the capacitive element without generating a reverse current, it is possible to significantly improve the high current supply capacity. .

According to the invention of claim 2, in addition to the effect obtained by the invention of claim 1, in the charge pump circuit, when the logical value "L" of the operation clock changes from the logical value "H", The compensation signal is supplied from the first charge pump circuit, and the compensation signal is supplied from the second charge pump circuit when the logical value "H" of the operating clock changes to the logical value "L". It is possible to efficiently supply the compensation signal at the leading edge position and the trailing edge position of the operation clock.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a charge pumping circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a timing setting circuit that sets the timing of a signal that drives the charge pumping circuit of FIG.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing an overall configuration when a boosted potential generation circuit is applied to a DRAM.

FIG. 5 is a block diagram showing an overall configuration of a boosted potential generation circuit.

FIG. 6 is a circuit diagram showing a configuration of a charge pumping circuit in a conventional boosted potential generation circuit.

7 is a circuit diagram showing a configuration of a timing setting circuit for setting the timing of a signal for driving the charge pumping circuit of FIG.

FIG. 8 is a time chart explaining a normal operation of a conventional boosted potential generation circuit.

FIG. 9 is a time chart explaining an abnormal operation of a conventional boosted potential generation circuit.

[Explanation of symbols]

7 ... DRAM, 8 ... Charge pump circuit, 11a ...
11k ... NOT gate, 12a, 12b ... NAND
Gate, 13 ... Delay circuit, 15a, 15b ... Timing circuit, 16, 17 ... Level shift circuit, 18 ...
Boosted potential generation circuit.

Continued front page    F-term (reference) 5F038 BG05 BG06 CD06 DF05 EZ20                 5H730 AA14 AS04 BB02 BB57 BB88                       DD04 FG01                 5M024 AA24 BB29 BB33 BB34 BB35                       BB36 FF03 FF13 FF22 FF25                       GG01 HH11

Claims (2)

[Claims] 1. When a predetermined drive voltage is applied to an electronic element and a decrease in the drive voltage applied to the electronic element is detected, an operation clock from a operation clock generation circuit is supplied to a charge pump circuit including a capacitive element. Then, by charging the capacitance element based on the operation clock, a boosted potential is generated from the charge pump circuit, which supplies a compensation signal for compensating for the decrease in the driving voltage to the electronic element via an output terminal. A circuit that prevents a reverse current that is generated based on an increase in the capacitance value of the capacitive element and flows into the charge pump circuit from the output terminal by controlling the timing of the drive signal of the charge pump circuit. A boosted potential generation circuit having a timing circuit. 2. The boosted potential generating circuit according to claim 1, wherein the charge pump circuit supplies the compensation signal when the logical value “L” of the operating clock changes to a logical value “H”. And a second charge pump circuit for supplying the compensation signal when the logical value "H" of the operating clock changes from the logical value "H" to the logical value "L".