JP2003099396A - Network interfacing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a network interface circuit by ASIC, in which the rise in cost is prevented by managing frame data and simplifying the circuit constitution. SOLUTION: In the network interface circuit loaded to an imaging apparatus, in which the network interface is integrated and ASIC designed to use a plurality of application functions with a system memory 9 as a shared resource, the ASIC is provided with MAC 1 for carrying out protocol control of a network 16, reception buffers 3 to 5 temporarily storing the frame data and a DMA controller part 6 controlling the reception buffers 3 to 5. In this case, the frame data stored to the reception buffers 3 to 5 are written into the system memory 9 via a DMA controller 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network interface circuit installed in an image forming apparatus such as a copying machine or a printer having a built-in network interface, or a multi-function peripheral having those functions.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional general ASIC.
(Application Specific Int
FIG. 3 is a block diagram of a system configuration example of a network interface circuit based on an Evolved Circuit. The network controller 23 uses the DMA (Di
Rect Memory Access) interface or PCI (Peripheral Comp)
One interface) bus interface and is connected to the system bus 20. The transmission / reception buffer 24 is connected to a general-purpose memory device (FIFO memory or the like) via a dedicated interface or built in the device. The network 26 side is connected via the PHY 25 and a transformer. The transmission / reception buffer 24 is dedicated to the network function. The CPU 21 controls the entire device.

A data frame sent from the network 26 passes through an address filter and temporarily stores the frame data addressed to itself in the transmission / reception buffer 24. At the same time, the built-in DMA controller requests the right to use the bus, and when the right is granted, the received data is transferred to the system memory 22.

[0004]

However, the conventional ASIC network interface as described above has the following problems. In a network such as Ethernet (registered trademark), data is received on a frame-by-frame basis, and therefore reception cannot be stopped in the middle of a frame. If the receiving operation is stopped for some reason, the frame data will be lost, and it is necessary to request the frame data again to the transmission source.

Therefore, the FI used for the receive buffer
As the capacity of the FO memory, a size of 1K to 2Kbyte or more is used. Further, the FIFO memory is managed on a frame-by-frame basis, and it is necessary to manage addresses and the like by the number of frames stored in the memory, so that the circuit configuration assumes the maximum number of frames.

That is, when a plurality of frames are stored in the memory, it is necessary to manage information such as address pointers by the number of frames. However, since the number of frames is not constant, it is necessary to construct a circuit assuming the maximum number. That is, since it becomes a complicated circuit, it becomes a factor of prolonging the development period of the ASIC, and further, if a large-scale reception buffer is incorporated, the cost of the ASIC is increased.

[0007] Recently, it has become possible to develop an ASIC having a plurality of functions by using a MAC core provided by an ASIC vendor, but the transmission / reception buffer is often connected to the outside of the ASIC. This is because it is difficult to incorporate a large-scale FIFO memory, but at the same time, there are physical problems such as complicated memory management and increase in I / O pins of the ASIC.

When the system memory of the image forming apparatus is shared with other functions, it is necessary to provide a corresponding transmission / reception buffer inside the ASIC. Otherwise, when other functions frequently use the system memory, transfer errors such as overflow of received data and underflow of transmitted data are likely to occur. However, as mentioned above, A
Providing outside the SIC increases I / O pins, while
Providing it inside the ASIC increases the gate size, resulting in a problem of increased manufacturing cost.

The present invention has been made in view of the above, and an object of the present invention is to provide a network interface circuit using ASIC, which simplifies the management of frame data and the circuit configuration, and avoids an increase in cost.

[0010]

In order to achieve the above object, a network interface circuit according to a first aspect of the present invention is mounted in an image forming apparatus having a built-in network interface and has a plurality of application functions as a system memory. A network interface circuit using an ASIC designed to utilize as a shared resource, the ASIC comprising: a MAC unit for performing protocol control of the network; a receiving block for temporarily storing frame data; A DMA controller for controlling a reception block,
The frame data stored in the reception buffer is written in the system memory via the controller.

According to the present invention, by writing the frame data stored in the reception buffer in the system memory via the DMA controller, it becomes possible to store only one frame in the memory block, and the frame management is performed. And the circuit configuration is simplified.

Further, in the network interface circuit according to a second aspect of the present invention, the reception block is further composed of a plurality of small-capacity reception buffers, and is provided with reception buffer control means for controlling the reception buffers. Is.

According to the present invention, the memory is made into a block of small-scale memory blocks, and each memory block stores only one frame, so that the reception buffer can be easily incorporated in the ASIC. It becomes possible to do.

In the network interface circuit according to a third aspect of the present invention, the receiving block is composed of three receiving buffers, and when receiving frame data, two receiving buffers are used and another receiving buffer is used. The buffer is always controlled in the standby state.

According to the present invention, when the receiving buffer is composed of two buffer blocks, it may happen that neither of the buffer blocks can be used and the receiving overrun easily occurs. The configuration and provision of a standby buffer allows new frames to be allocated to the standby buffer.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a network interface circuit according to the present invention will be described in detail below with reference to the accompanying drawings. The present invention is not limited to this embodiment.

The present invention realizes a network interface incorporated in various image forming apparatuses such as a digital copying machine, a printer, or a multi-functional peripheral for realizing functions such as copying, printing, and facsimile, and image processing and image output. , Has a plurality of application functions such as data communication, and each application function is equipped with an ASIC designed to be usable as a shared resource such as a memory and a hard disk. The specific configuration and operation will be described below.

FIG. 1 shows an AS according to an embodiment of the present invention.
It is a block diagram showing an example of composition of IC (network interface circuit). The network in this embodiment is 100 Mbps or 100 Mbps.
s Ethernet.

This ASIC is a MAC (Media Access) that executes network protocol control.
Control: medium access control unit 1 and MAC1
The receiving buffer control unit 2 connected to the receiving buffer control unit 3, the three receiving buffers 3 to 5 connected to the receiving buffer control unit 2, and the DMA control unit 6 connected to the receiving buffer control unit 2. The reception buffers 3 to 5 are, for example, small capacity FIFO (fist-i).
n first-out: first-in first-out buffer circuit)
It is composed of memory.

The MAC is a transmission control technique required for a LAN and performs access control for smooth joint use of a local cable and a plurality of nodes. That is, a link level communication function that does not depend on the type of transmission medium is realized. Frame assembly / disassembly, CSMA / for the transmission request and serial data received by the physical layer
Performs CD access control and the like.

The DMA control unit 6 is connected to the bus arbiter 7 that arbitrates between the DMA control units 11 and 12, and is indirectly connected to the system memory 9 via the memory control unit 8.

The reception buffer control section 2 controls the data management of the reception buffers 3 to 5, and also controls the data reception from the MAC 1 and the data transmission to the DMA control section 6.

This ASIC is a CP that controls the entire device.
PCI (Pe) that is connected to U12 and is a general-purpose bus
ripheral Component Interc
connected) bus 13 and local bus 14. Furthermore, this ASIC is based on PHY (physi
It is connected to the network 16 via a sublayer such as a cal layer protocol (physical layer protocol) 15.

The size of the reception buffers 3 to 5 is ASIC.
However, if the DMA transfer speed is sufficiently higher than the reception speed, the burst transfer size of DMA, for example, 32 bytes (total of 3 blocks is 96 bytes). However, there is no problem.

In many cases, the internal bus cannot be used preferentially in a multi-function ASIC having a built-in image processing function. However, since the configuration can be easily determined by calculating the reception buffer size from the maximum value of the bus acquisition interval, it is possible to deal with ASICs of any configuration.

Next, an example of optimization of the receiving buffer according to the present invention will be described with reference to FIG. Here, in the initial state, all reception blocks (reception buffers 3 to 5 in FIG. 1) are in an empty state. In addition,
In FIG. 2, the receiving buffers 3 to 5 in FIG. 1 are described as receiving buffers A, B, and C for convenience of explanation.
When a frame is received in this state, the receiving buffers A, B and C are stored in the order of priority.

It is now assumed that frame 1 is received. First, in the [state 1], the frame 1 is stored in the reception buffer A. Subsequently, in [state 2], when the reception buffer A becomes full, the frame 1 is continuously stored in the reception buffer B. At the same time, the DMA controller 6
The data is read from the reception buffer A and transferred to the system memory 9.

In [state 3], the network 16 has 100
In case of Mbps Ethernet, the maximum data storage speed in the receiving buffer is 12.5 Mbyte / sec.
Is. By setting the data transfer rate inside the ASIC to a higher rate, the receiving buffer A becomes empty before the receiving buffer B becomes full.

In [state 4], when the receiving buffer B becomes full, the frame 1 is stored in the receiving buffer A again.
At the same time, data transfer from the reception buffer B to the system memory 9 is started. In [states 1 to 4], the reception buffer C always waits for a new frame, and the reception operation itself is always performed by the two reception buffers.

In [state 5], when the reception of the frame 1 is completed and the next frame (frame 2) is sent, it is stored in the reception buffer C. This is the receive buffer A,
It does not depend on the state of B. If the reception buffers A and C were used in the reception of the previous frame, a new frame will be stored in the reception buffer B.

In [state 6], either the reception buffer A or the reception buffer B becomes empty before the reception buffer C becomes full. When the reception buffer C becomes full, an empty reception buffer is automatically selected. In the case of FIG. 1, the frame 2 is received by the reception buffers C and B.

By the way, when the receiving buffers 3 to 5 are composed of two buffer blocks, it may be impossible to use any of the buffer blocks when shifting to the above [state 4] to [state 5]. Although overrun is likely to occur, the configuration of three buffer blocks as shown in FIG. 1 makes it possible to easily avoid the occurrence of this problem.

As described above, the memory block including the receiving buffers 3 to 5 of about several tens of bytes, the control block for managing the memory block, the protocol control block of the network,
And a DMA control block, which is connected to the memory control block via an arbiter 7 inside the ASIC. Also, the DMA control block has 3
It suffices to prepare 3 blocks of about 2 bytes, and the reception buffer can be easily incorporated in the ASIC.

As described above, according to the present invention, the memory is not managed on a frame-by-frame basis, but a collection of small memory blocks (reception buffers 3 to
5), so that only one frame is stored in each memory block. This facilitates frame management and simplifies the circuit configuration. Further, in order to ensure stable data reception, it is sufficient to prepare three blocks each having a memory block of about 32 to 128 bytes, and it becomes possible to easily incorporate the reception buffer into the ASIC.

[0035]

As described above, according to the network interface circuit (claim 1) of the present invention, the frame data stored in the receiving buffer is written in the system memory via the DMA controller. It is possible to easily manage the frame and avoid the cost increase of the ASIC.

Further, according to the network interface circuit of the present invention (claim 2), the memory is made into an aggregate of small memory blocks and each memory block stores only one frame. , The reception buffer can be easily incorporated in the ASIC, the frame can be easily managed, and the manufacturing cost thereof can be reduced.

Further, according to the network interface circuit of the present invention (claim 3), when the receiving buffer is composed of two buffer blocks, it may happen that neither buffer block can be used, and the receiving overrun occurs. Therefore, a new frame can be assigned to the standby buffer by providing three buffer block configurations and a standby buffer, so that stable frame data reception control is realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration example of an ASIC (network interface circuit) according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of reception and transfer operations of a reception buffer block in FIG.

FIG. 3 is a block diagram showing a system configuration example of a conventional general network interface circuit.

[Explanation of symbols]

1 MAC 2 Receive buffer control section 3-5 Receive buffer 6 DMA control section 7 bus arbiter 8 Memory control section 9 System memory 16 network

Claims (3)

[Claims] 1. A network interface circuit using an ASIC that is mounted on an image forming apparatus having a built-in network interface and is designed to use a plurality of application functions as a shared resource of a system memory, wherein the ASIC is A MAC unit that performs protocol control of the network, a reception block that temporarily stores frame data, and a DMA controller that controls the reception block are provided, and the reception block is stored in the system memory via the DMA controller. A network interface circuit characterized by writing stored frame data. 2. The network interface circuit according to claim 1, further comprising: a reception buffer control unit configured to control the reception buffer, wherein the reception block includes a plurality of small-capacity reception buffers. . 3. The reception block is composed of three reception buffers, and when receiving frame data, two reception buffers are used and another one reception buffer is controlled to be always in a standby state. The network interface circuit according to claim 1.