JP2003099149A - Power saving interface device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power saving interface device having a DMAC which is equipped with an internal register access control circuit to which a clock is selectively supplied only when CPU access is generated wherein the clock supply is temporarily stopped when a memory access request is not immediately permitted. SOLUTION: The DMAC 30 is constituted of an arbiter interface control part 34 for controlling the interface of a request signal 39 and a permission signal with an arbiter 60, a memory interface control part 44 for executing interface control with a memory interface 4, a data transfer block 42 constituted of a data buffer 35 for temporarily storing data and an external device interface control part 36 for controlling interface with an external device, a selector circuit 31 for validating a clock signal 37 by a clock enable signal 38, and an internal register access control part 32 for controlling a plurality of internal register groups 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving interface device, and more particularly to a power saving interface device for supplying power to a selected circuit to save power.

[0002]

2. Description of the Related Art Conventionally, as a power saving method for hardware, attention has been paid to the fact that the power consumption during semiconductor switching is large, and the clock is partially or entirely stopped or the clock frequency is reduced. Such a method has been proposed. For example, JP-A-5-27405
Japanese Patent No. 4 discloses a technique for saving power of an information processing apparatus having two or more devices that can be bus masters. According to this, when one device is the bus master, the supply of the clock of the device that can be another bus master is stopped to save power.

[0003]

In a system having a single CPU, a plurality of CPUs' access to peripheral devices naturally does not occur at the same time. Therefore, currently CPU
It is not necessary for all circuit modules in the peripheral device that accepts access to be operating, and if there are multiple modules that are being clocked even though there is no access from the CPU, useless power is consumed accordingly. become.
Also, a DMAC that has a single memory interface and serves as a bus master for multiple memory interfaces.
A system with a (Direct Memory Access Controller) has an arbiter that performs access arbitration. However, even though an access request is issued to the arbiter, unnecessary power consumption occurs while waiting without access permission. To do. In view of the above problems, the present invention has an internal register access control circuit to which a clock is selectively supplied only when a CPU access occurs, and a DMAC that temporarily stops the clock supply when a memory access request is not immediately granted. An object is to provide a power-saving interface device.

[0004]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention according to claim 1 is directed to an external register connected to a plurality of external devices and having an internal register group for operation control. A memory access controller,
A CPU interface unit for controlling an interface with a central control unit; a memory access interface unit for controlling an interface for memory access; and an arbiter for controlling access permission of the direct memory access controller.
The U interface unit has an address decoder unit that decodes an address from the central control unit and a clock enable generation unit that issues a clock enable signal to the memory access interface unit, and the U decoder unit decodes the address by the address decoder unit. The clock enable signal is input from the clock enable generation unit to the direct memory access controller corresponding to the generated address. In a system having a single CPU instead of a duplex system, a plurality of CPU accesses to peripheral devices naturally do not occur simultaneously. Therefore, it is not necessary to operate all the circuit modules in the peripheral device that currently accepts the CPU access, and if the clock supply to the circuit module that is not accessed by the CPU is stopped, wasteful power consumption will not be consumed. . According to this invention, since the clock enable signal is input from the clock enable generation unit to the direct memory access controller corresponding to the address decoded by the address decoder unit, wasteful power consumption is prevented. .

According to a second aspect of the present invention, the direct memory access controller includes an arbiter interface control unit for controlling an interface of a request signal and a permission signal for access to the arbiter, and interface control with a memory interface. A data transfer block including a memory interface control unit for performing the above operation, a data buffer for temporarily storing data, and an external device interface control unit for controlling an interface with the external device, and a clock input enabled by the clock enable signal. A first clock selection circuit for controlling the internal register group, and an internal register access control unit for controlling the internal register group. The internal register access control unit is configured to perform the internal operation when the clock selection circuit selects the clock. cash register It is also an effective means of the present invention that the data access control unit enabling operation. When an internal register access of a certain direct memory access controller (hereinafter referred to as DMAC) by the CPU occurs, the address is first decoded in the CPU interface unit to determine the DMAC to be accessed. Next, the clock enable signal to the target DMAC is enabled and the CPU interface signal is passed as it is. After that, the internal register access control unit of the target DMAC processes the register access. The CPU interface detects the end of the internal register access and disables the clock enable signal to the DMAC again. Since the internal register holds the value even when the clock is not supplied to the internal register access control unit, the arbiter interface and the external device interface control unit can refer to the internal register without any problem. According to such a technical means, the internal register access control unit enables the internal register access control unit to operate when the clock selection circuit selects the clock, so that power consumption is reduced while holding the contents of the register. Can be suppressed.

According to a third aspect of the invention, the arbiter selects flag storage means for storing a detection flag for detecting a request from the direct memory access controller, and selects any one of the detection flags. Arbitration means for outputting a permission signal to the direct memory access controller, the arbitration means issuing the permission signal until the access is completed while any of the direct memory access controllers is accessing. Not doing is also an effective means of the present invention. Each arbiter is DM
Input the access request signal from AC to each DM
It has a grant signal to AC as an output. The arbitration mechanism selects one DMAC that is allowed to access now. In addition to this, it has a DMAC request detection flag corresponding to each DMAC. Also, the arbiter cannot immediately issue the grant signal while another DMAC is accessing. According to such a technical means, the arbitration means of the arbiter does not issue the permission signal until any one of the DMACs is accessing until the access is completed, so that unnecessary power is not consumed. Further, the invention of claim 4 is the direct
The memory access controller includes a logical sum circuit that performs a logical sum of the internal enable signal from the arbiter interface control unit and the enable signal of the arbiter, and a second input that validates the clock input by the output of the logical sum circuit. It is also an effective means of the present invention that the data transfer block further comprises a clock selection circuit, and the data transfer block can be operated when the second clock selection circuit selects the clock. Even if a request is issued to the arbiter, the grant signal is not always generated immediately. Therefore, if a grant signal does not come after a lapse of a fixed time after issuing a request, the internal enable signal is disabled and the clock is stopped. Subsequent control is performed by the grant signal. According to this technical means, when the second clock selection circuit selects the clock, the data transfer block enables the data transfer block, so that a request is sent to the arbiter and a grant signal comes. It is possible to suppress unnecessary power consumption during waiting time.

According to a fifth aspect of the present invention, a direct memory access controller, which is connected to a plurality of external devices and has an internal register group for operation control, and a PCI target for interface control of the input / output bus. The PCI target control unit includes a control unit, a PCI master control that controls a memory access interface, and an arbiter that controls access permission of the direct memory access controller, and the PCI target control unit receives an address from the input / output bus. An address decoder unit for decoding, a clock enable generation unit for issuing a clock enable signal to the memory access interface unit, and a configuration register for setting an address of the internal register group of the direct memory access controller are provided. And, characterized by inputting a clock enable signal from the clock enable generator to said direct memory access controller corresponding to the address decoded by the address decoder. According to the PCI specifications, the internal register group of this device is mapped in the memory space from the base address set in the configuration register address. Once this mapping is complete, the PCI target controller will request access to the mapped internal registers from other PCI masters (usually the CPU).
(Access request from) and responds. According to this invention, since the clock enable signal is input from the clock enable generation unit to the direct memory access controller corresponding to the address decoded by the address decoder unit, unnecessary PC
Power can be saved by stopping access to the I target control unit. According to a sixth aspect of the present invention, the direct memory access controller is an arbiter interface control unit that controls an interface of a request signal and a permission signal of access with the arbiter, and a memory that performs interface control with a memory interface. A data transfer block including an interface control unit, a data buffer for temporarily storing data, and an external device interface control unit for controlling an interface with the external device; and a clock input signal for enabling a clock input by the clock enable signal. No. 1 clock selection circuit and an internal register access control unit for controlling the internal register group. The internal register access control unit is configured to access the internal register when the clock selection circuit selects the clock. It is also an effective means of the present invention to allow running control section. According to this technical means, the same operational effect as that of claim 2 is achieved.

According to a seventh aspect of the invention, the arbiter selects flag storage means for storing a detection flag for detecting a request from the direct memory access controller, and selects any one of the detection flags. Arbitration means for outputting a permission signal to the direct memory access controller, the arbitration means issuing the permission signal until the access is completed while any of the direct memory access controllers is accessing. Not doing is also an effective means of the present invention. According to this technical means, the same operational effect as that of claim 3 is achieved. Further, in the invention of claim 8, the direct memory access controller is a logical sum circuit for performing a logical sum of an internal enable signal from the arbiter interface control section and a permission signal of the arbiter, and the logical sum circuit. A second clock selection circuit for validating a clock input according to the output of the second data transfer block,
It is also an effective means of the present invention to enable the data transfer block when the clock selection circuit of (1) selects the clock. According to this technical means, claim 4
The same action and effect are obtained.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments shown in the drawings. However, the constituent elements, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely explanatory examples, not the gist of limiting the scope of the present invention thereto, unless specifically stated. .. FIG. 1 is a block diagram of a power saving interface device according to a first embodiment of this invention. The configuration of the power saving interface device 10 includes a plurality of external devices A22, external devices B23, and external devices X24, and DMAC-A5, DMAC-B6, and DMAC-X that are respectively connected to the external devices A22, B23, and X24.
7, a CPU interface unit 1 connected to the CPU 20 to control the interface, and a memory interface unit 4 connected to the memory 21 to control the interface.
And an arbiter 6 for controlling the access permission of the DMAC.
It is composed of 0 and. An address decoding unit 2 that decodes an address for internal register access in the CPU interface unit 1 to determine which DMAC register in the device, and a clock enable generation unit that enables clock supply to the decoding destination DMAC Have 3.
The arbiter 60 arbitrates memory access from the DMAC-A5 to the DMAC-X7. Each circuit is connected to the internal CPU interface 8 and the internal arbiter / memory interface 9. FIG. 2 is an internal block diagram of the first DMAC of the present invention. The configuration of the DMAC 30 is such that an arbiter / interface controller 34 that controls the interface of the request signal 39 and the permission signal with the arbiter 60, a memory interface controller 44 that controls the interface with the memory interface 4, and a temporary data transfer. A data transfer block 42 composed of a data buffer 35 for storing data in an external device and an external device interface control section 36 for controlling an interface with the external device, and a selector circuit 3 for enabling a clock signal 37 by the clock enable signal 38.
1 and an internal register access control unit 32 that controls a plurality of internal register groups 33.

Next, the flow of the internal register access will be described with reference to FIGS. First, in the initial state, the CPU interface unit 1 disables the clock enable signal 38 for all DMACs. At this time, the clock is not supplied to the internal register access control unit 32 of each DMAC, and the operation is stopped. Here, when an internal register access of a certain DMAC occurs from the CPU 20, the address is first decoded by the address decoding unit 2 in the CPU interface unit 1 to determine the DMAC to be accessed. Next, the clock enable signal 38 to the target DMAC is enabled by the clock enable generation unit 3, and the CP
Pass the U interface signal as it is. After that, the target DM
The AC internal register access controller 32 handles register access. The CPU interface unit 1 detects the end of the transaction for accessing the internal register and disables the clock enable signal 38 to the DMAC again. The internal register group 33 retains the value even when the clock is not supplied to the internal register access control section 32. Therefore, the arbiter interface control section 34 and the external device interface control section 36 perform the internal register group 33.
Can be referred to. As described above, wasteful power consumption can be reduced by operating the internal register access control unit, which is relatively infrequently used in the operation of the DMAC, by supplying the clock only during access.

FIG. 3 is a block diagram of an arbiter according to the second embodiment of the present invention. The arbiter 600 inputs the access request signal 65 from each DMAC and
Output a grant signal 66 to The arbitration mechanism 64 selects one DMAC to which access is now permitted.
In addition to this, it has DMAC request detection flags 61 to 63 corresponding to each DMAC. FIG. 4 is a DMAC block diagram of the second embodiment of the present invention. Since the same components are designated by the same reference numerals, duplicate description will be omitted. The difference between FIG. 3 and FIG. 2 is that, in addition to the selector B51 and the DMAC of FIG.
From the internal enable signal 53 from the arbiter 60, an OR circuit 52 that ORs the grant signal 40 from the arbiter 60, and a selector B51 for inputting a clock. As a result, the clock 54 is supplied to the data transfer block 42 only when the internal enable signal 53 is enabled. In some external devices, if the data transfer fails when the clock is stopped, the external device interface control unit 36 may be excluded from the range in which the clock 54 is stopped.

Next, the operation when one of the DMACs receiving data from the external device accesses the memory will be described. First, in the initial state, the request detection flags 61 to 63 in the arbiter 60 are all 0. At this time, a memory access request 65 is issued from the DMAC.
If another DMAC is not accessing the memory,
Arbiter 60 immediately grants 6 to this DMAC.
Issue 6 (permit). On the other hand, when another DMAC is accessing the memory, the arbiter 60 cannot immediately issue the grant. The DMAC that issued the request 65 samples the grant signal 66 with a clock after issuing the request. If the grant does not arrive within a certain period, the internal enable signal 53 is disabled and the clock 54 to the data transfer block 42 is sent. To stop. Although the arbiter did not issue a grant to this DMAC, it sets an internal DMAC request detection flag corresponding to this DMAC. When the memory access operation of another DMAC is completed and the memory access to this DMAC is permitted, the arbiter 60 outputs a grant signal 66 to this DMAC. This grant 40 enables the selector B51, and the clock 54 is supplied again. After the data transfer block 42 is restarted, the internal enable signal 53 is enabled and
Perform memory access. As described above, since the DMAC issues a memory access request and stops the clock while waiting for the grant, useless power consumption can be reduced.

FIG. 5 is a block diagram of a power-saving interface device according to the third embodiment of the present invention. Where DM
The AC and the arbiter have the same configuration as in the second embodiment. Since the same components are designated by the same reference numerals, duplicate description will be omitted. 5 is different from FIG. 1 in that the CPU interface unit 1 and the memory interface unit 4 are PCI (Peripheral Component Interconn
ect) The point is that the target control unit 71 and the PCI master control unit 75 are replaced. PCI target control unit 71
Is an address decoding unit 72 that decodes an address from the PCI bus 76, and a clock enable generation unit 73 that generates an enable signal for the DMAC selected by the address decoding unit 72.
And a configuration register 74 for mapping addresses. PCI target control unit 71
, The PCI master control unit 75 is connected to the PCI bus 76, access of internal registers from the CPU, and PC
Access to the I configuration register 74 is response-controlled by the PCI target control unit 71. On the other hand, the memory access by DMA is controlled by the PCI master control unit 75. According to the PCI specifications, the internal register group 33 of this device is mapped in the memory space from the base address set in the address of the configuration register 74. Once this mapping is completed, the PCI target control unit 71 decodes and responds to an access request (usually an access request from the CPU) to the mapped internal register from another PCI master. The PCI target control unit 71 of this embodiment has a clock enable generation unit 73,
The clock enable signal 38 is enabled only when the access request generated on the PCI bus 76 is addressed to this device, and the other states are disabled. As a result, the internal register control unit 32 is provided except when the internal register is accessed.
The clock supply to is stopped. On the data transfer block side, the memory interface is only replaced by the PCI master control unit 75, and the clock can be stopped while waiting for the grant, as in the second embodiment. As described above, it is possible to reduce unnecessary power consumption in both the internal register access control unit 32 and the data transfer block 42.

[0014]

As described above, according to the present invention, the clock enable signal from the clock enable generation unit is sent to the direct memory access controller corresponding to the address decoded by the address decoder unit. Is input, there is no need to waste power. According to claims 2 and 6, the internal register access control unit enables the internal register access control unit to operate when the clock selection circuit selects the clock, so that power consumption is reduced while holding the contents of the register. Can be suppressed. According to claims 3 and 7, the arbitration means of the arbiter is:
Since the permission signal is not issued until the access is completed, unnecessary power is not consumed. Claims 4 and 8
Since the data transfer block enables the data transfer block when the second clock selection circuit selects the clock, the waiting time until the grant signal comes to the arbiter is issued. Useless power consumption can be suppressed. According to a fifth aspect of the present invention, the clock enable signal is input from the clock enable generation section to the direct memory access controller corresponding to the address decoded by the address decoder section, so that unnecessary access of the PCI target control section is prevented. Power can be saved by stopping.

[Brief description of drawings]

FIG. 1 is a block diagram of a power-saving interface device according to a first embodiment of this invention.

FIG. 2 is an internal block diagram of a first DMAC of the present invention.

FIG. 3 is a block diagram of an arbiter according to a second embodiment of the present invention.

FIG. 4 is a DMAC block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of a power saving interface device according to a third embodiment of the present invention.

[Explanation of symbols]

1 CPU interface unit, 2 address decoding unit, 3 clock enable generation unit, 4 memory interface unit, 5 DMAC-A, 6 DMAC-B, 7
DMAC-X, 8 Internal CPU interface, 9
Internal arbiter / memory interface, 10 power saving interface device, 20 CPU, 21 memory, 2
2 external device A, 23 external device B, 24 external device X

Claims (8)

[Claims] 1. A direct circuit which is connected to a plurality of external devices and has an internal register group for controlling operation.
A memory access controller, a CPU interface section for controlling the interface with the central control unit, a memory access interface section for controlling the memory access interface, and an arbiter for controlling access permission of the direct memory access controller. The CPU interface unit includes an address decoder unit that decodes an address from the central control unit, and a clock enable generation unit that issues a clock enable signal to the memory access interface unit. A clock enable signal is input from the clock enable generation unit to the direct memory access controller corresponding to the address decoded by the address decoder unit. Power interface device. 2. The direct memory access controller includes an arbiter interface control unit that controls an interface of a request signal and a permission signal of access to the arbiter, and a memory interface control unit that controls an interface with a memory interface. A data transfer block that includes a data buffer that temporarily stores data and an external device interface control unit that controls an interface with the external device,
A first clock selection circuit that validates a clock input by the clock enable signal; and an internal register access control unit that controls the internal register group. The power-saving interface device according to claim 1, wherein when the clock is selected, the internal register access control unit is made operable. 3. The direct memory access controller, wherein the arbiter stores a detection flag for detecting a request from the direct memory access controller, and selects one of the detection flags. And an arbitration unit that outputs a permission signal to each of the direct memory access controller and the arbitration unit does not issue the permission signal until the access is completed while any of the direct memory access controllers is accessing. Item 1. The power-saving interface device according to item 1. 4. The direct memory access controller comprises a logical sum circuit for performing a logical sum of an internal enable signal from the arbiter interface control section and a permission signal of the arbiter, and a clock based on the output of the logical sum circuit. A second clock selection circuit that enables the input;
The power-saving interface device according to claim 1, further comprising: a data transfer block that enables the data transfer block when the second clock selection circuit selects the clock. 5. A direct connection which is connected to a plurality of external devices and has an internal register group for controlling operations.
A memory access controller; a PCI target control unit for controlling the interface of the input / output bus; a PCI master control for controlling the memory access interface; and an arbiter for controlling access permission of the direct memory access controller, The PCI target control unit includes an address decoder unit that decodes an address from the input / output bus, a clock enable generation unit that issues a clock enable signal to the memory access interface unit, and the direct memory access controller. And a configuration register for setting the address of the internal register group of the direct memory access controller corresponding to the address decoded by the address decoder unit. Saving interface apparatus characterized by inputting a clock enable signal from the click enable generator. 6. The direct memory access controller includes an arbiter interface control unit that controls an interface of a request signal and a permission signal of access to the arbiter, and a memory interface control unit that controls an interface with a memory interface. A data transfer block that includes a data buffer that temporarily stores data and an external device interface control unit that controls an interface with the external device,
A first clock selection circuit that validates a clock input by the clock enable signal; and an internal register access control unit that controls the internal register group. The power saving interface device according to claim 5, wherein when the clock is selected, the internal register access control unit is made operable. 7. The direct memory access controller, wherein the arbiter stores a detection flag for detecting a request from the direct memory access controller, and selects one of the detection flags. And an arbitration unit that outputs a permission signal to each of the direct memory access controller and the arbitration unit does not issue the permission signal until the access is completed while any of the direct memory access controllers is accessing. Item 5. The power-saving interface device according to item 5. 8. The direct memory access controller includes a logical sum circuit for performing a logical sum of an internal enable signal from the arbiter interface control section and a permission signal of the arbiter, and a clock by an output of the logical sum circuit. A second clock selection circuit that enables the input;
6. The power saving interface device according to claim 5, further comprising: a data transfer block that enables the data transfer block when the second clock selection circuit selects the clock.