JP2003092390A - Magnetoresistive memory device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetoresistive memory device having a three- dimensional cell laminated structure suitable for high integration and a method for manufacturing it. SOLUTION: At first, MR elements 4a and 4b are stacked on a silicon substrate 1 with a digit line 8 shred. A bit line 3a to be connected to the lower MR element 4a is formed under the MR element 4a, and a bit line 3b to be connected to the upper MR element 4b is formed above the MR element 4b. The word line 6a to be connected to the lower MR element 4a and the word line 6b to be connected to the upper MR element 4b are formed by using the same conductive layer at the same time as the digit line 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoresistive memory device using a magnetoresistive effect element as a storage element and a manufacturing method thereof.

[0002]

2. Description of the Related Art A tunnel magnetoresistive effect (TM) is used as a memory device having characteristics such as nonvolatility, high speed, and long-term reliability.
R: Tunneling Magneto Resistance (MRAM: Magnetic Random)
Access Memory has been proposed (eg S. Tehran
i et al., "Recent Developments in Magnetic Tunnel J
unction MRAM, "IEEE Trans. Magn., vol. 36, p.2752,
2000).

A magnetic tunnel junction (MTJ), which is a main part for obtaining TMR, is
It has a structure in which two ferromagnetic films are opposed to each other with a tunnel insulating film interposed therebetween. The two ferromagnetic films are formed in a structure that has two stable states when the spin directions are parallel to each other and antiparallel to each other. When the spin directions are parallel to each other in the upper and lower ferromagnets, the tunnel current becomes the largest, that is, the tunnel resistance becomes the smallest. When the spin directions of the upper and lower magnetic bodies are anti-parallel to each other, the tunnel current decreases and the tunnel resistance becomes the largest. Data "1" and "0" can be stored depending on the magnitude of these tunnel resistances. Usually, one of the two ferromagnetic films is fixed to the spin and the other is set to the variable spin, and the variable spin is rotated by the current magnetic field to enable data rewriting.

As shown in FIG. 10, a TMR memory cell is usually composed of a select transistor 101 formed on a silicon substrate 100 and an MTJ 102 formed on the select transistor 101. Under the MTJ 102, a digit line (write word line) 103 for applying a current magnetic field at the time of writing data is embedded in the MTJ 102.
The bit line 104 connected to the upper surface of the bit line 104 is disposed on the upper side of the bit line 2. The lower surface of the MTJ 102 has contact wiring 10
It is connected to the drain of the selection transistor 101 via 8, 105, and 109. The gate 107 of the selection transistor 101 serves as a read word line.

In such a TMR cell, when writing data, the bit line 104 and the digit line 10
3 is selected and a current is caused to flow through both of the selected bit line 104 and digit line 103 to generate a current magnetic field. As a result, only the magnetic field applied to the MTJ 102 of the selected cell located at the cross point between the bit line 104 and the digit line 103 can exceed the spin inversion threshold value, and the target information is MTJ 102.
Written in.

When reading the data written in the MTJ 102, a voltage is applied to the read word line 107 to turn on the selection transistor 101, and then the ground line 11 is passed from the bit line 104 through the MTJ 102.
The value of the current flowing through 0 is detected, and the difference in tunnel resistance of different MTJs is read. As a result, the data “1”,
The determination of "0" is performed.

[0007]

The MRAM structure in which one cell is composed of the MTJ and the selection transistor described above has a serious problem for high integration. As shown in FIG. 10, in this MRAM, the MOS which needs to be formed on the MTJ and crystalline Si in one memory cell.
Since the FETs are arranged, the structure is complicated and the unit cell area cannot be reduced sufficiently.
On the other hand, it has been proposed to form an MTJ and an amorphous Si diode as a switching element in series to reduce the cell area and enable multi-layering. It wasn't done. It is an object of the present invention to provide a magnetoresistive memory device having a three-dimensional cell laminated structure suitable for high integration and a method for manufacturing the same.

[0008]

A magnetoresistive memory device according to the present invention includes a substrate, a first bit line formed on the substrate, and a first lower surface formed on the first bit line. A first magnetoresistive element connected to the bit line;
A digit for providing a write current magnetic field to the first magnetoresistive effect element, which is arranged on the first insulating film covering the first magnetoresistive effect element so as to intersect with the first bit line. Line and the digit line on the first insulating film in parallel with each other, and connected to the upper surface of the first magnetoresistive effect element through a contact formed on the first insulating film. A first word line and the first digit line on the first insulating film in parallel with the digit line;
A second word line disposed on the opposite side of the second word line and a second insulating film covering the digit line and the first and second word lines at a position for receiving the current magnetic field of the digit line. And a lower surface connected to the second word line through a contact formed in the second insulating film.
Of the magnetoresistive effect element and the third insulating film covering the second magnetoresistive effect element are arranged in parallel with the first bit line, and the contact is formed through a contact formed in the insulating film. A second bit line connected to the upper surface of the second magnetoresistive element.

The magnetoresistive memory device according to the present invention also includes a substrate, a first word line and a first digit line arranged in parallel with each other on the substrate, the first word line and the first digit line. The first insulating film covering the first digit line is formed at a position to receive the current magnetic field of the first digit line, and the lower surface of the first digit line is connected to the first insulating film via a contact formed in the first insulating film. A first magnetoresistive effect element connected to the word line, and intersecting the first word line and the first digit line so as to be connected to the upper surface of the first magnetoresistive effect element. The bit line is provided, a second magnetoresistive effect element formed on the bit line and having a lower surface connected to the bit line, and the second insulating film covering the second magnetoresistive effect element is provided on the second magnetoresistive effect element. Parallel to 1 word line and 1st digit line And a second magnetic line connected to the upper surface of the second magnetoresistive effect element through a contact formed in the second insulating film, and a current magnetic field is applied to the second wordline and the second magnetoresistive effect element. And a second digit line for providing.

In the method of manufacturing a magnetoresistive memory device according to the present invention, a step of forming a first bit line on a substrate and a first lower surface connected to the first bit line on the first bit line. A step of forming a magnetoresistive effect element;
On the first insulating film covering the magnetoresistive element of
A digit line for applying a write current magnetic field to the first magnetoresistive effect element so as to intersect the bit line of
The digit line and the first word line connected in parallel to the digit line and connected to the upper surface of the first magnetoresistive effect element through the contact formed in the first insulating film. Forming a second word line on the opposite side of the first word line with the digit line interposed between the digit line and the second insulating film covering the first and second word lines; Forming a second magnetoresistive element such that the lower surface is connected to the second word line through a contact formed in the second insulating film at a position where the current magnetic field of the line is received; On the third insulating film covering the second magnetoresistive effect element, in parallel with the first bit line, through the contact formed in the third insulating film, the second magnetoresistive effect element Form a second bit line connected to the top surface And having a degree, the.

The method of manufacturing a magnetoresistive memory device according to the present invention also includes a step of forming a first word line and a first digit line parallel to each other on a substrate, and the first word line and the first digit line. The lower surface is connected to the first word line via a contact formed in the first insulating film at a position on the first insulating film covering the line that receives the current magnetic field of the first digit line. Forming a first magnetoresistive effect element, and forming a bit line intersecting with the first word line and the first digit line so as to be connected to an upper surface of the first magnetoresistive effect element. A step of forming a second magnetoresistive effect element having a lower surface connected to the bit line on the bit line, and the first word on the second insulating film covering the second magnetoresistive effect element. Line and first digit In parallel with the above, a current magnetic field is applied to the second word line connected to the upper surface of the second magnetoresistive effect element and the second magnetoresistive effect element via the contact formed in the second insulating film. And forming a second digit line for providing.

According to the present invention, the magnetoresistive effect (MR)
When the elements are arranged three-dimensionally, the digit lines, which are current magnetic field wiring, or the bit lines, which are data lines, are placed above and below
By sharing the R element, the laminated structure and the laminated process can be simplified, and a highly integrated memory can be obtained.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1A is a layout of four cells of an MRAM cell array according to the first embodiment, and FIG. 1B is a sectional view taken along the line II '. In this embodiment, the first MR elements 4a are two-dimensionally arranged on the silicon substrate 1, and the second MR elements 4b are two-dimensionally arranged on the first MR elements 4a. A digit line 8 for applying a current magnetic field to the upper and lower MR elements 4a and 4b is arranged so as to be shared by the upper and lower MR elements 4a and 4b.

More specifically, a plurality of first bit lines (BL1) 3a which are data transfer lines are formed on the silicon substrate 1 with the insulating film 2 interposed therebetween. This first
The first MR elements 4a are formed in a two-dimensional array by contacting the lower surface with the bit lines 3a. First MR element 4
a is covered with an insulating film 5, and a first word line (WL1) 6 serving as a read word line of the first MR element 4a is formed on the a.
a, read word line (WL2) of the second MR element 4b
Second word line (WL2) 6b and first and second
Digit line (D) shared by the MR elements 4a and 4b of
L) 8 are arranged in parallel with each other so as to be orthogonal to the bit lines. The digit line 8 is the MR element 4
The word lines 6a and 6b are arranged immediately above a and sandwich the word lines 6a and 6b. The first word line 6 a is connected to the MR element 4 via the contact wiring 12 embedded in the insulating film 5.
It is connected to the upper surface of a.

The second MR elements 4b are two-dimensionally arrayed on the insulating film 9 covering the digit lines 8 and the word lines 6a and 6b. The lower surface of the second MR element 4b has an insulating film 9
It is connected to the second word line 6b via the contact wiring 13 buried in. Then, the second MR element 4b
Second bit line 3b so as to contact the upper surface of the
, Are arranged in parallel with the first bit line 3a.

In the case of this embodiment, the first MR element 4
a, the digit line 8 and the second MR element 4b are the substrate 1
They are stacked almost in line on the vertical line. In other words, the first MR element 4a is located almost directly below the digit line 8 and the second MR element 4b is located almost directly above the digit line 8.

The MR elements 4a and 4b of this embodiment are
As shown in FIG. 7A, the MTJ has ferromagnetic films 71 and 73 facing each other with the tunnel insulating film 72 interposed therebetween. In the case of this embodiment, the ferromagnetic films 71 and 73 have an easy axis of magnetization in the longitudinal direction of the digit line 8, one of which is spin-fixed and the other is spin-variable. The cell array of this embodiment has a simple matrix structure having no switching element. Data reading is performed by detecting the magnitude of the current between the selected word line (WL1) 6a and bit line (BL1) 3a in the lower cell array. Similarly, for the upper cell array, the selected word line (WL2) 6b and bit line (BL2)
This is performed by detecting the magnitude of the current between 3b and 3b. As the sense amplifier, a current detection type sense amplifier that compares the current with the reference cell may be used.

Although the digit line 8 functions only as a current magnetic field wiring for performing a write operation on the MR elements 4a and 4b, in this embodiment, two MR elements 4a and 4a vertically stacked.
It is also used as the current magnetic field wiring of 4b. Upper MR
When writing to the element 4b, both the upper bit line 3b and the digit line 8 are selected. As a result, a current field in the hard axis direction is applied by the digit line 8 to the selected MR element 4a on the upper side, and a current field in the easy axis direction is applied by the bit line 3b, and the spin inversion threshold value is increased. A magnetic field exceeding the level can be obtained, and writing becomes possible.
Similarly, writing to the MR element 4a on the lower side can be similarly performed by selecting both the lower bit line 3a and the digit line 8. Digit line 8 only or bit line 3
If the inversion threshold of the MR element is not exceeded by the current magnetic fields of only a and 3b, the digit line 8 and the bit line 3
Selective writing can be performed only at the intersection of a and 3b.

The MR elements 4a and 4b may have a switch element integrated structure as shown in FIG. 7 (b). this is,
The MTJ and the diode Di including the p-type amorphous silicon film 74 and the n-type amorphous silicon film 75 are integrally laminated. By using such an MR element structure, it is possible to prevent the bit line data from sneaking into the unselected word lines.

The manufacturing process of the cell array of the embodiment will be described with reference to FIGS. Silicon substrate 1 shown in FIG.
In this case, it is assumed that transistors and the like which form peripheral circuits have already been formed. On this silicon substrate 1, SiO
An insulating film 2 such as 2 is formed, and CMP (Chemical Mechanica)
l Polish) method. And this insulating film 2
To 200 by RIE (Reactive Ion Etching) method.
A wiring groove of about nm is formed, and the bit line 3a is embedded and formed. Specifically, MOCVD (Metal Organic Chemic
Al Vapor Deposition) method is used to bury W, and this is flattened by CMP method to form the bit line 3a.
At this time, in the region of contact with the peripheral circuit, a contact for the lower bit line 3a is also formed at the same time.

Next, as shown in FIG. 3, a laminated film of the MR element 4a is formed on the entire surface by sputtering. Where M
The R element 4a is an MTJ element as described above, for example, 1
The tunnel insulating film made of AlOx of about 2 nm is sandwiched between ferromagnetic films. CVD on the MR element 4a
Method using DLC (Diamond Like Carbo
n) 31 is formed, this is patterned by ion milling using a resist mask, and the MTJ layer is further patterned using the mask of the DLC film.

Next, as shown in FIG. 4, an insulating film 5 is formed to cover the patterned MR element 4a and to embed a contact wiring 12 for connecting the upper surface of the MR element 4a to a word line. Specifically, the insulating film 51 is formed on the entire surface.
Are deposited and planarized by the CMP method. Next, a conductor film is formed by a sputtering method, and this is patterned to form the contact wiring 12. Further, after depositing an insulating film 52 on the entire surface, a via hole for forming a contact is formed, and a metal 41 such as W is buried therein,
Planarization is performed by the CMP method.

Next, as shown in FIG. 5, an Al--Cu film is deposited by the sputtering method and patterned by RIE using a resist mask to form digit lines 8 and word lines 6a, which are parallel to each other with the digit line 8 interposed therebetween. 6b is formed. The word line 6a is connected to the M via the buried contacts 41 and 12.
It will be connected to the R element 4a.

Next, as shown in FIG. 6, an insulating film 91 covering the wiring layer is deposited and flattened, the W contact 61 is embedded in the word line 6b, and the contact wiring 13 is further patterned thereon. Further, on this contact wiring 13, an MR element 4b having a similar structure is formed in the same process as the lower MR element 4a. Thereafter, as shown in FIG. 1B, an insulating film 92 is deposited and flattened, and the MR element 4b is formed.
Forming an upper bit line 3b connected to.

As described above, according to this embodiment, the digit lines are shared by the upper and lower cell arrays and the three-dimensional M is formed.
By arranging the R elements, the unit cell area is small,
A highly integrated MRAM can be obtained. Further, since the word lines used in the upper and lower cell arrays are simultaneously formed by using the same conductor layer as the digit lines, it is easy to form a laminated structure of the cell arrays.

[Second Embodiment] FIG. 8 shows a cross-sectional structure of an MRAM cell array according to the second embodiment, corresponding to FIG. 1B. The laminated structure of the MRAM cell array is basically the same as that of the first embodiment, but the arrangement of the lower cell array and the upper cell array is different from that of the first embodiment in the lateral direction. That is, the first MR element 4a is located below the space between the digit line 8 and the word line 6b for the upper cell array, and the second MR element 4a is the digit line 8 and the word for the lower cell array. It is arranged so as to be located above the space with the line 6a.

In this embodiment, the upper MR element 4b
When writing data to, at the same time as the digit line 8,
Word line 6a used for reading the lower cell array
To drive. When writing to the lower MR element 4a,
The digit line 8 and the word line 6b used for reading the upper cell array are simultaneously driven. That is, the word line not directly connected to the target MR element is used as the current magnetic field wiring at the same time as the shared digit line for the write operation of the two memory cells stacked above and below. By using two current magnetic field wirings for the write operation in this way, a stronger current magnetic field can be obtained. Further, since the current density per wire can be reduced in order to obtain the same current magnetic field, problems associated with wiring such as electromigration can be reduced.

[Third Embodiment] FIG. 9 is a sectional view of a cell array according to a third embodiment of the present invention. In this embodiment, unlike the first and second embodiments, the upper and lower cell arrays are stacked with the bit line 3 shared. To briefly explain according to the manufacturing process, the digit line 8a for the lower cell array and the word line 6 are formed on the insulating film 2 covering the silicon substrate 1.
a are formed so as to be parallel to each other. This wiring layer is flattened with the insulating film 51 to form the contact wiring 12 connected to the word line 6a.

Then, the first MR element 4a is located on the contact wiring 12 so as to be located directly above the digit line 8a.
Are formed in a matrix. Then, after being flattened by the insulating film 52, the bit line 3 connected to the upper surface of the MR element 4a is patterned thereon so as to be orthogonal to the digit line 8a. Further, on the bit line 3, a second MR
The elements 4b are formed in a matrix. MR element 4
a and 4b are similar to those of the previous embodiment, and
The structure shown in (b) is assumed.

After flattening with the insulating film 91,
The contact wiring 13 connected to the upper surface of the MR element 4b is formed and further covered with the insulating film 92. On top of this, the word line 6 connected to the MR element 4b via the contact wiring 13 is formed.
b and the digit line 8b are patterned so as to be parallel to the lower digit line 8a and the word line 6a. Thus, the MR element 4a of the lower cell array and the digit line 8a for giving a current magnetic field to it, and the MR element 4a of the upper cell array and the digit line 8b for giving a current magnetic field to it are aligned on the perpendicular line of the substrate 1. A structure is obtained in which the layers are stacked side by side.

The read and write operations of the MRAM according to this embodiment are the same as those of the previous embodiment, except that the bit lines are shared by the upper and lower cell arrays and that separate digit lines are used in the upper and lower cell arrays during writing. Form 1
Does not change.

The present invention is not limited to the above embodiment.
For example, in each of the above embodiments, the current magnetic field of the digit line is applied in the hard axis direction of the MR element, and the current magnetic field of the bit line is applied in the easy axis direction of the MR element. However, these can be reversed. You can also In addition, in the first embodiment, the word line (WL
1) 6a, digit line (DL) 8, range of word line (WL2) 6b used for reading the upper cell (WL1
/ DL / WL2) is the unit area for the upper and lower two cells.
On the other hand, the word line can be shared by the upper and lower cells adjacent in the bit line direction. By thus sharing the word line between the upper and lower cell arrays, the cell array area can be further reduced.

Further, in the embodiment, the two-layer cell array has been described, but the cell arrays may be stacked in multiple layers. In that case, by alternately stacking the laminated structures of the first and second embodiments and the laminated structure of the third embodiment, a multilayer structure can be realized without using unnecessary thickness.
In the embodiment, the MTJ is used as the MR element. However, for example, a GMR element formed by stacking giant magnetoresistive (GMR) films, in particular, a current C flowing vertically through the stacked film.
A PP type GMR element can also be used.

[0034]

As described above, according to the present invention, when the magnetoresistive (MR) elements are arranged three-dimensionally, the digit line which is a current magnetic field wiring or the bit line which is a data line is vertically moved. It is possible to obtain a highly integrated memory by simplifying the laminated structure and the laminated process by sharing the MR element with the MR element.

[Brief description of drawings]

FIG. 1A is a diagram showing a layout of an MRAM cell array according to an embodiment of the present invention.

1B is a cross-sectional view taken along the line I-I ′ of FIG. 1A.

FIG. 2 is a cross-sectional view showing a step of forming a first bit line of the same embodiment.

FIG. 3 is a cross-sectional view showing a step of forming a first MR element of the same embodiment.

FIG. 4 is a cross-sectional view showing a step of forming a buried contact wiring according to the same embodiment.

FIG. 5 is a cross-sectional view showing a step of forming a digit line and a word line according to the same embodiment.

FIG. 6 shows a buried contact wiring and a second embodiment of the same embodiment.
FIG. 6 is a cross-sectional view showing the step of forming the MR element.

FIG. 7 is a cross-sectional view showing the structure of the MR element according to the same embodiment.

FIG. 8 is a cross-sectional view of a cell array according to another embodiment.

FIG. 9 is a cross-sectional view of a cell array according to another embodiment.

FIG. 10 is a cross-sectional view of a conventional MRAM cell.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... Insulating film, 3a, 3b ... Bit line, 4a, 4b ... MR element, 5 ... Insulating film, 6a, 6b ...
Word line, 8 ... Digit line, 9 ... Insulating film, 12, 13
… Contact wiring.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshiaki Saito             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center (72) Inventor Minoru Amano             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center (72) Inventor Katsuya Nishiyama             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center (72) Inventor Tomomasa Ueda             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center F-term (reference) 5F083 FZ10 GA10 GA30 JA36 LA02                       LA11 LA12 LA16 MA06 MA16                       PR03 PR22 PR38

Claims (8)

[Claims] 1. A substrate, a first bit line formed on the substrate, and a first magnetoresistive effect element formed on the first bit line and having a lower surface connected to the first bit line. , For applying a write current magnetic field to the first magnetoresistive effect element, which is arranged on the first insulating film covering the first magnetoresistive effect element so as to intersect with the first bit line. A digit line and a digit line are disposed on the first insulating film in parallel with the digit line and are connected to the upper surface of the first magnetoresistive effect element through a contact formed in the first insulating film. First
A word line, a second word line provided on the first insulating film in parallel with the digit line and on the opposite side of the digit line from the first word line, the digit line, Second covering the first and second word lines
Second magnetic resistance having a lower surface connected to the second word line via a contact formed in the second insulating film, the second magnetic resistance being formed on the insulating film at a position for receiving the current magnetic field of the digit line. The effect element and the third insulating film covering the second magnetoresistive effect element are arranged in parallel with the first bit line, and the contact is formed through a contact formed in the third insulating film. And a second bit line connected to the upper surface of the second magnetoresistive effect element. 2. The magnetoresistive memory device according to claim 1, wherein the first and second magnetoresistive effect elements are arranged immediately below and above the digit line. 3. The first magnetoresistive effect element is arranged below a space between the digit line and the second word line, and the second magnetoresistive effect element is arranged between the digit line and the second word line. One digit line and the second word line are driven to write data in the first magnetoresistive effect element, and the digit line and the second wordline are driven above the space between the second magnetoresistive effect element and the first word line. 2. The magnetoresistive memory device according to claim 1, wherein the digit line and the first word line are driven for data writing. 4. A substrate, a first word line and a first digit line arranged in parallel with each other on the substrate, and a first word line and a first digit line covering the first word line and the first digit line. A first digit line is formed on the insulating film at a position to receive the current magnetic field of the first digit line, and a lower surface of the first digit line is connected to the first word line via a contact formed in the first insulating film. A magnetoresistive effect element, and a bit line arranged on the first magnetoresistive effect element so as to be connected to the upper surface thereof so as to intersect with the first word line and the first digit line. A second magnetoresistive effect element formed on the bit line and having a lower surface connected to the bit line, and the first word line and the first digit on a second insulating film covering the second magnetoresistive effect element. Arranged in parallel with the wire and formed on the second insulating film A second word line connected to the upper surface of the second magnetoresistive effect element via a contact and a second digit line for applying a current magnetic field to the second magnetoresistive effect element. A characteristic magnetoresistive memory device. 5. The magnetoresistive memory device according to claim 1, wherein the first and second magnetoresistive effect elements have a ferromagnetic film / tunnel insulating film / ferromagnetic film structure. . 6. The first and second magnetoresistive effect elements have a ferromagnetic film / tunnel insulating film / ferromagnetic film structure,
2. A laminated structure with an amorphous semiconductor diode in contact with one of the ferromagnetic films is provided.
Alternatively, the magnetoresistive memory device according to item 4. 7. A step of forming a first bit line on a substrate, and a step of forming a first magnetoresistive element having a lower surface connected to the first bit line on the first bit line, On the first insulating film covering the first magnetoresistive effect element,
A digit line for applying a write current magnetic field to the first magnetoresistive effect element so as to intersect with the first bit line, and is formed in the first insulating film in parallel with the digit line. A first word line connected to the upper surface of the first magnetoresistive effect element via a formed contact,
And forming a second word line arranged on the opposite side of the first word line with the digit line interposed therebetween, and a second insulating layer covering the digit line and the first and second word lines. A second magnetoresistive effect element is formed on the film so that the lower surface is connected to the second word line via a contact formed in the second insulating film at a position where the current magnetic field of the digit line is received. And a second insulating film covering the second magnetoresistive element in parallel with the first bit line through the contact formed in the third insulating film. Forming a second bit line connected to the upper surface of the magnetoresistive element;
A method of manufacturing a magnetoresistive memory device, comprising: 8. A step of forming a first word line and a first digit line parallel to each other on a substrate, and a first step of covering the first word line and the first digit line.
Magnetic resistance whose lower surface is connected to the first word line via a contact formed in the first insulating film at a position on the insulating film where the current field of the first digit line is received. Forming an effect element; forming a bit line intersecting with the first word line and the first digit line so as to be connected to an upper surface of the first magnetoresistive effect element; A second line whose bottom surface is connected to the bit line
Forming a magnetoresistive effect element, and in parallel with the first word line and the first digit line on a second insulating film covering the second magnetoresistive effect element,
A second word line connected to the upper surface of the second magnetoresistive effect element through a contact formed in the second insulating film, and a second magnetic field for applying a current magnetic field to the second magnetoresistive effect element. A step of forming a digit line, and a method of manufacturing a magnetoresistive memory device.