JP2003092366A - Semiconductor memory and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method which increases a floating-to- control gate capacitance ratio without increasing the occupied area and suppresses variations in cell characteristics caused by processes. SOLUTION: A method of manufacturing a semiconductor memory comprises processes of: forming at least one insular semiconductor layer on a semiconductor substrate, forming a tunnel insulation film on the surface of the insular semiconductor layer, forming a side wall spacer consisting of a first conductive film divided in the height direction on the tunnel insulation film, doping impurities in self-aligning manner into the divided first conductive film to form an impurity diffusion layer, and forming an interlayer capacitor film and a second conductive film on the first conductive film. The semiconductor memory manufactured by this method comprises the semiconductor substrate and at least one memory cell which consists of at least one insular semiconductor layer, and an electric charge accumulation layer and a control gate which are formed on the entire area or a part of the area around the side wall of the insular semiconductor layer, with at least one memory cell electrically insulated from the semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a method of manufacturing a semiconductor memory device including a memory transistor having a charge storage layer and a control gate.

[0002]

2. Description of the Related Art As a memory cell of an EEPROM, a MOS transistor having a charge storage layer and a control gate in its gate portion and injecting charges into and discharging charges from the charge storage layer by utilizing a tunnel current. Devices of construction are known. In this memory cell, the difference in threshold voltage due to the difference in charge storage state of the charge storage layer is stored as data "0" and "1". For example, in the case of an n-channel memory cell using a floating gate as a charge storage layer, in order to inject electrons into the floating gate, the source / drain diffusion layer and the substrate are grounded and a positive high voltage is applied to the control gate. . At this time, electrons are injected from the substrate side to the floating gate by the tunnel current. Due to this electron injection, the threshold voltage of the memory cell moves in the positive direction. To emit electrons from the floating gate, the control gate is grounded and a positive high voltage is applied to either the source, drain diffusion layer or the substrate. At this time, the electrons on the substrate side are emitted from the floating gate by the tunnel current. By this electron emission,
The threshold voltage of the memory cell moves in the negative direction.

In the above operation, the relationship of capacitive coupling between the floating gate and the control gate and between the floating gate and the substrate is important for efficient electron injection and emission, that is, writing and erasing. That is, the larger the capacitance between the floating gate and the control gate, the more effectively the potential of the control gate can be transmitted to the floating gate, which facilitates writing and erasing. However, due to recent advances in semiconductor technology, particularly advances in fine processing technology, miniaturization and increase in capacity of EEPROM memory cells are rapidly advancing. Therefore, how to secure a large capacity between the floating gate and the control gate, which is a small memory cell area, is an important issue.

In order to increase the capacitance between the floating gate and the control gate, the gate insulating film between them should be thinned or its dielectric constant should be increased, or the facing area between the floating gate and the control gate should be increased. It needs to be large.
However, thinning the gate insulating film has a limit in reliability. Increasing the dielectric constant of the gate insulating film may be achieved by using, for example, a silicon nitrogen film or the like instead of the silicon oxide film, but this is also not practical because it has a problem mainly in reliability. Therefore, in order to secure a sufficient capacitance, it is necessary to secure the overlap area of the floating gate and the control gate to a certain value or more. This is an obstacle to reducing the area of the memory cell and increasing the capacity of the EEPROM.

On the other hand, in the EEPROM disclosed in Japanese Patent No. 2877462, a memory transistor is constructed by utilizing the sidewalls of a plurality of columnar semiconductor layers which are separated by lattice-striped grooves and arranged in a matrix on a semiconductor substrate. To be done. That is, the memory transistor has a drain diffusion layer formed on the upper surface of each columnar semiconductor layer, a common source diffusion layer formed at the bottom of the groove, a charge storage layer surrounding the entire side wall of each columnar semiconductor layer, and a control gate. The control gate is formed by continuously disposing the plurality of columnar semiconductor layers in one direction to form a control gate line. Also, a bit line connected to the drain diffusion layers of the plurality of memory transistors in a direction intersecting the control gate line is provided.
The charge storage layer and the control gate of the memory transistor described above are formed below the columnar semiconductor layer. Further, in the one-transistor / one-cell configuration, when the memory transistor is in the over-erased state, that is, when the read potential is 0 V and the threshold value is negative, the cell current flows even if it is not selected, which is inconvenient. Is. In order to reliably prevent this, a select gate transistor having a gate electrode formed so as to surround at least a part of the periphery of the columnar semiconductor layer is provided over the memory transistor. As a result, the memory cell of the EEPROM of the conventional example has the charge storage layer and the control gate formed by surrounding the columnar semiconductor layer by utilizing the side wall of the columnar semiconductor layer, so that the charge storage layer can be formed with a small occupied area. It is possible to secure a sufficiently large capacitance between the control gates. The drain diffusion layer connected to the bit line of each memory cell is formed on the upper surface of the columnar semiconductor layer, and is completely electrically separated by the groove. Further, the element isolation region can be made small, and the memory cell size can be made small. Therefore, it is possible to obtain a large capacity EEPROM in which memory cells having excellent writing and erasing efficiency are integrated.

FIG. 202 shows a case where the columnar silicon layer 2 has a columnar shape, that is, a top surface has a circular shape. The outer shape of the columnar silicon layer may not be cylindrical. Hereinafter, a conventional example will be described with reference to the drawings. FIG. 202
Is a plan view of a conventional EEPROM, and FIG. 203 is a sectional view taken along the line AA 'and BB' of FIG. Note that FIG.
In 02, the select gate line in which the gate electrodes of the select gate transistors are continuously formed is not shown because it becomes complicated. In the conventional example, a plurality of columnar p-type silicon layers 2 separated by lattice-striped grooves 3 are arranged in a matrix on a p-type silicon substrate 1, and each columnar silicon layer 2 serves as a memory cell region. Each silicon layer 2
A drain diffusion layer 10 is formed on the upper surface of the groove 3, a common source diffusion layer 9 is formed on the bottom of the groove 3, and an oxide film 4 having a predetermined thickness is buried in the bottom of the groove 3. Further, a floating gate 6 is formed below the pillar-shaped silicon layer 2 via a tunnel oxide film 5 so as to surround the circumference of the pillar-shaped silicon layer 2, and a control gate 8 is formed outside the floating gate 6 via an interlayer insulating film 7. Formed to form a memory transistor.
Here, the control gate 8 is shown in FIG. 202 and FIG. 203 (b).
As shown in, the memory cells are continuously arranged for a plurality of memory cells in one direction, and control gate lines or word lines WL (WL
1, WL2, ...). A gate electrode 32 is formed on the pillar-shaped silicon layer 2 via a gate oxide film 31 so as to surround the periphery of the pillar-shaped silicon layer 2 like the memory transistor.
Are arranged to form a select gate transistor. Similar to the control gate 8 of the memory cell, the gate electrode 32 of this transistor is continuously arranged in the same direction as the control gate line to form a select gate line.

In this way, the memory transistor and the select gate transistor are embedded and formed in a state of being superposed inside the trench. One end of the control gate line is left on the surface of the silicon layer as a contact portion 14, and the select gate line is also left a contact portion 15 on the silicon layer at the end opposite to the control gate. The Al wirings 13 and 16 to be the line CG are in contact with each other. A common source diffusion layer 9 of the memory cell is formed on the bottom of the groove 3, and a drain diffusion layer 10 of each memory cell is formed on the upper surface of each columnar silicon layer 2. The CVD oxide film 11 is formed on the substrate of the memory cell thus formed.
And a contact hole is opened in the drain diffusion layer 1 of the memory cell in the direction intersecting the word line WL.
Al to be the bit lines BL (BL1, BL2, ...) Connecting 0s in common
The wiring 12 is provided. At the time of patterning the control gate line, P is formed at the position of the columnar silicon layer at the end of the cell array.
A mask made of EP is formed, and a contact portion 14 made of a polycrystalline silicon film that is continuous with the control gate line is left on the surface of the mask. A is formed at the same time as the bit line BL.
The Al wiring 13 serving as a word line is brought into contact with the l film.

A specific manufacturing process example for obtaining the structure corresponding to FIG. 203 (a) will be described with reference to FIGS. 204 (a) to 207 (g). A wafer in which a p-type silicon layer 2 having a low impurity concentration is epitaxially grown on a p-type silicon substrate 1 having a high impurity concentration is used, a mask layer 21 is deposited on the surface thereof, and a photoresist pattern 22 is formed by a known PEP process. Then, the mask layer 21 is etched using this (FIG. 203 (a)). Then, using the mask layer 21, the silicon layer 2 is etched by the reactive ion etching method to form the lattice-stripe-shaped grooves 3 having a depth reaching the substrate 1. Thereby, the silicon layer 2
Are columnar and separated into islands. Then CVD
A silicon oxide film 23 is deposited by the method and is left on the side wall of each columnar silicon layer 2 by anisotropic etching. Then, by ion implantation of n-type impurities, a drain diffusion layer 10 is formed on the upper surface of each columnar silicon layer 2, and a common source diffusion layer 9 is formed on the bottom of the groove (FIG. 204).
(B)). Then, after removing the oxide film 23 around each columnar silicon layer 2 by isotropic etching,
Each silicon layer 2 using oblique ion implantation as needed
Channel ion implantation is performed on the side wall of. Instead of the channel ion implantation, an oxide film containing boron may be deposited by the CVD method and boron diffusion from the oxide film may be used. Then, a CVD silicon oxide film 4 is deposited, and this is etched by isotropic etching to fill the bottom of the groove 3 with an oxide film having a predetermined thickness.

Then, a tunnel oxide film 5 having a thickness of, for example, about 10 nm is formed around each silicon layer 2 by thermal oxidation, and then a first-layer polycrystalline silicon film is deposited. This first
The layer polycrystalline silicon film is etched by anisotropic etching to leave the lower side wall of the columnar silicon layer 2 and form a floating gate 6 surrounding the silicon layer 2 (FIG. 20).
5 (c)). Then, an interlayer insulating film 7 is formed on the surface of the floating gate 6 formed around each columnar silicon layer 2.
The interlayer insulating film 7 is, for example, an ONO film. Specifically, after the surface of the floating gate 6 is oxidized to a predetermined thickness, a silicon nitride film is deposited by a plasma CVD method and the surface thereof is thermally oxidized to form an ONO film. Then, the second-layer polycrystalline silicon film is deposited and etched by anisotropic etching, so that the pillar-shaped silicon layer 2 is also formed.
The control gate 8 is formed in the lower part of (FIG. 205 (d)).
At this time, the control gate 8 sets the distance between the pillar-shaped silicon layers 2 to
By setting the vertical direction in FIG. 202 to a predetermined value or less in advance, the control gate lines are formed continuously in that direction without using a mask process. Then, after removing the unnecessary interlayer insulating film 7 and the tunnel oxide film 2 thereunder by etching, a CVD silicon oxide film 111 is deposited, and this is etched to the middle of the groove 3, that is, the floating gate 7 and control of the memory cell. The gate 8 is buried until it is hidden (FIG. 206 (e)). Then, a gate oxide film 31 of about 20 nm is formed on the exposed columnar silicon layer 2 by thermal oxidation, a third-layer polycrystalline silicon film is deposited, and this is etched by anisotropic etching to form a MO film.
The gate electrode 32 of the S transistor is formed (FIG. 206).
(F)). This gate electrode 32 is also continuously patterned in the same direction as the control gate line to form a select gate line.
The select gate line can be continuously formed by self-alignment, but it is more difficult than the case of the control gate 8 of the memory cell. This is because the memory transistor section has a two-layer gate, whereas the select gate transistor has a single-layer gate, so that the gate electrode spacing between adjacent cells is wider than the control gate spacing. Therefore, in order to ensure the continuity of the gate electrode 32, this is formed as a two-layer polycrystalline silicon structure, and the first polycrystalline silicon film is left only in the portion where the gate electrode is connected in the mask process, and the next polycrystalline silicon film is formed. On the other hand, the technique of leaving the side wall may be used. Note that a mask is formed at the time of etching the polycrystalline silicon film so that the contact portions 14 and 15 are formed on the upper surface of the columnar silicon layer at different ends of the control gate line and the select gate line. Finally CVD
After depositing a silicon oxide film 112 and performing a planarization process if necessary, a contact hole is opened, and Al wiring 12 serving as a bit line BL and an Al wiring 13 serving as a control gate line CG are formed by vapor deposition and patterning of Al. And the Al wiring 16 to be the word line WL is formed at the same time (FIG. 207).
(G)).

FIG. 208 (a) shows an EEPR of this conventional example.
The cross-sectional structure of the main part of one memory cell of the OM is shown in FIG.
Shows an equivalent circuit. The operation of the conventional EEPROM will be briefly described with reference to FIGS. First, in the case of using hot carrier injection for writing, a sufficiently high positive potential is applied to the selected word line WL, and a predetermined positive potential is applied to the selection control gate line CG and the selected bit line BL. As a result, the select gate transistor Qs
A positive potential is transmitted to the drain of the memory transistor Qc via the memory transistor Qc, a channel current is flown in the memory transistor Qc, and hot carrier injection is performed. As a result, the threshold value of the memory cell moves in the positive direction. For erasing, the selection control gate CG is set to 0 V, a high positive potential is applied to the word line WL and the bit line BL, and electrons in the floating gate are emitted to the drain side. In the case of batch erasing, a high positive potential can be applied to the common source to emit electrons to the source side. As a result, the threshold value of the memory cell moves in the negative direction. In the read operation, the select gate transistor Qs is turned on by the word line WL, the read potential of the control gate line CG is applied, and "0" or "1" discrimination is performed depending on the presence or absence of current.
When FN tunneling is used for electron injection, a high positive potential is applied to the selection control gate line CG and the selection word line WL to set the selection bit line BL to 0 V and electrons are injected from the substrate to the floating gate. Further, according to this conventional example, since there is the select gate transistor, an EEPROM which does not malfunction even in the overerased state can be obtained.

By the way, in this conventional example, FIG.
As shown in (a), there is no diffusion layer between the select gate transistor Qs and the memory transistor Qc. This is because it is difficult to selectively form the diffusion layer on the side surface of the columnar silicon layer. Therefore, FIG.
In the structures (b) and (b), it is desirable that the isolation oxide film between the gate portion of the memory transistor and the gate portion of the select gate transistor be as thin as possible. In particular, when hot electron injection is used, the isolation oxide film thickness needs to be about 30 to 40 nm in order to transmit a sufficient “H” level potential to the drain portion of the memory transistor. Such a minute interval is practically difficult only by burying an oxide film by the CVD method described in the above manufacturing process. Therefore, the filling with the CVD oxide film leaves the floating gate 6 and the control gate 8 exposed, and a thin oxide film is simultaneously formed on the exposed portions of the floating gate 6 and the control gate 8 in the gate oxidation process for the select gate transistor. Method is preferred. Further, according to the conventional example, since the pillar-shaped silicon layer is arranged with the lattice-stripe-shaped groove bottom as an isolation region, and a memory cell having a floating gate formed so as to surround the circumference of the pillar-shaped silicon layer is formed, Highly integrated EE with a small memory cell occupation area
A PROM is obtained. Moreover, despite the small occupied area of the memory cell, a sufficiently large capacitance can be secured between the floating gate and the control gate. In the conventional example, the control gate of each memory cell is formed continuously in one direction without using a mask. This is possible only if the arrangement of the pillar-shaped silicon layers is not symmetrical.
That is, by making the distance between the columnar silicon layers adjacent to each other in the word line direction smaller than that in the bit line direction, the control gate lines which are separated in the bit line direction and are connected to the word line direction are automatically obtained without a mask. ..

On the other hand, for example, when the columnar silicon layers are arranged symmetrically, the PEP process is required. More specifically, a second-layer polycrystalline silicon film is deposited thickly, and a PEP process is performed, followed by selective etching so as to leave it in a portion to be continued as a control gate line. Then, a third-layer polycrystalline silicon film is deposited, and etching is performed with the sidewall left, as described in the conventional example. Further, even if the pillar-shaped silicon layers are not symmetrically arranged, it may not be possible to automatically form a continuous control gate line as in the conventional example depending on the distance of the arrangement. Even in such a case, the control gate line continuous in one direction may be formed by using the mask process as described above.
Further, although the memory cell having the floating gate structure is used in the conventional example, the charge storage layer does not necessarily have to be the floating gate structure, and the charge storage layer is realized by trapping in the multilayer insulating film, for example, the MNOS structure. It is also effective in cases.

FIG. 209 is a sectional view corresponding to FIG. 203 (a) when a memory cell having the MNOS structure is used.
The laminated insulating film 24 serving as a charge storage layer has a laminated structure of a tunnel oxide film and a silicon nitride film, or a structure in which an oxide film is further formed on the surface of the nitride film. FIG. 210 shows an example in which the memory transistor and the select gate transistor are reversed in the conventional example, that is, the columnar silicon layer 2
203A is a cross-sectional view corresponding to FIG. 203A, in which the select gate transistor is formed in the lower part of FIG. This structure in which the select gate transistor is provided on the common source side can be adopted when the hot electron injection method is used as the writing method. FIG. 211 shows a conventional example in which a plurality of memory cells are formed in one columnar silicon layer. The parts corresponding to those of the above-mentioned conventional example are denoted by the same reference numerals as those of the above-mentioned conventional example, and detailed description thereof is omitted. In this conventional example, a select gate transistor Qs1 is formed at the bottom of the pillar-shaped silicon layer 2, three memory transistors Qc1, Qc2, Q3c are stacked thereon, and a select gate transistor Qs2 is further formed thereon. is doing.
This structure is basically obtained by repeating the manufacturing process described above. In the conventional example described with reference to FIGS. 210 and 211, the MNOS structure can be used as the memory transistor instead of the floating gate structure.

As described above, according to the prior art, a memory cell using a memory transistor having a charge storage layer and a control gate is formed by utilizing the side wall of the columnar semiconductor layer separated by the lattice stripe groove. As a result, a sufficiently large capacitance is secured between the control gate and the charge storage layer, and the occupied area of the memory cell is reduced to achieve high integration.
A PROM can be obtained.

[0015]

However, when a plurality of memory cells are connected in series to one columnar semiconductor layer and the thresholds of the memory cells are considered to be the same, the data is read to the control gate line CG. During a read operation in which a potential is applied and "0" or "1" is discriminated depending on the presence or absence of a current, in the memory cells located at both ends connected in series, the back bias effect from the substrate causes a significant change in the threshold value. Become.
As a result, the number of memory cells connected in series is restricted on the device, which becomes a problem when the capacity is increased.

In the conventional example, the charge storage layer and the control gate are formed in self-alignment with the columnar semiconductor layer.
In consideration of increasing the capacity of the cell array, it is preferable to form the columnar semiconductor layer with the minimum processing size. When a floating gate is used as the charge storage layer, the relationship of capacitive coupling among the floating gate, the control gate, and the substrate is as follows: the area of the outer periphery of the columnar semiconductor layer and the area of the outer periphery of the floating gate; It is determined by the thickness of the tunnel oxide that insulates and the thickness of the interlayer insulating film that insulates the floating gate and the control gate. In the conventional example, the side wall of the columnar semiconductor layer is used to have the charge storage layer and the control gate formed so as to surround the columnar semiconductor layer, and a sufficiently large capacitance can be secured between the charge storage layer and the control gate with a small occupied area. However, the capacitance between the charge storage layer and the control gate is simple when the columnar semiconductor layer is formed with the minimum processing size and the tunnel oxide film thickness and the interlayer insulating film thickness are fixed. The area of the outer circumference of the floating gate, that is, the film thickness of the floating gate. Therefore,
It is difficult to increase the capacitance between the charge storage layer and the control gate without increasing the occupied area of the memory cell. In other words, it is difficult to increase the ratio of the capacitance of the floating gate and the control gate to the capacitance of the floating gate and the island-shaped semiconductor layer without increasing the occupied area of the memory cell.

The present invention has been made in view of the above problems, and improves the degree of integration by reducing the influence of the back bias effect of a semiconductor memory device having a charge storage layer and a control gate, and occupies an area occupied by memory cells. The capacitance ratio between the charge storage layer and the control gate is further increased without increasing, and the iterative history of the thermal history of each memory cell transistor due to the manufacturing process is minimized to reduce the variation in the characteristics of the memory cell. It is an object of the present invention to provide a method of manufacturing a semiconductor memory device that suppresses the semiconductor memory device.

[0018]

According to the present invention, a step of forming at least one island-shaped semiconductor layer on a semiconductor substrate, a step of forming a tunnel insulating film on the surface of the island-shaped semiconductor layer, and a step of forming the tunnel A step of forming a sidewall spacer made of a first conductive film divided in the height direction on an insulating film, and an impurity diffusion layer by introducing impurities into the divided first conductive film in a self-aligned manner And a step of forming
A step of forming an interlayer capacitance film and a second conductive film on the conductive film, so that the semiconductor substrate, at least one island-shaped semiconductor layer, and all or part of the periphery of the sidewall of the island-shaped semiconductor layer are formed. At least one memory cell including a charge storage layer and a control gate, and a semiconductor memory device for manufacturing a semiconductor memory device in which at least one of the memory cells is electrically insulated from the semiconductor substrate. A manufacturing method is provided.

Further, according to the present invention, a step of forming at least one island-shaped semiconductor layer on the semiconductor substrate, a step of forming a tunnel insulating film on the surface of the island-shaped semiconductor layer, and a step of forming the tunnel insulating film on the tunnel insulating film. A step of forming a charge storage layer made of a laminated insulating film, a step of forming a sidewall spacer made of a first conductive film divided in the height direction on the charge storage layer, and a step of forming the divided first conductive film. A step of introducing an impurity into the film in a self-aligning manner to form an impurity diffusion layer, whereby the semiconductor substrate, at least one island-shaped semiconductor layer, and all or around the sidewalls of the island-shaped semiconductor layer are formed. At least one memory cell formed of a charge storage layer and a control gate formed in part, and at least one of the memory cells is electrically insulated from the semiconductor substrate. Method of manufacturing a semiconductor memory device to be manufactured.

Further, a step of forming at least one island-shaped semiconductor layer on the semiconductor substrate, a step of introducing an impurity into a part of the surface of the island-shaped semiconductor layer to form an impurity diffusion layer, and the island-shaped semiconductor. A step of forming a sidewall spacer made of a first conductive film divided in the height direction on the surface of the layer with an insulating film interposed therebetween.
At least one island-shaped semiconductor layer, at least one memory cell including a charge storage layer formed on all or part of the periphery of the sidewall of the island-shaped semiconductor layer, and a control gate, Provided is a method for manufacturing a semiconductor memory device, wherein at least one is electrically insulated from the semiconductor substrate to manufacture a semiconductor memory device.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION In a semiconductor memory device of the present invention, a plurality of memory cells each having a charge storage layer and a third electrode serving as a control gate are connected in series in a direction perpendicular to a surface of a semiconductor substrate. A semiconductor substrate and an impurity diffusion layer formed on the sidewalls of a plurality of island-shaped semiconductor layers arranged in a matrix on the semiconductor substrate and arranged in a matrix pattern, and an impurity diffusion layer arranged in the island-shaped semiconductor layer The semiconductor substrate and the island-shaped semiconductor layer are electrically separated by the impurity diffusion layer as a source or a drain, and the control gate is continuous with respect to a plurality of island-shaped semiconductor layers in one direction, and is formed on the semiconductor substrate surface. In contrast, it has a control gate line which is a third wiring arranged in a horizontal direction, is electrically connected to the impurity diffusion layer in a direction intersecting with the control gate line, and is in a horizontal direction with respect to the semiconductor substrate surface. Having a bit line which is the fourth wiring formed by location.

Implementation in plan view of a memory cell array
Modes A plan view of a memory cell array in a semiconductor memory device of the present invention will be described with reference to FIGS. 1 to 8
Is an EEPROM having a floating gate as a charge storage layer
9 is a plan view showing a memory cell array of FIG. 9, FIG. 9 is a memory cell array having a MONOS structure having a laminated insulating film as a charge storage layer, and FIG. 11 is a plan view showing a memory cell array having an SRAM structure having a MIS transistor as a charge storage layer. In these figures, a gate electrode for selecting a memory cell (hereinafter referred to as "selection gate")
As the second wiring or the fifth wiring as a selection gate line,
The layout of the control gate line which is the third wiring, the bit line which is the fourth wiring, and the source line which is the first wiring will be described.

First, a plan view showing a memory cell array of an EEPROM having a floating gate as a charge storage layer will be described. FIG. 1 shows an arrangement in which columnar island-shaped semiconductor portions forming memory cells are arranged, for example, at respective intersections of two kinds of parallel lines, and a first memory cell for selecting and controlling each memory cell is formed. The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer represent memory cell arrays arranged in parallel to the substrate surface. Further, by changing the arrangement interval of the island-shaped semiconductor portions in the AA ′ direction which is the direction intersecting with the fourth wiring layer 840 and the BB ′ direction which is the direction of the fourth wiring layer 840, each memory is changed. The second conductive film which is the control gate of the cell is unidirectionally
The third wiring layer is formed continuously in the −A ′ direction.
Similarly, the second conductive film which is the gate of the select gate transistor is continuously formed in one direction to form the second wiring layer. Further, a terminal for electrically connecting to the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is connected to, for example, the AA ′ direction in FIG. And a terminal for electrically connecting to the second wiring layer and the third wiring layer is provided at an end portion on the A side of the memory cell connected in the AA ′ direction in FIG. The fourth wiring layer 840 arranged on the side opposite to the substrate of the semiconductor island portion is electrically connected to each of the cylindrical island semiconductor portions forming the memory cell. For example, in FIG. A fourth wiring layer 840 is formed in a direction intersecting the second wiring layer and the third wiring layer.
Are formed. The terminal for electrically connecting to the first wiring layer is formed of an island-shaped semiconductor portion, and the terminal for electrically connecting to the second wiring layer and the third wiring layer is It is formed of a second conductive film which covers the island-shaped semiconductor portion. The terminals for electrically connecting to the first wiring layer, the second wiring layer and the third wiring layer are respectively the first contact portion 910, the second contact portion 921,
924 and the third contact portions 932 and 933.

In FIG. 1, the first wiring layer 810 is drawn out to the upper surface of the semiconductor memory device via the first contact portion 910. Note that the columnar island-shaped semiconductor portions forming the memory cells do not have to be arranged as shown in FIG. 1, and the memory cells may be arranged as long as the above-mentioned positional relationship of wiring layers and electrical connection are provided. The array of the cylindrical island-shaped semiconductor portions forming the is not limited. The island-shaped semiconductor portion connected to the first contact portion 910 is arranged at all end portions on the A ′ side of the memory cells connected in the AA ′ direction in FIG. May be arranged in a part or all of the part, or in any of the island-shaped semiconductor parts forming the memory cells connected in the AA ′ direction which is the direction intersecting with the fourth wiring layer 840. You may have. Further, the island-shaped semiconductor portion covered with the second conductive film connected to the second contact portions 921 and 924 and the third contact portions 932 and 933 is located on the side where the first contact portion 910 is not arranged. It may be arranged at the end portion, may be arranged continuously at the end portion on the side where the first contact portion 910 is arranged, or may be a direction crossing the fourth wiring layer 840 AA It may be arranged in any of the island-shaped semiconductor portions forming the memory cells connected in the direction ', and the second contact portions 921 and 9 are formed.
24, the third contact portion 932 and the like may be arranged separately. First wiring layer 810 and fourth wiring layer 840
May have any width and shape as long as a desired wiring can be obtained.

Further, the first wiring layer arranged on the substrate side of the island-shaped semiconductor portion is formed in self-alignment with the second wiring layer and the third wiring layer formed of the second conductive film. In this case, the island-shaped semiconductor portion serving as a terminal for electrically connecting to the first wiring layer is electrically connected to the second wiring layer and the third wiring layer formed of the second conductive film. Although separated,
It may be in contact with the insulating film. For example, in FIG. 1, the first conductive film is formed on a part of the side surface of the island-shaped semiconductor portion to which the first contact portion 910 is connected via an insulating film, and the first conductive film forms a memory cell. The second conductive film is formed between the island-shaped semiconductor portion and the second conductive film, and the second conductive film is formed on the side surface of the first conductive film with an insulating film interposed therebetween. The second wiring layer and the third wiring layer, which are continuously formed, are connected to each other in the AA ′ direction which is a direction intersecting with the wiring layer 840. At this time,
The shapes of the first and second conductive films formed on the side surfaces of the island-shaped semiconductor portion do not matter. In addition, the distance between the island-shaped semiconductor portion serving as a terminal for electrically connecting to the first wiring layer and the first conductive film in the island-shaped semiconductor portion where the memory cell is formed is set to, for example, the second By setting the thickness of the conductive film to twice or less, it is possible to remove all the first conductive film on the side surface of the island-shaped semiconductor portion, which serves as a terminal for electrically connecting to the first wiring layer.

In FIG. 1, the second and third contact portions are formed on the second conductive films 521 to 524 formed so as to cover the tops of the island-shaped semiconductor portions, but they can be connected to each other. Then, the shapes of the second and third wiring layers do not matter. In FIG. 1, the select gate transistor and the polycrystalline silicon film 530 that is the third electrode are omitted because they are complicated. Further, the cross sections used in the manufacturing process examples, that is, the AA 'cross section, the BB' cross section, the CC 'cross section, the D-
The D'section, the EE 'section, and the FF' section are also shown.

In FIG. 2, the columnar island-shaped semiconductor portions forming the memory cells are arranged so that, for example, two kinds of parallel lines are arranged at the intersections of the parallel lines, which are not orthogonal to each other. The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer for selecting and controlling represent a memory cell array arranged parallel to the substrate surface.
In addition, A− that is a direction intersecting with the fourth wiring layer 840
By changing the arrangement interval of the island-shaped semiconductor portions in the A ′ direction and the BB ′ direction in the figure, the second conductive film which is the control gate of each memory cell is unidirectional, and in FIG. The third wiring layer is formed continuously in the 'direction. Similarly, the second conductive film which is the gate of the select gate transistor is continuously formed in one direction to form the second wiring layer. Further, a terminal for electrically connecting to the first wiring layer arranged on the substrate side of the island-shaped semiconductor portion is connected to, for example, A- in FIG.
Provided at the end on the A ′ side of the memory cell connected in the A ′ direction,
A terminal for electrically connecting to the second wiring layer and the third wiring layer is provided, for example, at the end on the A side of the memory cell connected in the AA ′ direction in FIG. The fourth wiring layer 840 arranged on the side opposite to the substrate is electrically connected to each of the columnar island-shaped semiconductor portions forming the memory cell. For example, in FIG. A fourth wiring layer 840 is formed in a direction intersecting the wiring layer and the third wiring layer. Further, the terminal for electrically connecting to the first wiring layer is formed of the island-shaped semiconductor portion, and the terminal for electrically connecting to the second wiring layer and the third wiring layer is
It is formed of a second conductive film which covers the island-shaped semiconductor portion. The terminals for electrically connecting to the first wiring layer, the second wiring layer, and the third wiring layer are respectively the first contact portion 910, the second contact portions 921, 924,
It is connected to the third contact portions 932 and 933.

Further, in FIG. 2, the first contact portion 9
The first wiring layer 810 is drawn out to the upper surface of the semiconductor memory device via 10. Note that the columnar island-shaped semiconductor portions forming the memory cells do not have to be arranged as shown in FIG. 2, but the memory cells may be arranged as long as there is a positional relationship between wiring layers and an electrical connection relationship as described above. The arrangement of the cylindrical island-shaped semiconductor portions forming the is not limited. The first contact portion 91
The island-shaped semiconductor portion connected to 0 is AA ′ in FIG.
Although it is arranged at all the end portions on the A ′ side of the memory cells connected in the direction, it may be arranged at a part or all of the end portion on the A side, or in the direction intersecting with the fourth wiring layer 840. Is A-
It may be arranged in any of the island-shaped semiconductor portions forming the memory cells connected in the A ′ direction. In addition, the second contact portions 921 and 924, the third contact portion 93
The island-shaped semiconductor portion which is connected to the second conductive film 2933 and is covered with the second conductive film may be disposed at an end portion on the side where the first contact portion 910 is not disposed, or the first contact portion 910. The part 910 may be continuously arranged at the end on the side where the part 910 is arranged, or may be a direction intersecting with the fourth wiring layer 840 A−
It may be arranged in any of the island-shaped semiconductor portions forming the memory cells connected in the A ′ direction, or the second contact portions 921 and 924, the third contact portion 932, etc. are divided and arranged. You may. The width and shape of the first wiring layer 810 and the fourth wiring layer 840 are not limited as long as desired wiring can be obtained. When the first wiring layer arranged on the substrate side of the island-shaped semiconductor portion is formed in a self-aligned manner with the second wiring layer and the third wiring layer formed of the second conductive film, The island-shaped semiconductor portion serving as a terminal for electrically connecting to the first wiring layer is electrically separated from the second wiring layer and the third wiring layer formed of the second conductive film. However, they may be in contact with each other through the insulating film. Figure 2
Then, a first conductive film is formed on a part of the side surface of the island-shaped semiconductor portion to which the first contact portion 910 is connected via an insulating film, and the first conductive film forms a memory cell. A second conductive film is formed on the side surface of the first conductive film with an insulating film interposed therebetween, and the second conductive film is a fourth conductive film. The second wiring layer and the third wiring layer, which are continuously formed, are connected in the AA ′ direction which is a direction intersecting the wiring layer 840. The shapes of the first and second conductive films formed on the side surfaces of the island-shaped semiconductor portion do not matter. In addition, the distance between the island-shaped semiconductor portion serving as a terminal for electrically connecting to the first wiring layer and the first conductive film in the island-shaped semiconductor portion where the memory cell is formed is set to, for example, the second By setting the thickness of the conductive film to twice or less, it is possible to remove all the first conductive film on the side surface of the island-shaped semiconductor portion, which serves as a terminal for electrically connecting to the first wiring layer.

In FIG. 2, the second and third contact portions are formed on the second conductive films 2521 to 2524 formed so as to cover the tops of the island-shaped semiconductor portions, but they can be connected to each other. Then, the shapes of the second and third wiring layers do not matter. The select gate transistor is omitted because it is complicated. Further, the cross sections used in the manufacturing process examples, that is, the AA 'cross section and the BB' cross section are also shown.

3 and 4 are different from FIGS. 1 and 2 in that the island-shaped semiconductor portion forming the memory cell has a quadrangular cross-sectional shape. Examples of different directions are shown. The cross-sectional shape of the island-shaped semiconductor portion is not limited to a circle or a quadrangle. For example, it may be oval, hexagonal or octagonal. However, if the size of the island-shaped semiconductor part is near the processing limit, even if it has a corner such as a square, hexagon, or octagon at the time of design, the corner will be rounded due to the photo process or etching process. The cross-sectional shape of the island-shaped semiconductor portion approaches a circle or an ellipse. In FIGS. 3 and 4, the select gate transistor is omitted because it is complicated.

In contrast to FIG. 1, FIG. 5 shows an example in which the number of memory cells formed in series in the island-shaped semiconductor portion forming the memory cells is two and no select gate transistor is formed. In FIG. 5, the cross sections used in the manufacturing process example, that is, the AA ′ cross section and the BB ′ cross section are also shown.

FIG. 6 shows an example in which the cross-sectional shape of the island-shaped semiconductor portion forming the memory cell is not a circle but an ellipse as compared with FIG. Here is an example.

FIG. 7 shows a case in which the direction of the major axis of the ellipse is the AA 'direction with respect to FIG. The direction of the major axis of this ellipse is not limited to the AA 'direction and the BB' direction, but may be any direction. Further, in FIGS. 6 and 7, the select gate transistor is omitted because it is complicated.

In contrast to FIG. 2, FIG. 8 shows polycrystalline silicon 521 to 524 which is the second conductive film in a region where a contact is made.
Is formed stepwise, and the insulating film and the like above the desired wiring layer are removed by anisotropic etching to form a contact portion in the desired wiring layer. A common contact portion is formed in the lead portion of the wiring layer. Also, an independent contact portion may be formed in each wiring layer. In FIG. 8, the cross section used in the manufacturing example, that is, H
-H 'cross section, I1-I1' cross section to I5-I5 'cross section are shown together. The arrangements and structures shown in FIGS. 1 to 8 can be used in various combinations.

FIG. 9 shows an example in which a laminated insulating film is used for the charge storage layer as in the MONOS structure,
The charge storage layer is the same as that shown in FIG. 1 except that the floating gate is replaced by a laminated insulating film. In FIG. 9, the cross sections used in the manufacturing process example, that is, the AA ′ cross section and the BB ′ cross section are shown together. Also, in FIG. 9, the select gate transistor is omitted because it is complicated.

FIG. 10 shows an example in which a MIS capacitor is used as a charge storage layer as in a DRAM, for example. The charge storage layer is changed from the floating gate to the MIS capacitor, and the bit line and the source line are parallel to each other. It is the same as FIG. 1 except that it is arranged. In FIG. 10, the cross sections used in the manufacturing process example, that is, the AA ′ cross section and the BB ′ cross section are shown together.

FIG. 11 shows an example in which a MIS transistor is used as a charge storage layer as in SRAM. FIG. 11 shows an arrangement in which cylindrical island-shaped semiconductor portions forming memory cells are arranged, for example, at intersections where two types of parallel lines intersect each other, and impurity diffusion for selecting and controlling each memory cell is performed. A first wiring layer formed of the layer 3721, a third wiring layer formed of the control gate 3514,
The fourth wiring layer serving as a bit line represents a memory cell array arranged parallel to the substrate surface. Second conductive film 3
The second wiring layer 3840 including the 512 and the third conductive film 3513 is wired in two directions, a vertical direction and a horizontal direction, with respect to the substrate surface. The shapes of the second, third and fourth wiring layers do not matter as long as they can be connected to each other. Further, in FIG. 11, a cross section used in the manufacturing process example, that is, J1-
The J1 ′ cross section, the J2-J2 ′ cross section, the K1-K1 ′ cross section and the K2-K2 ′ cross section are also shown. Note that in FIG. 11, the first wiring layer 3710, the first wiring layer 3850, terminals for electrically connecting to these wiring layers, and the fifth wiring layer 3850 are omitted because they are complicated. Further, in order to distinguish the island-shaped semiconductor layer 3110 from each wiring layer, the shape of the island-shaped semiconductor layer is circular, but the shape is not limited to this, and the opposite may be applied.

Implementation in cross-section of a memory cell array
Morphology Sectional views of a semiconductor memory device having a floating gate as a charge storage layer are shown in FIGS. Among these, the even numbered drawing is the AA 'sectional view of FIG. 1, and the odd numbered drawing is the BB'.
A sectional view is shown.

In the semiconductor memory device of the present invention, a plurality of pillar-shaped island-shaped semiconductor layers 110 are formed on the p-type silicon substrate 100.
Are arranged in a matrix, and a transistor having a second electrode or a fifth electrode serving as a selection gate is arranged above and below each of the island-shaped semiconductor layers 110, and a plurality of memory transistors are sandwiched between the selection gate transistors. Fig. 1
In FIGS. 2 to 39, for example, two transistors are arranged and each transistor is connected in series along the island-shaped semiconductor layer.
That is, the silicon oxide film 460, which is an eighth insulating film having a predetermined thickness, is arranged at the bottom of the groove between the island-shaped semiconductor layers, and the gate insulating film thickness is formed on the sidewalls of the island-shaped semiconductor layer so as to surround the periphery of the island-shaped semiconductor layer 110. A selection gate 500 is disposed via a gate to form a selection gate transistor, and silicon oxide, which is a third insulating film, is formed on the sidewall of the island semiconductor layer so as to surround the island semiconductor layer 110 above the selection gate transistor. A floating gate 510 is disposed through the film 420,
Further, a control gate 520 is disposed on the outer side of the control gate 520 via an interlayer insulating film 610 made of a multi-layered film to form a memory transistor. Further, a transistor having a fifth electrode 500 serving as a selection gate is arranged above the plurality of memory transistors similarly arranged.

Further, the select gate 500 and the control gate 520 are, as shown in FIGS. 1 and 13, continuously arranged for a plurality of transistors in one direction and are a second wiring or a fifth wiring. It serves as a selection gate line and a control gate line which is the third wiring. The source diffusion layer 71 of the memory cell is formed on the surface of the semiconductor substrate so that the active region of the memory cell is in a floating state with respect to the semiconductor substrate.
0 is further arranged, a diffusion layer 720 is arranged so that the active region of each memory cell is in a floating state, and a drain diffusion layer 725 for each memory cell is arranged on the upper surface of each island-shaped semiconductor layer 110. Has been done. An oxide film 460, which is an eighth insulating film, is exposed between the memory cells arranged in this manner so that the upper portion of the drain diffusion layer 725 is exposed.
And an Al wiring 840 serving as a bit line commonly connecting the drain diffusion layers 725 of the memory cells in the direction intersecting the control gate line. In addition, in FIG.
Although the Al wiring 840 is arranged in a state where the alignment is misaligned, it is preferable that the Al wiring 840 is arranged without the misalignment (the same applies hereinafter). The impurity concentration distribution of the diffusion layer 720 is not uniform, but, for example, by introducing impurities into the island-shaped semiconductor layer 110 and performing thermal diffusion treatment, the impurity concentration distribution gradually increases from the surface of the island-shaped semiconductor layer 110 toward the inside. It is preferable that the concentration becomes low. Thereby, the diffusion layer 72
The junction breakdown voltage between 0 and the island-shaped semiconductor layer 110 is improved, and the parasitic capacitance is also reduced. Similarly, regarding the impurity concentration distribution of the source diffusion layer 710, it is preferable that the impurity concentration distribution gradually decreases in the direction from the surface of the semiconductor substrate 100 to the inside of the semiconductor substrate. This improves the junction breakdown voltage between the source diffusion layer 710 and the semiconductor substrate 100, and also reduces the parasitic capacitance in the first wiring layer.

12 and 13 show an example in which the film thickness of the gate insulating film of the select gate transistor is equal to the film thickness of the gate insulating film of the memory transistor. 14
15 and FIG. 15 are different from FIG. 12 and FIG.
An example in which 10 is formed of a single layer film is shown. 16 and 17 are different from FIGS. 12 and 13 in that in the memory cell, the thickness of the control gate 520 in the semiconductor substrate in the horizontal direction is larger than that of the floating gate 510 in the horizontal direction, and An example in which the resistance can be easily reduced will be shown. FIG.
19 and FIG. 19, the surface of the silicon oxide film 420, which is the third insulating film, is different from that of FIGS.
An example in the case of being located outside the periphery of 10 is shown. Figure 2
0 and 21 are different from FIGS. 12 and 13 in that the gate of the select gate transistor is not formed by depositing the conductive film once, but is formed by depositing the conductive film multiple times, for example, twice. Indicates. 22 and 23 are similar to FIGS.
3 shows an example in which the materials of the control gate 520 and the floating gate 510 of the memory cell are different. 24 and 2
5 shows an example in which the outer peripheral size of the control gate 520 of the memory cell and the outer peripheral size of the gate 500 of the select gate transistor are different from those in FIGS. 12 and 13.
26 and 27 show an example in which the thickness of the gate insulating film of the select gate transistor is larger than that of the memory transistor. 28 and 29 are different from FIGS. 26 and 27 in that the silicon oxide film 420 that is the third insulating film and the silicon oxide film 4 that is the thirteenth insulating film.
An example in which the surface of 80 is located outside the periphery of the island-shaped semiconductor layer 110 is shown.

30 and 31 show an example in which the diffusion layer 720 is not arranged between the respective transistors. Figure 3
2 and FIG. 33, the diffusion layer 720 is not disposed, and the polycrystalline silicon film 530 that is the third electrode disposed between the gate electrodes 500, 510 and 520 of the memory transistor and the select gate transistor is shown. An example in the case of being formed is shown. 34 and 35 are the same as FIGS. 32 and 3.
3 shows an example in which the positions of the bottom and the top of the polycrystalline silicon film 530, which is the third electrode, are different from the position of the top of the gate 500 of the select gate transistor.
36 and 37, the source diffusion layer 710 is arranged so that the semiconductor substrate 100 and the island-shaped semiconductor layer 110 are connected, and the diffusion layer 720 is arranged so that the active regions of adjacent transistors are connected. In some cases, the source diffusion layer 710 and the semiconductor substrate or the island-shaped semiconductor layer 110 are caused by a potential difference between the potential of the source diffusion layer 710 given during reading or erasing and the potential given to the semiconductor substrate 100.
The island-shaped semiconductor layer 11 is formed by the depletion layer formed on the semiconductor substrate 100 or the island-shaped semiconductor layer 110 side of the PN junction composed of
0 and the semiconductor substrate 100 are in an electrically floating state, and the potential of the diffusion layer 720 and the island-shaped semiconductor layer 110.
The island-shaped semiconductor layer 1 of the PN junction composed of the diffusion layer 720 and the island-shaped semiconductor layer 110 due to the potential difference due to the potential applied to the
An example in which the active regions of adjacent transistors are electrically isolated by the depletion layer formed on the 10 side is shown. Figure 3
8 and 39, the island-shaped semiconductor layer 110 is the source diffusion layer 7.
Although the floating state is shown by 10, the active region of each memory cell is not electrically isolated by the diffusion layer 720.

40 to 51 are sectional views of a semiconductor memory device having a laminated insulating film as a charge storage layer. Among these, the even drawing shows the AA ′ sectional view of FIG. 9, and the odd drawing shows the BB ′ sectional view. The semiconductor memory device of FIGS. 40 to 51 is the same as the semiconductor memory device of FIGS. 12 to 35, except that the charge storage layer is replaced with the laminated insulating film from the floating gate. 42 and 43 are the same as FIGS.
On the other hand, the case where the film thickness of the laminated insulating film is thicker than the gate film thickness of the select gate transistor is shown for 1. 44 and 4
5 shows an example in which the film thickness of the laminated insulating film is thinner than the gate film thickness of the select gate transistor, as compared with FIGS. 52 to 57 are cross-sectional views of the semiconductor memory device having the MIS capacitor as the charge storage layer. Among these, the even numbered drawing shows the AA ′ sectional view of FIG. 10, and the odd numbered drawing shows the BB ′ sectional view.

In the semiconductor memory device of FIGS. 52 to 57, the charge storage layer is changed from the floating gate to the MIS capacitor, the diffusion layer is arranged on the side of the memory capacitor, and the fourth wiring is the bit line. 12 to 29, except that the first wiring source lines are arranged in parallel. 58 to 61 are cross-sectional views of a semiconductor memory device having a MIS transistor as a charge storage layer. These are J1-J1 ', J2-J2' and K of FIG. 11, respectively.
1 shows a cross-sectional view of 1-K1 'and K2-K2'. Fig. 58
61 is a p-type silicon substrate 310.
A plurality of columnar island-shaped semiconductor layers 3110 are arranged in a matrix on 0, and as shown in FIGS. 58 and 60, two MIS transistors are arranged above and below each island-shaped semiconductor layer 3110. It has a structure in which transistors are connected in series along the island-shaped semiconductor layer. That is,
A memory gate 3511 is arranged on the sidewalls of the island-shaped semiconductor layer with a gate insulating film thickness 3431 so as to surround the island-shaped semiconductor layer 3110, and surrounds the island-shaped semiconductor layer 3110 above the memory gate transistor. In addition, a third electrode 3514 serving as a control gate is arranged on the sidewall of the island-shaped semiconductor layer with a gate insulating film thickness 3434 interposed therebetween. Also, the control gate 3514 is shown in FIG.
As shown in FIG. 7, a plurality of transistors in one direction are continuously arranged to form a control gate line which is a third wiring. Further, as shown in FIGS. 58 and 60, on the surface of the semiconductor substrate, a transistor which is electrically common to the transistors arranged in the lower stage so that the active region of the transistor is in a floating state with respect to the semiconductor substrate. Of the island-shaped semiconductor layer 31 such that the impurity diffusion layer 3710 of the transistor is arranged and the active region of each transistor is in a floating state.
Impurity diffusion layer 3721 is arranged in FIG. An impurity diffusion layer 3724 for each memory cell is arranged on the upper surface of each island-shaped semiconductor layer 3110. As a result, the transistors are connected in series along the island-shaped semiconductor layer 3110. Further, as shown in FIGS. 58 and 60, a fourth wiring layer 3840 serving as a bit line connecting the second impurity diffusion layer 3724 of the memory cell in the direction intersecting the control gate line is provided. In this example, four transistors and two transistors each composed of a pair of island-shaped semiconductor layers are provided.
The memory cell is composed of two high-resistance elements.
8 and FIG. 60, the second impurity diffusion layer 3721 formed in the island-shaped semiconductor layer facing the first conductive film 3511 which is the memory gate is the second conductive film 3512.
And a third conductive film 3513 through which they are connected to each other.

Further, as shown in FIGS. 59 and 61, the third conductive film 3 connected to the second impurity diffusion layers 3721 arranged in the respective island-shaped semiconductor layers 3110.
Reference numeral 513 is connected to the second wiring layer 3120 formed of an impurity diffusion layer which becomes a high resistance element, and each of the second wiring layers 312 is connected.
0 is connected to a fifth wiring which is an electrically common electrode. The first impurity diffusion layer 3710, which is electrically common to the memory cells adjacent in the direction of the fourth wiring layer 3840, is
It is electrically divided by a silicon oxide film 3471 which is an isolation insulating film, for example, an eleventh insulating film. An oxide film 3420, which is, for example, a third insulating film, is arranged between the memory cells and the wiring arranged in this way, and is insulated from each other. In this example, the memory cell is composed of four transistors and two high resistance elements formed on the sidewalls of the p-type island-shaped semiconductor layer, but a transistor formed on an n-type semiconductor may be used instead of the high resistance element. The structure is not limited to this as long as it can have a desired function.

Implementation in principle of operation of memory cell array
Form of the semiconductor memory device has a memory function depending on the state of charges accumulated in the charge accumulation layer. Below is an example of a memory cell array having a floating gate as a charge storage layer,
Read, write and erase will be described.

First, the read operation will be described. As an example of an array structure of a semiconductor memory device, a transistor including a second electrode as a gate electrode and a transistor including a fifth electrode as a gate electrode are provided as selection gate transistors, and charge accumulation is performed between the selection gate transistors. A plurality of memory cells each having a layer and including a third electrode as a control gate electrode, for example, L (L is a positive integer), an island-shaped semiconductor layer connected in series, and a plurality of island-shaped semiconductor layers. A plurality of, for example M × N, where M and N are positive integers, and in the memory cell array, a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are island-shaped semiconductor layers. Connected to one end of each, the first wiring is connected to the other end, and parallel to the semiconductor substrate,
A plurality of, for example N × L, third wirings arranged in a direction intersecting with the fourth wiring are connected to the third electrode of the memory cell, and the first wiring and the third wiring are parallel to each other. An example of the reading method in the case of arranging the above will be described. An equivalent circuit of the memory cell array structure is shown in FIG. 62, and the definition of memory cell writing is, for example, the threshold value of the memory cell is 0.5 V or more, and the definition of erasing is, for example, the threshold value of the memory cell is −0.5 V or less. Describe. As an example of the reading method, FIG.
FIG. 5 shows an example of the timing of the potential applied to each electrode during reading. For example, in a read operation in which the island-shaped semiconductor layer is formed of a P-type semiconductor, all the first wirings (1-1 to 1-
N) is applied with 0 V, and the fourth wiring (4-i) is connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell (i is 1 ≦ i
3V is applied to a positive integer of ≦ M, 0V is applied to the other fourth wiring (≠ 4-i), and the third wiring (3-jh connected to the third electrode connected to the selected cell) ) (J is a positive integer of 1 ≦ j ≦ N, h is a positive integer of 1 ≦ h ≦ L), and 0 V is applied to the third wiring (≠ 3-th) except the third wiring (3-jh). jh) is 3V, the second wiring (2-j) connected to the second electrode is 3V, and the fifth wiring (5-j) connected to the fifth electrode is 3V.
The second wiring (≠ 2-j) excluding the second wiring (2-j)
Or the fifth wiring (≠ 5-j) excluding the fifth wiring (5-j)
By applying 0V to at least one of the
Current flowing through the wiring (4-i) or the first wiring (1-j)
"0" or "1" is determined by the current flowing through the. By arranging the select gates above and below the plurality of memory cell parts in this way, when the memory cell transistor is in the over-erased state, that is, when the threshold value is in the negative state, the non-selected cells are read gate voltage. It is possible to prevent the cell current from flowing at 0V.

Further, it has an island-shaped semiconductor layer in which two memory cells each having a charge storage layer and having a third electrode as a control gate electrode are connected in series, and a plurality of island-shaped semiconductor layers, for example, M ×. In the case where N pieces (M and N are positive integers) are provided and a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate in the memory cell array, one end of each of the island-shaped semiconductor layers is provided. A plurality of, for example, N × 2, which are connected in parallel to the semiconductor substrate and are arranged in a direction intersecting with the fourth wiring. An example of a reading method when the first wiring is arranged in parallel with the third wiring when the third wiring is connected to the third electrode of the memory cell will be described. An equivalent circuit of the memory cell array structure is shown in FIG. 63, and the definition of memory cell writing is, for example, the threshold value of the memory cell is 4V or more, and the definition of erasing is, for example, the threshold value of the memory cell is 0.5V or more and 3V or less. Describe. As an example of the reading method,
FIG. 78 shows an example of the timing of the potential applied to each electrode during reading. For example, in a read operation in which the island-shaped semiconductor layer is formed of a P-type semiconductor, all the first wirings (1-1 to 1-
N) is applied with 0 V, and the fourth wiring (4-i) is connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell (i is 1 ≦ i
3V is applied to a positive integer of ≦ M, 0V is applied to the fourth wiring (≠ 4-i) other than the above, and the third wiring (3-j connected to the third electrode connected to the selected cell) -1) is given 5V and the third
0V is applied to the wiring (3-j-2) of the third wiring (3-j-1)
And the third wiring (≠ 3-j-1, except the third wiring (3-j-1)
By applying 0V to ≠ 3-j-2), the fourth wiring (4-i)
“0” or “1” is determined by the current flowing through the first wiring (1-j) (j is a positive integer of 1 ≦ j ≦ N).

Next, the write operation will be described. A transistor having a second electrode as a gate electrode and a transistor having a fifth electrode as a gate electrode are provided as selection gate transistors, a charge storage layer is provided between the selection gate transistors, and a third transistor is provided as a control gate electrode.
A plurality of memory cells each having an electrode (for example, L (L is a positive integer)) and an island-shaped semiconductor layer connected in series, and a plurality of island-shaped semiconductor layers, for example M × N (M, N Is a positive integer), and in the memory cell array, a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are connected to one end of each of the island-shaped semiconductor layers, A first wiring is connected to the other end, and a plurality of, for example, N × L third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring are When connected to the third electrode of the memory cell, the first wiring is arranged in parallel with the third wiring, and the F-N tunneling current (hereinafter F
An example of a writing method using (-N current) will be described. FIG. 62 shows an equivalent circuit of the above memory cell array structure. Further, FIG. 76 shows an example of the timing of the potential applied to each electrode in writing. When writing is performed by accumulating a certain amount of negative charges in the charge storage layer of the selected cell, for example, a write operation in which the island-shaped semiconductor layer is formed of a P-type semiconductor is connected to the island-shaped semiconductor layer including the selected cell. First to do
0V is applied to the first wiring (1-j) connected to the electrode of (where j is 1 ≦ j
≤N is a positive integer), 0 V is applied to the other first wirings (≠ 1-j), and the fourth wirings connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell (4 -i) (i is a positive integer 1≤i≤M)
To the third electrode (3-jh) (h is 1 ≦ h) connected to the third electrode connected to the selected cell. 20V to a positive integer of ≤L,
3 for the third wire (≠ 3-jh) excluding (3-jh) of the third wire
A second voltage applied to connect to the island-shaped semiconductor layer including the selected cell
0V is applied to the second wiring (2-j) connected to the electrode of, and 1V is applied to the fifth wiring (5-j) connected to the fifth electrode connected to the island-shaped semiconductor layer including the selected cell. , 0V is applied to the second wiring (≠ 2-j) excluding the second wiring (2-j) and the fifth wiring (≠ 5-j) excluding the fifth wiring (5-j). A state in which a high potential is applied only between the channel portion of the selected cell and the control gate is created, and electrons are injected from the channel portion into the charge storage layer by the FN tunneling phenomenon. By applying 3V to the fourth wiring (≠ 4-i) excluding the fourth wiring (4-i), the selection gate transistor including the fifth electrode in the island-shaped semiconductor layer not including the selection cell is Cut off and connect the third wiring (3-j-
h)) Non-selected cell diffusion layer and fourth wiring (≠ 4-i)
The electrical path to and is cut off, a channel is not formed, and writing is not performed.

Further, as an example of performing writing without cutting off the select gate transistor having the fifth electrode in the island-shaped semiconductor layer which does not include the selected cell, FIG. 81 shows the timing of the potential applied to each electrode. An example is shown. First connected to the first electrode connected to the island-shaped semiconductor layer including the selected cell
0V is applied to the wiring (1-j) of (where j is a positive integer of 1 ≦ j ≦ N), 0V is applied to the other first wiring (≠ 1-j), and the selected cell is selected. 0 V is applied to the fourth wiring (4-i) (i is a positive integer of 1 ≦ i ≦ M) connected to the fourth electrode connected to the island-shaped semiconductor layer including the other fourth wiring ( 7V is applied to ≠ 4-i) and the third wiring (3-j) connected to the third electrode connected to the selected cell
-h) (h is a positive integer of 1 ≤ h ≤ L) is given 20V, and the third wire (≠ 3-jh) except (3-jh) of the third wire is given 7V and selected 0 V is applied to the second wiring (2-j) connected to the second electrode connected to the island-shaped semiconductor layer including cells, and connected to the fifth electrode connected to the island-shaped semiconductor layer including selected cells. 5
20V is applied to the wiring (5-j) of the second wiring (the second wiring (≠ 2-j) except the second wiring (2-j) and the fifth wiring except the fifth wiring (5-j))
By applying 0V to (≠ 5-j), a potential difference of about 20V is generated between the channel portion of the selected cell and the control gate, and F-
Tunnel electrons are injected from the channel portion into the charge storage layer by the N tunneling phenomenon. It should be noted that 1 is provided between the control gate and the channel portion of the non-selected cell connected to the third wiring (3-jh).
Although a potential difference of about 3 V is generated, sufficient electron injection to change the threshold value of this cell cannot be performed within the write time of the selected cell, and therefore writing of this cell is not realized.

Further, there is an island-shaped semiconductor layer in which two memory cells each having a charge storage layer and having a third electrode as a control gate electrode are connected in series.
For example, when M × N (M and N are positive integers) are provided, and
In the memory cell array, a plurality of, for example, M fourth wirings arranged parallel to the semiconductor substrate are connected to one end of each of the island-shaped semiconductor layers, and the other end is connected to the first wiring. A plurality of, for example, N × 2, third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring are connected to the third electrode of the memory cell. In that case, an example of a writing method in which the first wiring is arranged in parallel with the third wiring and channel hot electrons (hereinafter referred to as CHE) is used will be described. An equivalent circuit of the above memory cell array structure is shown in FIG. 63, and FIG. 79 shows an example of the timing of the potential applied to each electrode during writing. When writing is performed by accumulating a certain amount of negative charges in the charge storage layer of the selected cell, for example, a write operation in which the island-shaped semiconductor layer is formed of a P-type semiconductor is connected to the island-shaped semiconductor layer including the selected cell. First wiring to connect to the first electrode
0V is applied to (1-j) (j is a positive integer of 1 ≦ j ≦ N), and 0V is applied to the other first wiring (≠ 1-j), and the island-shaped semiconductor layer including the selected cell is applied. The fourth wiring (4
-i) Apply 12V to (i is a positive integer of 1≤i≤M) and 0V to the other fourth wiring (≠ 4-i), and connect to the third electrode connected to the selected cell. 12V is applied to the third wire (3-j-1), and the third wire (≠ 3-j-1) excluding (3-j-1) of the third wire
Is applied to the charge storage layer of the selected cell due to the high potential applied to the third wiring (3-j-1) by generating CHE near the high potential side diffusion layer of the selected cell. Inject the generated electrons.

The erase operation will be described below. A transistor having a second electrode as a gate electrode and a transistor having a fifth electrode as a gate electrode are provided as select gate transistors, a charge storage layer is provided between the select gate transistors, and a third gate is provided as a control gate electrode. A plurality of memory cells each having an electrode, for example, L (L is a positive integer), and an island-shaped semiconductor layer connected in series are provided, and a plurality of the island-shaped semiconductor layers, for example, M × N (M, N). Is a positive integer), and in this memory cell array, a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are connected to one end of each of the island-shaped semiconductor layers. However, a first wiring is connected to the other end, and a plurality of, for example, N × L third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring are provided. The wiring is with the third electrode of the memory cell In case you are continued, and the first wires are arranged in parallel to the third wiring is described an example of the erasing method using F-N tunneling current (hereinafter referred to as F-N current). An equivalent circuit of the above memory cell array structure is shown in FIG. FIG. 77 shows an example of the timing of the potential applied to each electrode in erasing. The erase unit is one block or chip. When erasing is performed by changing the charge state of the charge storage layer of the selected cell and lowering the threshold value of the selected cell, for example, an erasing operation in which the island-shaped semiconductor layer is formed of a P-type semiconductor is performed in the island shape including the selected cell. 20 V is applied to the first wiring (1-j) connected to the first electrode connected to the semiconductor layer (j is a positive integer of 1 ≦ j ≦ N), and the other first wiring
0V is applied to the wiring (≠ 1-j), and the fourth wiring (4-i) connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell
20V is applied to (i is a positive integer of 1 ≦ i ≦ M), and the third wiring (3-jh) is connected to the third electrode connected to the selected cell (h is 1 ≦ i ≦ M).
0 volt is applied to a positive integer of h ≦ L, 0 V is applied to the third wiring except the third wiring (3-jh), and is applied to the second electrode connected to the island-shaped semiconductor layer including the selected cell. Second wiring to connect (2-j)
To the fifth electrode (5-j) connected to the fifth electrode connected to the island-shaped semiconductor layer including the selected cell, and 20 V is applied to the second wiring (2-j) except the second wiring (2-j). By applying 0 V to both the wiring (≠ 2-j) and the fifth wiring (≠ 5-j) excluding the fifth wiring (5-j), the electrons in the charge storage layer of the selected cell are F -Pull out by N tunneling phenomenon. Further, it has an island-shaped semiconductor layer in which two memory cells each having a charge storage layer and having a third electrode as a control gate electrode are connected in series, and a plurality of island-shaped semiconductor layers, for example, M × N ( (Where M and N are positive integers), and in the memory cell array, a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are connected to one end of each of the island-shaped semiconductor layers. However, the first wiring is connected to the other end, and a plurality of, for example, N × 2, third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring are provided. When the wiring is connected to the third electrode of the memory cell, the first wiring is arranged in parallel with the third wiring, and an example of an erasing method using an F-N current will be described.

An equivalent circuit of the above memory cell array structure is shown in FIG. 63, and FIG. 80 shows an example of the timing of the potential applied to each electrode during erasing. When erasing is performed by changing the charge state of the charge storage layer of the selected cell and lowering the threshold value of the selected cell, for example, an erasing operation in which the island-shaped semiconductor layer is formed of a P-type semiconductor is performed in the island shape including the selected cell. 3V is applied to the first wiring (1-j) connected to the first electrode connected to the semiconductor layer (j is a positive integer of 1 ≦ j ≦ N), and the other first wiring (≠ 1-
0V is applied to j) and the fourth wiring (4-i) connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell (i is 1 ≦ i ≦ M
Positive integer) is opened and the other 4th wiring (≠
4-i) gives an open state or 0 V, and applies -12 V to the third wiring (3-j-1) connected to the third electrode connected to the selected cell.
By applying 5 V to the third wiring (3-j-2) and 0 V to the other third wiring, the electrons in the charge storage layer of the selected cell are extracted by the FN tunneling phenomenon. .
The operation principle of the memory cell array may be such that the polarities of all electrodes are interchanged as in the case of an island-shaped semiconductor layer formed of an N-type semiconductor. At this time, the magnitude relationship of the potentials is opposite to that described above. Further, the above-mentioned read, write, and erase operations have been described for the case where the first wiring is arranged in parallel with the third wiring, but the case where the first wiring is arranged in parallel with the fourth wiring and Even when the wiring of 1 is made common to the entire array, it is possible to operate by applying a potential corresponding to each wiring.

The operation principle of other than the memory cell having the floating gate as the charge storage layer will be described below. 65 and 66 are equivalent circuit diagrams showing a part of the memory cell array of the MONOS structure shown in FIGS. 9 and 40 to 49. FIG. 65 shows one island-shaped semiconductor layer 1.
1 shows an equivalent circuit diagram of a memory cell array of MONOS structure arranged at 110. FIG. FIG. 66 shows a plurality of island-shaped semiconductor layers 1.
In the memory cell array in which 110 is arranged, FIG.
The connection relationship between the electrodes of each circuit element arranged in each island-shaped semiconductor layer 1110 and each wiring shown in FIG. A transistor having a twelfth electrode 12 as a gate electrode and a transistor having a fifteenth electrode 15 as a gate electrode as selection gate transistors, and a stacked insulating film as a charge storage layer between the selection gate transistors; A plurality of memory cells, for example, L memory cells, each having a thirteenth electrode (13-h) (h is a positive integer of 1 ≦ h ≦ L and L is a positive integer) as a control gate electrode, which are connected in series. In the semiconductor layer 110,
The fourteenth electrode 14 is connected to one end of each of the island-shaped semiconductor layers 1110, and the eleventh electrode 11 is connected to the other end. A plurality of such island-shaped semiconductor layers 1110, for example, M × N (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N. ), And in the memory cell array, a plurality of, for example, M, 14th wirings arranged in parallel to the semiconductor substrate are respectively connected to the above-mentioned 14th electrodes 14 provided in each island-shaped semiconductor layer 1110. To do. In addition, a plurality of, for example, N, arranged in a direction parallel to the semiconductor substrate and intersecting the fourteenth wiring 14 are provided.
The × L thirteenth wiring is the above-mentioned first wiring of each memory cell.
3 electrodes (13-h) (h is a positive integer of 1 ≦ h ≦ L). Also, a plurality of wires arranged in a direction intersecting with the fourteenth wiring,
For example, N number of eleventh wirings are formed in the respective island-shaped semiconductor layers 111.
The eleventh wiring is connected to the eleventh electrode 11 described above, and the eleventh wiring is arranged in parallel with the thirteenth wiring. Further, a plurality of, for example, N twelfth wirings arranged in a direction parallel to the semiconductor substrate and intersecting with the fourteenth wiring 14 are connected to the above-mentioned twelfth electrode 12 of each memory cell, Similarly, the fourteenth wiring 14 is parallel to the semiconductor substrate.
A plurality of, for example, N first, arranged in a direction intersecting with
The wiring 5 is the above-mentioned fifteenth electrode 15 of each memory cell.
Connect with.

67 and 68 show FIGS. 10 and 52-.
FIG. 58 is an equivalent circuit diagram showing a part of the memory cell array having the DRAM structure shown in FIG. 57. FIG. 67 shows an equivalent circuit diagram of a memory cell array of DRAM structure arranged on one island-shaped semiconductor layer 1110. FIG. 68 shows a memory cell array in which a plurality of island-shaped semiconductor layers 1110 are arranged,
65 shows a connection relationship between electrodes and wirings of each circuit element arranged in each island-shaped semiconductor layer 1110 shown in FIG. 65.

One memory cell is formed by connecting one transistor and one MIS capacitor in series. A memory cell having a twenty-third electrode 23 connected to one end of the memory cell, a twenty-first electrode 21 connected to the other end, and a twenty-second electrode 22 as a gate electrode, For example, two sets, which are connected as shown in FIG. 67, are connected from one island-shaped semiconductor layer 1110 to two 21st semiconductor layers.
Electrodes (21-1), (21-2) and two 22nd electrodes
(22-1) and (22-2) are provided, and the 23rd electrode 23 is provided at one end of the island-shaped semiconductor layer 1110. A plurality of such island-shaped semiconductor layers 1110, for example, M × N (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M,
j is a positive integer of 1 ≦ j ≦ N), and in this memory cell array, a plurality of, for example, M, twenty-third wirings arranged in parallel to the semiconductor substrate are provided in each island-shaped semiconductor layer 1110. To be connected to the above-mentioned twenty-third electrode 23. In addition, a plurality of, for example, 2 × N, arranged in a direction parallel to the semiconductor substrate and intersecting with the 23rd wiring 23.
The 22nd wiring of the book is connected to the above-mentioned 22nd electrodes (22-1) and (22-2) of each memory cell. In addition, a plurality of wires arranged in a direction intersecting with the 23rd wiring, for example, 2 × N
The twenty-first wiring of the book is connected to the above-mentioned twenty-first electrodes (21-1) and (21-2) of each memory cell. Note that FIG.
68 and FIG. 68 show an example in which two sets of memory cells are arranged in one island-shaped semiconductor layer 1110, but the number of memory cells arranged in one island-shaped semiconductor layer 1110 may be three or more, or Only one set is required.

As another example of the arrangement, an example in which a transistor, a MIS capacitor, a MIS capacitor, and a transistor are arranged in this order from the bottom of the island-shaped semiconductor layer 1110 will be described below. 69 and 70 are equivalent circuit diagrams showing a part of the memory cell array of the DRAM structure shown in FIGS. 11 and 49 to 52. FIG. 69 shows an equivalent circuit diagram of a memory cell array of DRAM structure arranged on one island-shaped semiconductor layer 1110. 68 shows a connection relationship between electrodes and wirings of each circuit element arranged in each island-shaped semiconductor layer 1110 shown in FIG. 65 in a memory cell array in which a plurality of island-shaped semiconductor layers 1110 are arranged. Similar to the above, the memory cell configuration is such that one transistor and one MIS capacitor are connected in series to form one memory cell, and the 23rd electrode 23 is connected to one end of this memory cell. The second end on the other end
The first electrode 21 is connected, and the 22nd electrode 22 is connected as a gate electrode. For example, two sets of the memory cells are connected as shown in FIG. 69 to form one island-shaped semiconductor layer 11
10 to two 21st electrodes (21-1) and (21-2) and two 22nd electrodes (22-1) and (22-2) are provided respectively, and one of the island-shaped semiconductor layers 1110 is provided. 23rd at the end
Electrode 23 is provided, and the 24th electrode 24 is provided at the other end. A plurality of such island-shaped semiconductor layers 1110, for example M × N (M and N are positive integers, and i is 1)
≤ i ≤ M, j is a positive integer of 1 ≤ j ≤ N), and in this memory cell array, a plurality of, for example, M, twenty-third, arranged in parallel to the semiconductor substrate. The wiring is connected to the above-mentioned 23rd electrode 23 provided in each island-shaped semiconductor layer 1110. Similarly, a plurality of, for example, M, twenty-fourth wirings arranged in parallel to the semiconductor substrate are connected to the above-mentioned twenty-fourth electrodes 24 provided in each island-shaped semiconductor layer 1110. In addition, a plurality of, for example, 2 × N-th 22nd wirings arranged in a direction parallel to the semiconductor substrate and intersecting the 23rd wiring 23 and the 24th wiring 24.
Wiring is the above-mentioned 22nd electrode (22-
1) and (22-2). Similarly, a plurality of, for example, 2 × N, twenty-first wirings arranged in a direction intersecting with the twenty-third wiring 23 and the twenty-fourth wiring 24 are the above-mentioned twenty-first electrodes (21 -1), connect with (21-2).

71 and 72, the diffusion layer 1720 is not disposed between the respective transistors, and the third diffusion layer 1720 is disposed between the gate electrodes 1500, 1510 and 1520 of the memory transistor and the select gate transistor. 49 is an equivalent circuit diagram of the memory cell array shown in FIGS. 33 to 35, 47, and 48 in the case where the polycrystalline silicon film 1530 which is the conductive film of FIG. In FIG. 71, as a structure arranged in one island-shaped semiconductor layer 1110, a polycrystalline silicon film 1530 which is a third conductive film arranged between the gate electrodes of each memory transistor and select gate transistor is formed. FIG. 72 shows an equivalent circuit diagram of the memory cell array in the case where the memory cell array is provided, and FIG. 72 shows an equivalent circuit when a plurality of island-shaped semiconductor layers 1110 are arranged. A transistor having a thirty-second electrode 32 as a gate electrode and a transistor having a thirty-fifth electrode 35 as a gate electrode are provided as selection gate transistors, and a charge storage layer is provided between the selection gate transistors. As an example, a plurality of memory cells, for example, L memory cells, each including a 33rd electrode (33-h) (h is a positive integer of 1 ≦ h ≦ L, L is a positive integer) are arranged in series, and each transistor is In the island-shaped semiconductor layer 1110 in which a transistor having a 36th electrode as a gate electrode is arranged between, the 34th electrode 34 is connected to one end of each of the island-shaped semiconductor layers 1110 and the other end thereof is connected. A 31st electrode 31 is connected to the
All six electrodes are connected to one and provided as the 36th electrode 36 in the island-shaped semiconductor layer 1110. A plurality of such island-shaped semiconductor layers 1110, for example, M × N (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N. ), And in the memory cell array, a plurality of, for example, M thirty-fourth wirings arranged in parallel to the semiconductor substrate are respectively provided with the above-mentioned thirty-fourth electrodes 34 provided in each island-shaped semiconductor layer 1110. Connecting. Also, a plurality of, for example, N × L thirty-third wirings arranged in a direction parallel to the semiconductor substrate and intersecting with the thirty-fourth wiring 34 are the above-mentioned thirty-third electrode (33- h). A plurality of, for example N, thirty-first wirings arranged in a direction intersecting with the thirty-fourth wiring are connected to the above-mentioned thirty-first electrode 31 provided in each island-shaped semiconductor layer 1110, and the thirty-first wiring. Are arranged in parallel with the 33rd wiring. Further, a plurality of, for example, N th 32nd wirings arranged in a direction parallel to the semiconductor substrate and intersecting with the 34th wiring 34 are connected to the above-mentioned 32nd electrode 32 of each memory cell, Similarly, a plurality of, for example, N th 35th wirings arranged in a direction parallel to the semiconductor substrate and intersecting with the 34th wiring 34 are connected to the 35th electrode 35 of each memory cell. To do. The above-mentioned 36th electrode 36 provided in each of the island-shaped semiconductor layers 1110 is connected to one by the 36th wiring. Each island-shaped semiconductor layer 1110
The 36th electrode 36 included in the above does not have to be connected to one by the 36th wiring, and the memory cell array may be divided into two or more and connected by the 36th wiring. That is, a structure may be adopted in which each 36th electrode is connected, for example, for each block.

FIGS. 73 and 74 are the same as FIGS.
FIG. 62 is an equivalent circuit diagram showing a part of the memory cell array having the SRAM structure shown in FIG. 61, showing an example in which the transistors constituting the memory cell are only NMOS. FIG. 73 shows two adjacent island-shaped semiconductor layers 1110.
FIG. 74 shows an equivalent circuit diagram of one SRAM-structured memory cell, and FIG. 74 shows an equivalent circuit when a plurality of memory cells are arranged. As shown in FIG. 73, two island-shaped semiconductor layers 110 in which transistors each having a 43rd electrode and a 45th electrode as gate electrodes are arranged in series are arranged adjacent to each other, and these four transistors are arranged as shown in FIG. Connect to each other.

Specifically, the 46th electrode (46-2) and the 45th electrode (45-1) of a transistor having the 43rd electrode (43-2) as a gate electrode are connected to each other, and the 43rd electrode ( 43-
46th electrode (4
6-1) and the 45th electrode (45-2) are connected. Further, in the two adjacent island-shaped semiconductor layers 1110, the 44th electrode is provided at one end of one island-shaped semiconductor layer 1110.
(44-1) is connected to another island-shaped semiconductor layer 1110
A forty-fourth electrode (44-2) is connected to one end of the. In the two island-shaped semiconductor layers 1110, the 44th electrode
A forty-first electrode 41 is connected as a common electrode to the other end portion where (44-1) and (44-2) are not connected. further,
Two high-resistance elements are connected to these four transistors and are shown in FIG.
And the 42nd electrode 42 is connected as a common electrode to the end on the side not connected to the transistor. A plurality of such island-shaped semiconductor layers 1110, for example, 2 × M × N (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N. In the memory cell array, a plurality of, for example, 2 × M, forty-fourth wirings arranged in parallel to the semiconductor substrate are provided in each of the island-shaped semiconductor layers 1110. electrode
(44-1) and (44-2) are connected respectively. In addition, a plurality of, for example, N, 43rd wirings arranged in a direction parallel to the semiconductor substrate and intersecting with the 44th wiring 44 are the 43rd electrodes (43-1) of the respective memory cells. ), (43
-Connect with 2). A plurality of, for example, N, 41st wirings arranged in a direction intersecting with the 44th wirings are connected to the 41st electrode 41 described above provided in each island-shaped semiconductor layer 1110. Note that the 41st wiring is formed in each of the island-shaped semiconductor layers 111.
All of the above-mentioned forty-first electrodes 41 provided in 0 may be commonly connected. The above-mentioned forty-second electrode 42 of each high-resistance element may be connected to one by the 42nd wiring. The transistors forming the memory cell are PMO.
It may be configured by only S, or may be replaced with a transistor of the opposite type to the transistor having the 43rd or 45th electrode as a gate electrode, instead of the high resistance element described above.

Below, the select gate transistor, the memory cell adjacent to the select gate transistor, and the adjacent memory cells are not connected via the impurity diffusion layer. Instead, the distance between the select transistor and the memory cells and the memory cells is not. The operation principle of the semiconductor memory device having a structure of about 30 nm or less, which is very close to the structure in which the select transistor and the memory cell and the memory cells are connected to each other through the impurity diffusion layer, will be described. When adjacent elements are close enough, the channel formed by the potential above the threshold applied to the gate of the select gate transistor or the control gate of the memory cell is connected to the channel of the adjacent element and the gates of all elements are connected. When a potential higher than the threshold value is applied, the channels of all the elements are connected. This state is almost equivalent to the case where the select transistor is connected to the memory cell or the memory cell via the impurity diffusion layer. Therefore, the operating principle is that the select transistor is connected to the memory cell or the memory cell via the impurity diffusion layer. It is the same as when Further, the semiconductor memory device having a structure in which the select gate transistor and the memory cell are not connected via the impurity diffusion layer, and instead the third conductive film is arranged between the select transistor and the memory cell or the gate electrode of the memory cell. The operating principle of is described. The third conductive film is located between the respective elements and is connected to the island-shaped semiconductor layer via an insulating film, for example, a silicon oxide film. That is, the third conductive film, this insulating film and the island-shaped semiconductor layer form a MIS capacitor. A channel is formed when the third conductive film is applied with a potential such that an inversion layer is formed at the interface between the island-shaped semiconductor layer and this insulating film. The formed channel has the same function as that of the impurity diffusion layer that connects the adjacent elements to the adjacent elements.
Therefore, when a potential capable of forming a channel is applied to the third conductive film, the same operation as in the case where the select gate transistor or the memory cell is connected through the impurity diffusion layer is performed. Further, even if the potential for forming a channel is not applied to the third conductive film, when the island-shaped semiconductor layer is a P-type semiconductor, it is necessary to extract electrons from the charge storage layer by selecting the gate transistor or the memory cell. Operates in the same way as when they are connected via an impurity diffusion layer.

Implementation in a method of manufacturing a memory cell array
In the semiconductor memory device formed in this production example, the semiconductor substrate is processed into, for example, a columnar shape to form an island-shaped semiconductor layer, and the side surface of the island-shaped semiconductor layer serves as an active region surface. Multiple floating gates are formed as tunnel oxide films and charge storage layers on the region surface, and each island-shaped semiconductor layer is electrically floated to the semiconductor substrate, and the active region of each memory cell is electrically flowed. In a semiconductor memory device in a towing state, select gate transistors are arranged above and below an island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors. The structure is such that the gate insulating film of the select gate transistor is connected in series along the island-shaped semiconductor layer, and the gate insulating film of the select gate transistor is the gate insulating film of the memory transistor. Larger, it is processed and formed each transistor from bottom to top.

Such a semiconductor memory device can be formed by the following manufacturing method. 82 to 91.
92 to 101 are sectional views taken along the lines AA 'and BB' of FIG. 1 showing the memory cell array of the EEPROM, respectively. First, a p-type silicon substrate 10 which is a semiconductor substrate
As a first insulating film to be a mask layer, for example, a silicon nitride film 310 is deposited to a thickness of 200 to 2000 nm on the surface of 0,
Using the resist R11 patterned by a known photolithography technique as a mask (FIGS. 82 and 92), the silicon nitride film 310 which is the first insulating film is etched by reactive ion etching. Then, using the silicon nitride film 310, which is the first insulating film, as a mask, the p-type silicon substrate 100, which is a semiconductor substrate, is 2,000 to 20 by reactive ion etching.
Etching is performed for about 000 nm to form the first groove portion 210 having a lattice stripe shape. As a result, the p-type silicon substrate 100, which is a semiconductor substrate, has a columnar shape and is separated into a plurality of island-shaped semiconductor layers 110. Then, the island-shaped semiconductor layer 1
The surface of 10 is oxidized to form a second insulating film, for example, a thermal oxide film 410 having a thickness of 10 to 100 nm (FIG. 83).
And FIG. 93). When the island-shaped semiconductor layer 110 is formed with the minimum processing size, the size of the island-shaped semiconductor layer 110 is reduced due to the formation of the thermal oxide film 410. In other words, it is formed with the minimum processing dimension or less. Next, after the thermal oxide film 410 that is the second insulating film around each island-shaped semiconductor layer 110 is removed by etching, for example, by isotropic etching (FIGS. 84 and 94), oblique ion implantation is used as necessary. Then, channel ion implantation is performed on the sidewall of each island-shaped semiconductor layer 110. For example, 5 to 100 ke from a direction inclined by about 5 to 45 °
V implantation energy, boron 1 × 10 ¹¹ to 1 × 10 ¹³ / c
The dose is about m ² . During the channel ion implantation, it is preferable to implant the island-shaped semiconductor layer 110 from multiple directions because the surface impurity concentration can be made uniform. Alternatively, instead of the channel ion implantation, an oxide film containing boron may be deposited by the CVD method and boron diffusion from the oxide film may be used. Note that the impurity introduction from the surface of the island-shaped semiconductor layer 110 may be performed before the surface of the island-shaped semiconductor layer 110 is covered with the thermal oxide film 410 that is the second insulating film, or may be performed. The introduction may be completed before forming 110, and the means is not limited as long as the island-shaped semiconductor layer 110 has the same impurity concentration distribution.

Then, as the fifth insulating film, for example, a silicon oxide film 431 is formed into a lattice-shaped first groove portion 210.
Is deposited by CVD to a thickness of 50 to 500 nm, the lattice-shaped first trenches 210 are etched back to a desired depth, and the silicon oxide film 431, which is a fifth insulating film, is buried to a desired depth. At this time, the silicon oxide film 431, which is the fifth insulating film, is the thermal oxide film 410, which is the second insulating film.
May be deposited without being removed by etching and etched back to a desired depth. Then, for example, a silicon oxide film 481 is formed around each of the island-shaped semiconductor layers 110 by using, for example, a CVD method as a thirteenth insulating film to be a tunnel oxide film having a thickness of, for example, about 10 nm. At this time, the tunnel oxide film is not limited to the CVD oxide film and may be a thermal oxide film or a nitrogen oxide film. Next, after depositing, for example, a polycrystalline silicon film 511 of about 50 to 200 nm as the first conductive film, the polycrystalline silicon film 511 that is the first conductive film is formed into a sidewall shape by, for example, reactive ion etching. The height is left (FIGS. 85 and 95). Next, for example, a silicon oxide film 432 is formed as a fifth insulating film.
Of 50 to 500 nm by the CVD method, the silicon oxide film 432 which is the fifth insulating film is etched back by, for example, isotropic etching, and the polycrystalline film which is the first conductive film is left in the shape of the side wall. The silicon film 511 is buried so as to be completely buried.

Then, for example, by thermal oxidation, 10 nm
A silicon oxide film 422 is formed as a third insulating film serving as a tunnel oxide film. The silicon oxide film 422 which is the third insulating film is not limited to the thermal oxide film like the silicon oxide film 481 which is the thirteenth insulating film, and may be a CVD oxide film or a nitrogen oxide film. It does not have to be the same material as the silicon oxide film 481. The thickness of the silicon oxide film 422 which is the third insulating film and the film thickness of the thirteenth insulating film 481 can be set arbitrarily, and the silicon oxide film 422 which is the third insulating film is the thirteenth insulating film. The thickness may be thinner, thicker, or equivalent to that of the silicon oxide film 481. Next, after depositing, for example, a polycrystalline silicon film 512 of about 50 to 200 nm as the first conductive film, the polycrystalline silicon film 512 that is the first conductive film is formed into a sidewall shape by, for example, reactive ion etching. The height is left (FIGS. 86 and 96). By repeating this in the same manner, a silicon oxide film 433, for example, is embedded as the fifth insulating film so that the polycrystalline silicon film 512, which is the first conductive film, is embedded, and then 10 nm is formed around each island-shaped semiconductor layer 110. For example, a silicon oxide film 423 is formed as a third insulating film to be a tunnel oxide film, and a polycrystalline silicon film 513 is arranged as a first conductive film on the side surface thereof. Similarly, as a fifth insulating film, for example, a silicon oxide film 434 is buried so that the polycrystalline silicon film 513 which is the first conductive film is buried, and then a tunnel oxide film of about 10 nm is formed around each island-shaped semiconductor layer 110. For example, a silicon oxide film 484 is formed as a thirteenth insulating film, and a polycrystalline silicon film 514 is arranged as a first conductive film on the side surface thereof (FIG. 8).
7 and FIG. 97).

Then, a fifth isolation is performed by isotropic etching.
Silicon oxide films 434, 433, 432, 4 which are edge films
31 is removed and the divided first conductive film is polycrystalline silicon.
Con films 511 to 514 and the first insulating film silicon
Self-aligned with the nitride film 310, the island-shaped semiconductor layer 110, the semiconductor
Impurities are introduced into the body substrate 100. For example, solid phase vapor diffusion
Arsenic as an N-type impurity diffusion layer of 710 to 724
1 x 10¹⁸~ 1 x 10 ^{twenty one}/ Cm³Form with a dose of about
It At this time, the impurity diffusion layer 710 to be the first wiring layer is
The impurity concentration may be adjusted by the ion implantation method.
(FIGS. 88 and 98). For example, incline about 0 to 7 degrees
5 to 100 keV implantation energy from the direction of
× 10¹³~ 1 x 10¹⁵/ Cm²The dose is about
It Then, heat treatment is applied to the impurity diffusion layer 71.
0 to 724 are diffused to form the p-type region of the island-shaped semiconductor layer 110.
It is electrically floating (FIGS. 89 and 9).
9). For the concentration of the impurity diffusion layer 710 to be the first wiring layer
The cloth serves as a semiconductor substrate, for example, a p-type silicon substrate 100
It is preferable to maintain a gradual slope toward. Also,
Of the polycrystalline silicon films 511 to 514 which are the first conductive film.
Impurities are introduced by using the polycrystalline silicon film that is the first conductive film.
It may be performed at the time of forming 510, or the island-shaped semiconductor layer 110.
It may be performed when introducing impurities into the
If so, there is no restriction on the time of introduction.

Thereafter, as the eleventh insulating film, for example, a silicon oxide film 471 is deposited by the CVD method to a thickness of 50 to 500 nm.
The silicon oxide film 4 serving as an eleventh insulating film is deposited and is embedded by anisotropic etching and isotropic etching so as to bury the side portion of the polycrystalline silicon film 511 serving as the first conductive film.
Embed 71. Next, as a twelfth insulating film, for example, a silicon nitride film 340 is deposited in a thickness of 5 to 50 nm to form sidewalls (FIGS. 90 and 100). Subsequently, the silicon oxide film 471, which is the eleventh insulating film, is etched back to the extent that the side portions of the polycrystalline silicon film 511, which is the first conductive film, are exposed, and the second conductive film is formed, for example, as a second conductive film. A crystalline silicon film 521 is deposited with a thickness of 15 to 150 nm. After that, the polycrystalline silicon film 52 which is the second conductive film is formed.
1 is etched back and self-aligned with the polycrystalline silicon film 521 which is the second conductive film, and the silicon oxide film 471 which is the eleventh insulating film and the p-type silicon substrate 1 which is the semiconductor substrate.
00 to the second groove 22 by, for example, anisotropic etching.
0 is formed, and the impurity diffusion layer 710 is separated. That is,
The isolation portion of the first wiring layer is formed in self-alignment with the isolation portion of the second conductive film. Subsequently, the polycrystal silicon film 521 which is the second conductive film is etched back to the extent that it can contact the polycrystal silicon film 511 which is the first conductive film to form a select gate. At that time, the distance between the island-shaped semiconductor layers 110 is set to a predetermined value or less in the AA ′ direction of FIG. 1 in advance, so that the selection gate lines continuous in the direction can be formed without using a mask process. Is formed as the second wiring layer.

After that, as the eighth insulating film, for example, a silicon oxide film 462 is deposited to a thickness of 50 to 500 nm by the CVD method, and the polycrystalline silicon film 521 which is at least the second conductive film is formed by anisotropic etching and isotropic etching.
Silicon oxide film 4 which is an eighth insulating film so that
62 is buried and the sidewall of the silicon nitride film 340 which is the twelfth insulating film is removed by isotropic etching to remove the exposed polycrystalline silicon film 51 which is the first conductive film.
An interlayer insulating film 612 is formed on the surfaces of 2 to 514. The interlayer insulating film 612 is, eg, an ONO film. Specifically, the surface of the polycrystalline silicon film is 5 to 10 nm thick by the thermal oxidation method.
Of silicon oxide film, a silicon nitride film of 5 to 10 nm, and a silicon oxide film of 5 to 10 nm are sequentially deposited by the CVD method. Then, similarly, as the second conductive film, for example, a polycrystalline silicon film 522 is deposited to a thickness of 15 to 150 nm,
By etching back, the polycrystalline silicon film 522 which is the second conductive film is arranged on the side portion of the polycrystalline silicon film 512 which is the first conductive film with the interlayer insulating film 612 interposed therebetween.
At this time, by setting a value equal to or less than a predetermined value in the direction AA ′ in FIG. 1, a third wiring layer which becomes a control gate line continuous in the direction is formed without using a mask process. It After that, as the eighth insulating film, for example, a silicon oxide film 463 is formed by CVD to 50
˜500 nm is deposited, a silicon oxide film 463 which is an eighth insulating film is buried by anisotropic etching and isotropic etching so that at least the polycrystalline silicon film 522 which is the second conductive film is buried, and the same process is repeated. Thus, the polycrystalline silicon film 523 which is the second conductive film is arranged on the side portion of the polycrystalline silicon film 513 which is the first conductive film with the interlayer insulating film 613 interposed therebetween. The polycrystalline silicon film 514, which is the uppermost first conductive film, can contact the polycrystalline silicon film 514, which is the first conductive film, like the polycrystalline silicon film 511, which is the lowermost first conductive film. Then, the polycrystalline silicon film 524 which is the second conductive film is etched back. For example, a silicon oxide film 465 which becomes a tenth insulating film is formed on the polycrystalline silicon film 524 which is the second conductive film.
Is deposited to 100-500 nm and then etched back or C
The upper part of the island-shaped semiconductor layer 110 provided with the impurity diffusion layer 724 is exposed by the MP method or the like, and the island-shaped semiconductor layer 1 is formed so that the fourth wiring layer intersects the direction of the second or third wiring layer.
Connect with the top of 10. Next, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed (FIGS. 91 and 101).

As a result, a semiconductor memory device having a memory function is realized by the charge state accumulated in the charge accumulation layer having the polycrystalline silicon film serving as the first conductive film as the floating gate. In addition, by setting the active region of each memory cell to the floating state with respect to the semiconductor substrate, the back bias effect from the substrate is eliminated, and the threshold value of the memory cells located at both ends connected in series during the read operation. Fluctuations disappear. Further, the side surface of the island-shaped semiconductor layer 110, which is the active region surface, is oxidized to remove the oxide film 410,
By forming the pillar-shaped island-shaped semiconductor layer 110 with a size equal to or smaller than the minimum processing dimension, the capacitance between the floating gate and the control gate relative to the capacitance between the floating gate and the island-shaped semiconductor layer can be increased without increasing the occupied area of the memory cell. The ratio can be increased, and writing and erasing of memory cells are facilitated. Further, by disposing the select gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is in a negative state. However, the phenomenon that the cell current flows can be prevented. In this manufacturing example, a film formed on the surface of the semiconductor substrate or the polycrystalline silicon film, such as the silicon nitride film 310 which is the first insulating film and the silicon nitride film 340 which is the twelfth insulating film, is formed from the silicon surface side. A multi-layer film of silicon oxide film / silicon nitride film may be used.

The insulating film used in the present invention is not limited to the oxide film and the nitride film, and the oxide film and the nitride film may be exchanged like the insulating film buried in the second groove 220. You can replace places that do not exist. In this manufacturing example, the control gate of each memory cell was formed so as to be continuous in one direction without using a mask. This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, separation is made in the fourth wiring layer direction. A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography.

Manufacturing Example 2 In the semiconductor memory device formed in this Manufacturing Example, a semiconductor substrate is processed into, for example, a columnar shape to form an island-shaped semiconductor layer, and the side surface of the island-shaped semiconductor layer serves as an active region surface. A plurality of floating gates are formed as tunnel oxide films and charge storage layers on the active region surface, and each island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically connected. In a common semiconductor memory device, select gate transistors are arranged above and below an island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors, and each transistor is It has a structure in which it is connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is larger than that of the memory transistor. First, each transistor is processed from the bottom to the top.

Such a semiconductor memory device can be formed by the following manufacturing method. 102 to 1
15 and FIGS. 116 to 129 are EEPROMs, respectively.
1 of FIG. 1 showing the memory cell array of FIG.
FIG. First, a silicon nitride film 310, for example, 200 to 200 is formed on the surface of a p-type silicon substrate 100, which is a semiconductor substrate, as a first insulating film that is a mask layer.
Using the resist R11 which is deposited to a thickness of 0 nm and patterned by a known photolithography technique as a mask, the silicon nitride film 310 which is the first insulating film is etched by reactive ion etching, and then by reactive ion etching, For example, p-type silicon substrate 10
0 is etched to about 100 to 5000 nm, and B-
Lattice-striped first grooves 210 are formed along the B ′ direction (FIGS. 102 and 116). p-type silicon substrate 100
When etching is performed, the resist R11 may be removed and the silicon nitride film 310 that is the first insulating film may be used as a mask for etching. Subsequently, a resist R12 patterned by a known photolithography technique
Using as a mask, the silicon nitride film 310, which is the first insulating film, is etched by reactive ion etching to form the grid-like grooves 211 along the AA 'direction (FIGS. 103 and 117). Then, the p-type silicon substrate 100 is 2,000 to 2 by reactive ion etching.
Etching about 0000 nm to form a grid-like groove 212
Are formed (FIGS. 104 and 118). As a result, the p-type silicon substrate 100, which is a semiconductor substrate, has a columnar shape and is separated into a plurality of island-shaped semiconductor layers 110. At this time B
The grid-striped grooves 212 along the −B ′ direction are formed to be deeper than the grid-striped grooves 212 along the AA ′ direction.

Next, as in the case of Manufacturing Example 1, channel ion implantation is performed on the sidewalls of each island-shaped semiconductor layer 110. The method and time of introducing the impurities are not limited as in Production Example 1. Next, the surface of the island-shaped semiconductor layer 110 is oxidized, for example, to form the thermal oxide film 410 as a second insulating film.
~ 100 nm is formed. When the island-shaped semiconductor layer 110 is formed with the minimum processing size, the size of the island-shaped semiconductor layer 110 is reduced due to the formation of the thermal oxide film 410. That is,
It is formed below the minimum processing size. After that, as the fifth insulating film, for example, a silicon oxide film 431 is formed in the grid-shaped grooves 2
12 to 50 nm to 500 nm is deposited by the CVD method. A-
After the silicon oxide film 431, which is the fifth insulating film, is buried in the same or deeper than the lattice-stripe-shaped groove 212 in the direction along A ′, impurities are introduced into the bottom of the isolation portion of the island-shaped semiconductor layer 110. (FIGS. 105 and 119). For example, by ion implantation, 5 to 10 from a direction inclined by 0 to 7 °
Arsenic 1 × 10 ¹³ to 1 × 1 with implantation energy of 0 keV
A dose of about 0 ¹⁶ / cm ² is performed. Then, heat treatment is performed to diffuse the impurities introduced earlier to form the impurity diffusion layer 710. This impurity diffusion layer 710 is directly formed as the first wiring layer without requiring a special separation step thereafter. After that, a silicon oxide film 481 is formed as a thirteenth insulating film to be a tunnel oxide film having a thickness of, for example, about 10 nm around each of the island-shaped semiconductor layers 110 by using, for example, a thermal oxidation method (FIGS. 106 and 120). At this time, the tunnel oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film. Subsequently, for example, a polycrystalline silicon film 511 having a thickness of 50 to 200 nm is used as the first conductive film.
After being deposited to a degree, the polycrystalline silicon film 511, which is the first conductive film, is made to remain in a sidewall shape at a desired height by, for example, reactive ion etching (FIGS. 107 and 121). At that time, the distance between the island-shaped semiconductor layers 110 is set to a predetermined value or less in the AA ′ direction of FIG. 1 in advance, so that the selection gate lines continuous in the direction can be formed without using a mask process. Is formed as the second wiring layer.

Then, for example, a silicon oxide film 451 is formed as a seventh insulating film around each of the island-shaped semiconductor layers 110 and around the polycrystalline silicon film 511 which is the first conductive film by using, for example, a thermal oxidation method. It is formed to have a thickness of about 10 to 30 nm, and then, for example, a silicon oxide film 432 is formed as a fifth insulating film.
Is deposited to a thickness of 50 to 500 nm by the CVD method (FIGS. 108 and 122), and the polycrystalline silicon film 511, which is the first conductive film left in the sidewall shape, is completely buried (FIGS. 109 and 122). 123). At this time, the film thickness of the silicon oxide film 432 which is the fifth insulating film at the upper end portion of the polycrystalline silicon film 511 which is the first conductive film is set to be 20 to 30 nm or less. After that, a silicon oxide film 422 is formed as a third insulating film to be a tunnel oxide film of about 10 nm by using, for example, a thermal oxidation method. At this time, the silicon oxide film 4 which is the 13th insulating film
Similar to 81, it is not limited to the thermal oxide film, but may be a CVD oxide film or a nitrogen oxide film, and need not be the same material as the silicon oxide film 481 which is the thirteenth insulating film. The thickness of the silicon oxide film 422 which is the third insulating film and the silicon oxide film 481 which is the thirteenth insulating film can be set arbitrarily, and the silicon oxide film 422 which is the third insulating film is It may be thinner than the silicon oxide film 481 which is an insulating film,
It may be thick or equivalent. The silicon oxide film 451 which is the seventh insulating film may not be formed, but in this case, the silicon oxide film 42 which is the third insulating film is formed.
2 is a silicon oxide film 432 which is a fourth insulating film.
Since there is a risk of non-uniformity of the film thickness in the vicinity of contact with, it is desirable to previously form the silicon oxide film 451 which is the seventh insulating film.

Then, after depositing, for example, a polycrystalline silicon film 512 of about 50 to 200 nm as a first conductive film, the polycrystalline silicon film 512 that is the first conductive film is deposited on the sidewall by, for example, reactive ion etching. To a desired height. After that, the interlayer insulating film 612
Are formed (FIGS. 110 and 124). The interlayer insulating film 612 is, eg, an ONO film. The ONO film can be formed in the same manner as in Manufacturing Example 1. Subsequently, as the second conductive film, for example, a polycrystalline silicon film 522 having a thickness of 15 to 1 is formed.
By depositing 50 nm and etching back, the interlayer insulating film 6 is formed on the side of the polycrystalline silicon film 512 which is the first conductive film.
And a polycrystalline silicon film 52 which is a second conductive film
2 are arranged (FIGS. 111 and 125). At this time,
By setting the value to a predetermined value or less in the AA ′ direction in FIG. 1 in advance, it is formed as a third wiring layer which becomes a control gate line continuous in that direction without using a mask process. Then, for example, a silicon oxide film 452 is formed as a seventh insulating film around each island-shaped semiconductor layer 110 and around the polycrystalline silicon film 522 that is the second conductive film by using, for example, a thermal oxidation method to a thickness of 10 to 30 nm. Formed as a fifth insulating film, and then, for example, a silicon oxide film 43 is formed as a fifth insulating film.
No. 3 is deposited to a thickness of 50 to 500 nm by the CVD method (FIG. 11).
2 and FIG. 126). By repeating the same process, a silicon oxide film 423, for example, is formed on the third wiring layer at a position of 20 to 30 nm or less as a third insulating film to be a tunnel oxide film.
Is formed on the surface of each island-shaped semiconductor layer 110, and a polycrystalline silicon film 513 serving as a first conductive film is arranged on the side of the island-shaped semiconductor layer 110.
In addition, the polycrystalline silicon film 523 to be the second conductive film is arranged on the side of the polycrystalline silicon film 513 to be the first conductive film via the interlayer insulating film 613.

Then, a silicon oxide film 453 is formed as a seventh insulating film around each of the island-shaped semiconductor layers 110 and around the polycrystalline silicon film 523 which is the second conductive film by using, for example, a thermal oxidation method. ˜30 nm, and then, as a fifth insulating film, for example, a silicon oxide film 434 is CV
50 to 500 nm is deposited by the D method (see FIGS. 113 and 1).
27), etch back. At this time, the film thickness of the silicon oxide film 434 which is the fifth insulating film at the upper end of the polycrystalline silicon film 523 which is the second conductive film is 20 to 30 nm.
Below. After that, a silicon oxide film 484 is formed on each island-shaped semiconductor layer 11 as a thirteenth insulating film to be a tunnel oxide film.
It is formed on the surface of 0, and the polycrystalline silicon film 514 to be the first conductive film is arranged on the side thereof. As a fifth insulating film on the upper layer of the polycrystalline silicon film 514 to be the first conductive film,
For example, the silicon oxide film 435 may be formed in a thickness of 50 to 5 by a CVD method.
00 nm is deposited (FIGS. 114 and 128), the upper portion of the island-shaped semiconductor layer 110 is exposed by etch back or CMP method, impurities are introduced therein, and an impurity diffusion layer 724 is formed by heat treatment. Regarding the introduction of impurities, for example, arsenic doping by an ion implantation method or an oxide film containing arsenic may be deposited by a CVD method and arsenic diffusion from the oxide film may be used. Subsequently, the fourth wiring layer is connected to the upper portion of the island-shaped semiconductor layer 110 so that the direction intersects with the second or third wiring layer (FIGS. 115 and 129). After that, an interlayer insulating film is formed by a known technique, and a contact hole and a metal wiring are formed.

Also in this manufacturing example, the same effect as in manufacturing example 1 can be obtained. Furthermore, the number of manufacturing steps is reduced, the required height of the island-shaped semiconductor layer can be reduced, and process variations can be suppressed. As a result, a semiconductor memory device having a memory function is realized by the charge state accumulated in the charge accumulation layer having the polycrystalline silicon film serving as the first conductive film as the floating gate. In addition, by setting the active region of each memory cell to the floating state with respect to the semiconductor substrate, the back bias effect from the substrate is eliminated, and the threshold value of the memory cells located at both ends connected in series during the read operation. Fluctuations disappear. Further, the side surface of the island-shaped semiconductor layer 110, which is the active region surface, is oxidized, the oxide film 410 is removed, and the island-shaped semiconductor layer 110 processed into a columnar shape is formed with a minimum processing dimension or less. It is possible to increase the ratio of the capacitance of the floating gate and the control gate to the capacitance of the floating gate and the island-shaped semiconductor layer without increasing the occupied area, which facilitates writing and erasing of the memory cell. Further, by disposing the select gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0 V and the threshold value is in a negative state, and the non-selected memory cells are not selected. It is possible to prevent a cell current from flowing even in a cell.

In this manufacturing example, films such as the silicon nitride film 310 which is the first insulating film and the silicon nitride film 340 which is the twelfth insulating film are formed on the surface of the semiconductor substrate or the polycrystalline silicon film. A multi-layer film of silicon oxide film / silicon nitride film may be formed from the silicon surface side. Further, the insulating film used in the present invention does not have to be an oxide film and a nitride film, and an oxide film and a nitride film, such as an insulating film to be buried in the second groove portion 220, may be replaced with each other. Good. In this manufacturing example, the control gate of each memory cell was formed continuously in one direction without using a mask. This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, separation is made in the fourth wiring layer direction. A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography. In addition, a silicon oxide film 452 which is a seventh insulating film
˜453 do not have to be formed for the same reason as the silicon oxide film 451 which is the seventh insulating film described above, but the silicon oxide film 423 which is the third insulating film and the thirteenth insulating film are the same. It is desirable to form the silicon oxide film 484 in order to improve the film thickness uniformity.

Further, in this manufacturing example, the formation of the memory cell or control gate in the upper stage is started after the memory cell or control gate in a certain stage is completely completed.
Similar to the manufacturing example 1, the tunnel oxide film and the floating gate may be formed in advance for all stages, and then the second wiring layer or the interlayer insulating film and the third wiring layer may be formed in each stage. More specifically, the polycrystalline silicon films 511 to 5 which are the first conductive films.
14 (FIGS. 85 to 87 and 95 to 9)
7), polycrystalline silicon films 511 to 11 which are first conductive films
The spacing between the spaces of 514 is set to 20 to 30 nm or less, and the impurity diffusion layers 721, 722, 723, 7 are set.
The same procedure as in Production Example 1 can be performed except that 24 is not introduced (FIGS. 88 and 98). Also in the method of forming the first wiring layer, the second groove portion 220 is formed in the p-type silicon substrate 100 which is the semiconductor substrate in a self-alignment manner with the polycrystalline silicon film 521 which is the second conductive film, as in Manufacturing Example 1. (Fig. 10
1), the separation portion of the first wiring layer may be formed.

Manufacturing Example 3 In the semiconductor memory device formed in this Manufacturing Example, an island-shaped semiconductor layer is formed by processing a semiconductor substrate on which an oxide film is inserted, for example, a semiconductor portion on the oxide film of an SOI substrate into a columnar shape. Then
A side surface of the island-shaped semiconductor layer is used as an active region surface, a plurality of floating gates are formed as tunnel oxide films and charge storage layers on the active region surface, and each island-shaped semiconductor layer is electrically common to a semiconductor substrate. In a semiconductor memory device in which the active region of each memory cell is electrically floated, select gate transistors are arranged above and below the island-shaped semiconductor layer, and the memory transistor is sandwiched between the select gate transistors. A plurality of, for example two, transistors are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor, Each transistor is machined from bottom to top.

Such a semiconductor memory device can be formed by the following manufacturing method. Note that FIGS.
36 and FIGS. 137 to 143 are cross-sectional views taken along the line AA ′ and the line BB ′ of FIG. 1 showing the memory cell array of the EEPROM. An SOI substrate 101 is used as a substrate, and a silicon nitride film 310, for example, having a thickness of 200 to 2000 nm is deposited on the surface of the SOI substrate 101 as a mask layer, and a resist R11 patterned by a known photolithography technique is used as a mask. Then, the silicon nitride film 31 which is the first insulating film is formed by reactive ion etching.
0, and then the reactive ion etching is performed to etch the surface of the SOI substrate 101 by 10 to 5000 nm to form the first groove portions 210 having a lattice stripe shape along the BB 'direction (FIGS. 130 and 137). . When the SOI substrate 101 is etched, the resist R11 may be removed and the silicon nitride film 310 that is the first insulating film may be used as a mask for etching.

Then, using the resist R12 patterned by a known photolithography technique as a mask, the silicon nitride film 310 which is the first insulating film is etched by reactive ion etching, and A-
Grooves 211 having a checkered pattern are formed along the A ′ direction (see FIG. 1).
31 and FIG. 138). Then, the SOI substrate 101 is etched to about 2000 to 20000 nm by reactive ion etching to form grooves 212 having a lattice stripe shape (FIGS. 132 and 139). As a result, the p-type silicon portion on the surface of the SOI substrate 101 has a columnar shape and is separated into a plurality of island-shaped semiconductor layers 110. At this time, the insulating layer portion of the SOI substrate 101 is exposed at the separation portion of the island-shaped semiconductor layer 110 in the direction along BB ′, and the SOI substrate 1 is formed in the direction along AA ′.
01 so that the p-type silicon portion on the surface remains. Next, as in Manufacturing Example 1, channel ion implantation is performed on the sidewall of each island-shaped semiconductor layer 110. The method and timing of introducing the impurities are not limited as in Production Example 1. Next, the surface of the island-shaped semiconductor layer 110 is oxidized, for example, to form a second insulating film, for example, a thermal oxide film 410 in a thickness of 10 to 10.
100 nm is formed. At this time, if the island-shaped semiconductor layer 110 is formed with the minimum processing size, the size of the island-shaped semiconductor layer 110 is reduced due to the formation of the thermal oxide film 410. In other words, it is formed with the minimum processing dimension or less. After the thermal oxide film 410, which is the second insulating film, is formed in this way, S remaining in the direction along the line AA ′ of the isolation portion of the island-shaped semiconductor layer 110 is left.
Impurities are introduced into the p-type silicon portion on the surface of the OI substrate 101 through the thermal oxide film 410 which is the second insulating film (FIGS. 133 and 140). For example, by the ion implantation method, 0
A dose of about 1 × 10 ¹³ to 1 × 10 ¹⁶ / cm ^{2 of} arsenic is performed with an implantation energy of 5 to 100 keV from a direction inclined by about 7 °. Then, heat treatment is performed to diffuse the impurities introduced earlier to form the impurity diffusion layer 710 (FIGS. 134 and 141). This impurity diffusion layer 71
0 does not require a special separation step thereafter, and is directly formed as the first wiring layer.

Next, as a fifth insulating film, for example, a silicon oxide film 431 is deposited in the lattice-striped grooves 212 by the CVD method to a thickness of 50 to 500 nm. The silicon oxide film 431 which is the fifth insulating film is formed to the desired depth of the grid-like grooves 212.
Then, a silicon oxide film 481 is formed as a thirteenth insulating film to be a tunnel oxide film having a thickness of, for example, about 10 nm around each island-shaped semiconductor layer 110 by using, for example, the CVD method (FIGS. 135 and 135). 142). At this time, the tunnel oxide film is not limited to the CVD oxide film, but may be a thermal oxide film or a nitrogen oxide film. The subsequent steps are the same as those in Production Example 2 (see FIGS.
115 and FIGS. 121 to 129).

According to this manufacturing example as well, the same effect as in Manufacturing Example 2 can be obtained, and further, the junction capacitance of the impurity diffusion layer 710 serving as the first wiring layer is suppressed. As a result, a semiconductor memory device having a memory function is realized by the charge state accumulated in the charge accumulation layer having the polycrystalline silicon film serving as the first conductive film as the floating gate. In addition, by setting the active region of each memory cell to the floating state with respect to the semiconductor substrate, the back bias effect from the substrate is eliminated, and the threshold value of the memory cells located at both ends connected in series during the read operation. Fluctuations disappear. Further, the side surface of the island-shaped semiconductor layer 110, which is the active region surface, is oxidized, the oxide film 410 is removed, and the island-shaped semiconductor layer 1 processed into a pillar shape.
By forming 10 with the minimum processing dimension or less, it becomes possible to increase the ratio of the capacitance of the floating gate and the control gate to the capacitance of the floating gate and the island-shaped semiconductor layer without increasing the occupied area of the memory cell. , Writing and erasing of memory cells becomes easy.

Further, by disposing the select gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0 V and the threshold value is negative. It is possible to prevent the cell current from flowing even in a non-selected cell. In this manufacturing example, a film formed on the surface of the semiconductor substrate or the polycrystalline silicon film, such as the silicon nitride film 310 which is the first insulating film and the silicon nitride film 340 which is the twelfth insulating film, is the silicon surface side. To a silicon oxide film / silicon nitride film multilayer film. The insulating film used in the present invention is not limited to the oxide film and the nitride film, and the second groove portion 220 may be used.
Where an oxide film and a nitride film may be replaced, such as an insulating film to be buried in, may be replaced. In this manufacturing example, the control gate of each memory cell was formed continuously in one direction without using a mask.
This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, separation is made in the fourth wiring layer direction. A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography.

Manufacture Example 4 The semiconductor memory device formed in this Manufacture Example is the same as that in Manufacture Example 1 except that the gate oxide films 481 and 48 which are the thirteenth insulating films.
4 and tunnel oxide films 422 and 42 which are third insulating films
3 is formed by thermal oxidation of the island-shaped semiconductor layer 110.
As shown in FIG. 5 and FIG. 147, the diameter of the island-shaped semiconductor layer 110 decreases toward the upper memory cell and the select gate.
For example, when the gate oxide film 481 which is the thirteenth insulating film is formed by thermal oxidation of the island-shaped semiconductor layer 110, the side surface of the island-shaped semiconductor layer 110 becomes the silicon oxide film 481 which is the thirteenth insulating film. The silicon oxide film 481 which is the 13th insulating film in the region which is not covered with the polycrystalline silicon film 511 which is the first conductive film is removed when the silicon oxide film which is the fifth insulating film is removed. To be done. Therefore, as shown in FIGS. 144 and 146, the diameter of the upper portion of the island-shaped semiconductor layer 110 is reduced. Since the memory cells and select gates in the upper stage are formed in the island-shaped semiconductor layer 110 having the reduced diameter, the memory cells and select gates have a shape in which the diameter of the island-shaped semiconductor layer 110 is reduced toward the top. . Also, FIG.
As shown in FIG. 45 and FIG. 147, the shape of the island 110 is not particularly limited as long as it has a structure in which memory cells can be arranged in series in a direction perpendicular to the semiconductor substrate 100.

Manufacture Example 5 In the semiconductor memory device formed in this Manufacture Example, an island-shaped semiconductor layer is formed by processing a semiconductor substrate into, for example, a columnar shape, and the side surface of the island-shaped semiconductor layer serves as an active region surface. A plurality of laminated insulating films are formed as a tunnel oxide film and a charge storage layer on the region surface, and each island-shaped semiconductor layer is electrically floated to the semiconductor substrate, and the active region of each memory cell is electrically In a floating semiconductor memory device, select gate transistors are arranged above and below an island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors. Are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is equal to the gate insulating film of the memory transistor. Each transistor is processed and formed from the bottom to the top, which is larger than the film thickness.

Such a semiconductor memory device can be formed by the following manufacturing method. 148 and 149 are cross-sectional views taken along the lines AA ′ and BB ′ of FIG. 9 showing the memory cell array of the EEPROM, respectively. In this manufacturing example, unlike the manufacturing example 1, the silicon oxide films 422 and 423 which are the third insulating films are not formed, but instead the laminated insulating films 622 and 623 are respectively formed, and the second conductive film is used. Without forming any polycrystalline silicon 521 to 524, the deposited film thickness and the etching amount are set so that the polycrystalline silicon 511 to 514 which are the first conductive film are continuous in the AA ′ line direction of FIG. The second groove 220 for adjusting and separating the first wiring layer is anisotropically etched by self-alignment with respect to the polycrystalline silicon 511 which is the first conductive film (FIGS. 148 and 149). Further, the introduction of the impurities into the polycrystalline silicon films 511 to 514 which are the first conductive films may be performed at the time of forming the polycrystalline silicon film, or after the film formation or the sidewall formation, The introduction time is not limited as long as it is a conductive film.

In this manufacturing example, the control gate of each memory cell is formed so as to be continuous in one direction without using a mask. This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent distance to the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, the second wiring layer is separated in the fourth wiring layer direction, A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography. Further, by disposing the select gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0 V and the threshold value is in a negative state, so that the non-selection is performed. It is possible to prevent a cell current from flowing even in a cell.

Manufacture Example 6 In the semiconductor memory device formed in this Manufacture Example, an island-shaped semiconductor layer is formed by processing a semiconductor substrate into, for example, a columnar shape, and the side surface of the island-shaped semiconductor layer serves as an active region surface. A plurality of gate oxide films are formed on the active region surface, and M is used as a charge storage layer.
Forming a gate and a select gate that will be IS capacitors,
In a semiconductor memory device in which the island-shaped semiconductor layer is electrically floated with respect to a semiconductor substrate and the active regions of each memory cell are electrically floated,
A transistor, a MIS capacitor, a transistor, and a MIS capacitor are arranged in this order from the upper part of the island-shaped semiconductor layer, and the gate insulating film thickness of the transistor is equal to the gate insulating film thickness of the MIS capacitor.

Such a semiconductor memory device can be formed by the following manufacturing method. Note that FIG. 150 to FIG.
51 and FIGS. 152 to 153 are cross-sectional views taken along the line AA ′ and the line BB ′ of FIG. 10 showing the memory cell array of the DRAM. In this manufacturing example, unlike the manufacturing example 1, the impurity diffusion layer 710 is not formed, and the polycrystalline silicon films 521 to 524 that are the second conductive films are not formed. First conductive film, polycrystalline silicon 511
To 514 are formed continuously, and the impurity diffusion layers 726 and 727 are formed in the island-shaped semiconductor layer 110.
Are distributed as shown in FIGS. 150 and 152. Note that, in contrast to FIGS. 150 and 152,
Transistors and MI are arranged in this order from the top of the island-shaped semiconductor layer 110.
When arranging the S capacitor, the MIS capacitor, and the transistor, the impurity diffusion layer 710 is formed, and
As shown in FIGS. 151 and 153, the impurity diffusion layers 726 and 727 that form the second groove 220 for separating the impurity diffusion layers in the −B ′ line direction and that are formed in the island-shaped semiconductor layer 110 are formed as shown in FIGS. It is realized by distributing. In this manufacturing example, an example in which two memory cells each including one transistor and one MIS capacitor are arranged in each island-shaped semiconductor layer 110 has been described. One may be arranged, or three or more may be arranged. Further, the introduction of impurities into the polycrystalline silicon films 511 to 514 which are the first conductive films may be performed at the time of forming the polycrystalline silicon film, or after the film formation or the sidewall formation. If it becomes a film, the time of introduction is not limited.

In this manufacturing example, the control gate of each memory cell is formed so as to be continuous in one direction without using a mask. This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent distance to the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, the second wiring layer is separated in the fourth wiring layer direction, A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography.

Manufacturing Example 7 In the semiconductor memory device formed in this Manufacturing Example, an island-shaped semiconductor layer is formed by processing a semiconductor substrate into, for example, a columnar shape, and the side surface of the island-shaped semiconductor layer is used as an active region surface. A plurality of floating gates are formed as tunnel oxide films and charge storage layers on the active region surface, and each island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically connected. In a floating semiconductor memory device, select gate transistors are arranged above and below an island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors. Are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is equal to that of the gate of the memory transistor. Equal to the edge film thickness, each transistor is processed from the bottom to the top. Such a semiconductor memory device can be formed by the following manufacturing method. 154 and 155 are cross-sectional views taken along the line AA ′ and the line BB ′ of FIG. 1 showing the memory cell array of the EEPROM.

In this manufacturing example, the silicon oxide films 481 and 484 which are the thirteenth insulating films are not formed in the manufacturing example 1, but instead the silicon oxide film 42 which is the third insulating film is formed.
This is realized by forming silicon oxide films 421 and 424, which are third insulating films having the same film thickness as 2, 423, respectively (FIGS. 154 and 155). In this manufacturing example, the control gate of each memory cell was formed continuously in one direction without using a mask. This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, separation is made in the fourth wiring layer direction. A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography.

Manufacture Example 8 In the semiconductor memory device formed in this Manufacture Example, an island-shaped semiconductor layer is formed on a semiconductor portion in which an oxide film is inserted, for example, a semiconductor portion of an SOI substrate, and a side surface of the island-shaped semiconductor layer is formed. A plurality of floating gates are formed as an active region surface, a tunnel oxide film and a charge storage layer are formed on the active region surface, and each island semiconductor layer is electrically floated to a semiconductor substrate. In a semiconductor memory device in which an active region is in an electrically floating state, select gate transistors are arranged above and below an island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are sandwiched between the select gate transistors. In this structure, the transistors are arranged in series and the transistors are connected in series along the island-shaped semiconductor layer. Each transistor is formed from the bottom to the top with a thickness larger than the gate insulating film thickness of the transistor. Such a semiconductor memory device can be formed by the following manufacturing method. 156 and 157 are lines AA ′ and B- in FIG. 1 showing the memory cell array of the EEPROM.
It is a B'line sectional view.

This manufacturing example is realized by using a semiconductor substrate having an oxide film inserted therein, for example, an SOI substrate 101, instead of the semiconductor substrate 100 in the manufacturing example 1 (FIGS. 156 and 157). Also in this manufacturing example, the same effect as in manufacturing example 1 can be obtained. Furthermore, the junction capacitance of the impurity diffusion layer 710 which becomes the first wiring layer is suppressed or eliminated. Further, the use of the SOI substrate as the substrate can be applied to all manufacturing examples of the present invention.

Manufacturing Example 9 The semiconductor substrate 100 and the island-shaped semiconductor layer 110 are not separated by the impurity diffusion layer, and the impurity diffusion layer and the semiconductor substrate 100 are not separated.
Alternatively, a method for manufacturing a semiconductor memory device in which the depletion layer existing at the junction of the island-shaped semiconductor layer 110 electrically separates is described below. 158 and 159 show the EEPROM.
1 of FIG. 1 showing the memory cell array of FIG.
It is a B'line sectional view. In FIGS. 158 and 159, the island-shaped semiconductor layer 110 and the semiconductor substrate 100 are structurally connected, but in this manufacturing example, for example, the impurity diffusion layer which is the first wiring layer at the time of reading or erasing. 7
10 and the island-shaped semiconductor layer 110 or the semiconductor substrate 100 due to a potential difference between the impurity diffusion layer 710 and the island-shaped semiconductor layer 11 serving as the first wiring layer.
0 or the island-shaped semiconductor layer 110 of the PN junction formed with the semiconductor substrate 100 or the depletion layer formed on the semiconductor substrate 100 side electrically separates the island-shaped semiconductor layer 110 and the semiconductor substrate 100. That is, when the width of the depletion layer formed on the side of the island-shaped semiconductor layer 110 or the semiconductor substrate 100 is W, the space Sa1 or Sb1 of the impurity diffusion layer 710 which is the first wiring layer shown in FIGS. 158 and 159 is shown. If at least one of the two is less than twice W, it is electrically separated. Impurity diffusion layers 721 to N-type semiconductor layers
Similarly to the impurity diffusion layer 710, which is the first wiring layer, 723 has an active region of each transistor if at least one of Sa2 or Sb2, Sa3 or Sb3, Sa4 or Sb4 is less than twice W. It is electrically separated. The above state may be set at the time of reading and erasing, or the above state may be set only at the time of erasing. The above state may be set at the time of writing. The above state may be obtained by various combinations. This manufacturing example may be applied to any form of the semiconductor memory device of the present invention.

Manufacturing Example 10 In the semiconductor memory device formed in Manufacturing Example 10, an island-shaped semiconductor layer is formed by processing a semiconductor substrate into, for example, a columnar shape, and the side surface of the island-shaped semiconductor layer serves as an active region surface. A plurality of floating gates are formed on the surface of the active region as a tunnel oxide film and a charge storage layer, and each island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically connected. In a semiconductor memory device that is in a floating state, a plurality of memory transistors,
For example, two transistors are arranged and each transistor is connected in series along the island-shaped semiconductor layer, and each transistor is processed and formed from the lower part to the upper part.

Such a semiconductor memory device can be formed by the following manufacturing method. Note that FIG. 160 and FIG. 161 are the same as FIG. 1 showing the memory cell array of the EEPROM.
FIG. 7 is a cross-sectional view taken along line AA ′ and line BB ′ of FIG. In this manufacturing example, polycrystalline silicon 513, 5 which is the first conductive film is used.
14 and the silicon oxide film 423 which is the third insulating film, and the silicon oxide film 484 which is the thirteenth insulating film are not formed,
After separating the impurity diffusion layer 710, the second conductive film polycrystalline silicon 521 is arranged on the side of the first conductive film polycrystalline silicon 511 via the interlayer insulating film 612,
Similarly, the same operation as in Manufacturing Example 1 is performed except that the second conductive film polycrystalline silicon 522 is arranged on the side portion of the first conductive film polycrystalline silicon 512 with the interlayer insulating film 613 interposed therebetween. As a result, a semiconductor memory device having two memory transistors arranged in an island-shaped semiconductor layer and having a memory function according to a charge state accumulated in a charge storage layer having a floating gate of a polycrystalline silicon film serving as a first conductive film is provided. It is realized (FIG. 160 and FIG. 161).

Manufacture Example 11 In the semiconductor memory device formed in this Manufacture Example, an island-shaped semiconductor layer is formed by processing a semiconductor substrate into, for example, a columnar shape, and the side surface of the island-shaped semiconductor layer serves as an active region surface. A plurality of floating gates are formed as tunnel oxide films and charge storage layers on the active region surface, and each island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically connected. In a floating semiconductor memory device, select gate transistors are arranged above and below an island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors. Are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is smaller than that of the memory transistor. It is a large structure and a transmission gate is placed between each memory transistor to transfer a potential to the active region of the memory transistor.

Such a semiconductor memory device can be formed by the following manufacturing method. Note that FIG. 162 and FIG. 163 are the same as FIG. 1 showing the memory cell array of the EEPROM.
FIG. 7 is a cross-sectional view taken along line AA ′ and line BB ′ of FIG. In this manufacturing example, the polycrystalline silicon film 521, which is the second conductive film,
After forming 522, 523, and 524, it can be performed in the same manner as in Manufacturing Example 1 except that a step of forming a gate electrode using the polycrystalline silicon film 530 which is the third conductive film is added. That is, after the second conductive film polycrystalline silicon films 521, 522, 523, and 524 are formed, the first conductive film polycrystalline silicon films 521 and 5 are formed.
The fifth insulating films, that is, the silicon oxide films 424 to 422 and the interlayer insulating films 612 and 613 are removed by isotropic etching to such an extent that the island-shaped semiconductor layer 110 between 22 can be exposed. Then, the oxide film 400, which is a sixteenth insulating film, is formed by using, for example, a thermal oxide film method, the surface of the island-shaped semiconductor layer 110 between the select gate and the memory cell, and the polycrystalline silicon film which is the first and second conductive films. 511, 512, 513, 514,
Formed on the exposed portions of 521, 522, 523, and 524, a polycrystalline silicon film 530 that is a third conductive film is deposited on the entire surface.

Next, the third conductive film polycrystalline silicon film 530 is etched back by anisotropic etching to the extent that the space portions of the second conductive film polycrystalline silicon films 523 and 524 are not exposed. After that, the same procedure as in Manufacturing Example 1 is performed to complete the semiconductor memory device (FIGS. 162 and 163).

Manufacturing Example 12 A specific manufacturing example for obtaining a structure in which the direction of the first wiring layer and the direction of the fourth wiring layer are parallel is shown below. 164 and 165 are cross-sectional views taken along the line AA ′ and the line BB ′ of FIG. 1 showing the memory cell array of the EEPROM. In this manufacturing example, the second groove 220 for separating the impurity diffusion layer 710 is not formed in a self-aligned manner with respect to the polycrystalline silicon 511 which is the first conductive film, and for example, a pattern is formed by a known photolithography technique. 1 except that the second groove portion 220 is formed so that the impurity diffusion layer 710 is separated in the AA ′ line direction of FIG. 1 by reactive ion etching using the resist thus patterned as a mask.
This is the same as in Production Example 1. As a result, a semiconductor memory having a memory function according to a charge state accumulated in a charge storage layer having a floating gate of a polycrystalline silicon film serving as a first conductive film in which the first wiring layer and the fourth wiring layer are parallel to each other. The device is realized (FIGS. 164 and 165).

The introduction of impurities into the polycrystalline silicon films 511 to 514 which are the first conductive film and the polycrystalline silicon films 521 to 524 which are the second conductive film is performed at the time of forming the polycrystalline silicon film. It may be performed after the film formation or after the sidewall formation, and the introduction time is not limited as long as it is a conductive film. In this manufacturing example, the control gate of each memory cell was formed continuously in one direction without using a mask. This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent distance to the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, the second wiring layer is separated in the fourth wiring layer direction, A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography. Further, by disposing the select gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is in a negative state. However, the phenomenon that the cell current flows can be prevented.

Manufacturing Example 13 A specific manufacturing example for obtaining a structure in which the first wiring layer is electrically common to the memory array will be shown. Note that FIG.
6 and 167 are sectional views taken along the line AA 'and the line BB' in FIG. 1 showing the memory cell array of the EEPROM.
In this manufacturing example, the second groove portion 220 is formed on the semiconductor substrate 100.
This is the same as the manufacturing example 1 in which the steps related thereto were omitted without forming the above. As a result, at least the first wiring layer in the array becomes common without being divided, and has a memory function by the charge state accumulated in the charge accumulation layer having the polycrystalline silicon film serving as the first conductive film as the floating gate. A semiconductor memory device is realized (FIGS. 166 and 167).

Production Example 14 In the method of forming the island-shaped semiconductor layer, the fourth wiring layer 8 is used.
40. The distribution region of the impurity diffusion layer 724 located at the upper end of the semiconductor layer 110, which is connected to the semiconductor layer 40, is formed on the semiconductor substrate without shortening the gate length of the select gate transistor arranged at the upper end of the island-shaped semiconductor layer 110. A specific manufacturing process example in the case of increasing the size in the vertical direction will be described. Note that FIG.
8 and 169 are sectional views taken along the line AA 'and the line BB' in FIG. 1 showing the memory cell array of the EEPROM.
In this manufacturing example, in the manufacturing example 1, the fourth wiring layer 84
It is realized by forming the semiconductor layer 724 connected to 0 to be high (FIGS. 168 and 169). At this time, the thickness of the silicon oxide film 465 which is the tenth insulating film can be set thick, and the polycrystalline silicon film 5 which is the second conductive film can be formed.
The insulation between the wiring 24 and the fourth wiring layer 840 is improved. Alternatively, when the impurity diffusion layer 724 is exposed, the exposed area can be set large, so that the contact resistance between the impurity diffusion layer 724 and the fourth wiring layer 840 is reduced.

Manufacture Example 15 A concrete manufacture example in the case where the lengths of the gates of the transistors in the vertical direction are different from each other in the method of forming the island-shaped semiconductor layer will be shown. 170 to 171 and 712.
1 to 173 are cross-sectional views taken along the line AA 'and the line BB' of FIG. 1 showing the memory cell array of the EEPROM. As shown in FIGS. 170 and 172, the polycrystalline silicon films 511 to 514, which are the first conductive films serving as the gates or the select gates of the memory cells, have a select gate length in the direction perpendicular to the semiconductor substrate 100. May be different. Further, as shown in FIGS. 171 and 173, even if the gate lengths of the memory cells of the first conductive film polycrystalline silicon films 512 and 513 are different, the first conductive film polycrystalline silicon film 511 is used. Vertical lengths of ˜514 do not have to be the same length.

Manufacture Example 16 In the semiconductor memory device formed in this Manufacture Example, a semiconductor substrate is processed to form an island-shaped semiconductor layer, and the side surface of the island-shaped semiconductor layer serves as an active region surface. A plurality of floating gates are formed as a tunnel oxide film and a charge storage layer, and each island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically floated. In this semiconductor memory device, select gate transistors are arranged above and below an island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors. Connected in series along the semiconductor layer,
Select gate transistor gate insulation film thickness is memory
The structure is larger than the gate insulating film thickness of the transistor, and the shape of the island-shaped semiconductor layer is not cylindrical, and each transistor is processed and formed from the lower part to the upper part.

Such a semiconductor memory device can be formed by the following manufacturing method. 174 to FIG.
75 and FIGS. 176 to 177 are cross-sectional views taken along the line AA ′ and the line BB ′ of FIG. 1 showing the memory cell array of the EEPROM. When the island-shaped semiconductor layer 110 is formed by the reactive ion etching and the outer shapes of the upper end portion and the lower end portion of the island-shaped semiconductor layer 110 are different, the shapes are as shown in FIGS. 174 and 176. 175 and 177 when the horizontal positions of the upper end portion and the lower end portion of the island-shaped semiconductor layer 110 are displaced. For example, when the island-shaped semiconductor layer 110 from the top has a circular shape, the former has a conical shape and the latter has an oblique columnar structure. The shape of the island-shaped semiconductor layer 110 is not particularly limited as long as the memory cells can be arranged in series in the direction perpendicular to the semiconductor substrate 100.

Production Example 17 In the method of forming the island-shaped semiconductor layer, the island-shaped semiconductor layer 1
A specific manufacturing example of the shape of the bottom portion of 10 will be shown. 178 to 181 and 182 to 185 show E
FIG. 2 is a sectional view taken along the line AA ′ and the line BB ′ of FIG. 1, showing a memory cell array of the EPROM. The bottom shape of the first grid-like groove 210 is shown in FIGS. 180, 184, and 181.
And may have a linear inclined structure as shown in FIG. 185. In addition, the bottom shape of the lattice-striped first groove portion 210 may have a rounded inclined structure as shown in FIGS. 178 and 182, 179 and 183. Here, the lower end portion of the polycrystalline silicon film 511 serving as the first conductive film may or may not reach the inclined portion of the bottom portion of the first groove portion 210.

Manufacture Example 18 In the method in which each transistor is processed from the bottom to the top after the island-shaped semiconductor layer is formed, the structure in which the control gate is covered on the side surface and the top surface of the floating gate through the interlayer insulating film is adopted. A specific production example for obtaining is shown. Note that FIG.
86 and FIG. 187 are sectional views taken along the line AA ′ and the line BB ′ of FIG. 1 showing the memory cell array of the EEPROM. In this manufacturing example, unlike the manufacturing example 1, after the polycrystalline silicon films 522 and 523 to be the second conductive films are deposited, the polycrystalline silicon films 512 and 513 are the first conductive films, respectively.
It is realized by etching back up to the upper end of, for example, isotropic etching (FIGS. 186 and 18).
7). As a result, in the polycrystalline silicon film 512, which is the first conductive film, the area in contact with the polycrystalline silicon film 522, which is the second conductive film, via the interlayer capacitance film 612 is increased, and it is the first conductive film. Since the area of the polycrystalline silicon film 513 in contact with the polycrystalline silicon film 523 which is the second conductive film is increased via the interlayer capacitance film 613, the coupling ratio in each memory cell is improved.

Manufacture Example 19 Electrical connection between the first, second and third wiring layers and the peripheral circuit is realized by a method of forming each island-shaped semiconductor layer from the bottom to the top after forming the island-shaped semiconductor layer. A specific manufacturing example of the terminal is shown. 188 to 193
Is H- in FIG. 8 showing the memory cell array of the EEPROM.
H'line, I1-I1 'line, I2-I2' line, I3-I
FIG. 3 is a cross-sectional view taken along line 3 ′, line I4-I4 ′, and line I5-I5 ′, showing that the embedded wiring layer is embedded with a terminal arranged on the upper surface of the semiconductor device in order to apply a voltage from the outside. Electrical connection sites 921, 932, 9
33, 934, and 910 are sectional views at positions where they can be respectively confirmed.

The first, second, and third wiring layers embedded in the wiring layer lead-out portion are arranged in a staircase pattern as shown in FIGS. 188 to 193, and desired wirings are formed from the end portions of the respective wiring layers. The first, second, and third contacts 921, 932, 933, 93 are arranged so as not to intersect wiring layers other than the wiring layer.
After opening 4, 910, for example, a silicon oxide film 492 is deposited as a fifteenth insulating film in a thickness of 10 to 100 nm, and then etched back by about the deposited film thickness to form a contact formed in the wiring layer lead portion. The side wall of the silicon oxide film 492 which is the fifteenth insulating film is formed on the inner wall, and then a metal or a conductive film is embedded in the contact portion to form the first wiring layer and the second and third wiring layers. To the upper surface of the semiconductor device. The first, second and third contacts 921, 932, 933, 93
The same effect may be obtained by forming the conductive film on the upper surface of the semiconductor device without forming 4, 910.

A silicon oxide film 49, which is a fifteenth insulating film, is formed on the inner wall of the contact formed in the wiring layer lead portion.
It is not necessary to form the second side wall. When the sidewall of the silicon oxide film 492 which is the fifteenth insulating film is formed on the inner wall of the contact formed in the wiring layer lead portion, the silicon oxide film 492 which is the fifteenth insulating film is not limited to the silicon oxide film. Alternatively, it may be a silicon nitride film and is not limited as long as it is an insulating film. As shown in FIGS. 188 to 193, the contact for drawing out the wiring layer may be formed in common in the wiring layer drawing section of the memory cells continuous in the adjacent AA ′ direction, or each wiring may be formed. You may form in a layer extraction part. Extracting the first wiring layer and the second and third wiring layers to the upper surface of the semiconductor by the above method can be applied to all the embodiments of the present invention.

Example 20 A specific manufacturing example of the shape of the polycrystalline silicon film coated on the island-shaped semiconductor layer 110 when the transistors are processed from the bottom to the top after forming the island-shaped semiconductor layer Indicates. Note that FIG. 194 to FIG. 195 and FIG. 196 to FIG. 197 are the same as FIG.
FIG. 7 is a cross-sectional view taken along line AA ′ and line BB ′ of FIG. As shown in FIGS. 194 and 196, 195 and 197, the polycrystalline silicon film 510, which is the first conductive film and is covered with the island-shaped semiconductor layer 110, extends along the bottom shape of the first groove portion 210. It may exhibit a uniformly deposited structure. Further, depending on the shape of the bottom of the first groove 210, the structure may be partially unevenly deposited.

Manufacturing Example 21 When each transistor is processed from the bottom to the top after forming the island-shaped semiconductor layer, the shape of the silicon nitride film 310 as the first insulating film is formed after the island-shaped semiconductor layer 110 is formed. A specific manufacturing example of is shown. 198 to 1
99 and FIGS. 200 to 201 are cross-sectional views taken along the line AA ′ and the line BB ′ in FIG. 1 showing the memory cell array of the EEPROM. In Production Example 1 (FIGS. 82 and 92),
Using the resist R1 patterned by a known photolithography technique as a mask, the mask layer 310 is etched by reactive ion etching, and the p-type semiconductor substrate 100 is 2,000 to 20000 nm by reactive ion etching using the mask layer 310. The mask layer 310 may be smaller than the outer shape of the island-shaped semiconductor layer 110 (FIGS. 198 and 200) or larger than the outer shape of the island-shaped semiconductor layer 110 (FIGS. 199 and 201) when the first groove portions 210 having a lattice stripe shape are etched. The shape of the mask layer 310 is not particularly limited.

As shown in the above-described manufacturing example, an embodiment of the present invention will be described in which each transistor is processed from the bottom to the top on the side surface of the island-shaped semiconductor layer 110 formed by processing the semiconductor substrate. However, various combinations may be used. Further, a plurality of memory cells each having a charge storage layer and a control gate are connected in series in a direction perpendicular to the surface of the semiconductor substrate, and the memory cells are arranged in a matrix in which the semiconductor substrate and the semiconductor substrate are separated in a lattice stripe pattern. The impurity diffusion layer formed on the sidewalls of the plurality of island-shaped semiconductor layers formed in the island-shaped semiconductor layer serves as the source or drain of the memory cell, and the impurity diffusion layer electrically connects the semiconductor substrate and the island-shaped semiconductor layer. The control gate lines are separated from each other, and the control gates are arranged continuously with respect to the plurality of island-shaped semiconductor layers in one direction and in the horizontal direction with respect to the semiconductor substrate surface. Although the embodiment of the present invention having the bit line electrically connected to the impurity diffusion layer in the direction intersecting with and having the bit line arranged in the horizontal direction with respect to the semiconductor substrate surface has been described. It may be used in combination.

[0118]

According to the method of manufacturing a semiconductor memory device of the present invention, it becomes possible to avoid or prevent the back bias effect of the substrate in the vertical direction of the island-shaped semiconductor layer, and prevent the variation between the bit line and the source line. A semiconductor memory device capable of forming a plurality of memory cells connected in series can be efficiently manufactured. This makes it possible to create a high-performance device that prevents the occurrence of variations in the characteristics of the memory cells due to the reduction in the threshold value of each memory cell at the time of reading due to the back bias effect from the substrate. Further, the vertical direction, which is the direction that determines the device performance, can be further miniaturized without depending on the minimum processing dimension.

Further, the capacity can be increased. For example,
When the diameter of the semiconductor substrate cylinder provided with the memory transistor is formed with the minimum processing size and the shortest distance of the space width between the semiconductor substrate columns is configured with the minimum processing size, the number of steps of the memory transistor per semiconductor substrate cylinder is two. In this case, the capacity twice that of the conventional one can be obtained. That is, it is possible to increase the capacity by as many as the number of memory transistor stages per semiconductor substrate cylinder. Generally, the larger the number of stages, the larger the capacity. As a result, the cell area per bit is reduced, and the chip size and cost can be reduced. Moreover, the vertical direction, which is the direction that determines the device performance, does not depend on the minimum processing dimension, and the device performance can be maintained.

Further, since each memory cell is arranged so as to surround the island-shaped semiconductor layer, it is possible to manufacture a device in which the driving current is improved and the S value is increased. Further, after the semiconductor substrate is processed into a columnar shape using a circular pattern, the side surface of the semiconductor substrate is sacrificial-oxidized to remove damages, defects and irregularities on the substrate surface, so that it can be used as a good active region surface. it can. At this time, the diameter of the pillar can be controlled by controlling the oxide film thickness, and the surface area of the tunnel oxide film and the surface area of the interlayer capacitance film between the floating gate and the control gate can be controlled to determine the capacitance between the floating gate and the control gate. Can be easily increased.

Further, by using a circular pattern, it is possible to avoid the occurrence of local electric field concentration on the active region surface, and electrical control can be easily performed. Further, by disposing the transistor on the columnar semiconductor substrate so as to surround the gate electrode of the transistor, the drive current and the S value can be improved. By forming the impurity diffusion layer so that the active region of each memory cell is in a floating state with respect to the substrate, the back bias effect from the substrate is eliminated, and the characteristics of the memory cell are reduced due to the decrease in the threshold value of each memory cell during reading. There is no variation. After the tunnel oxide film and floating gate deposition,
By forming a plurality of sidewalls of the insulating film in the vertical direction on the sidewalls of the floating gate, the floating gates can be collectively processed. That is, the same tunnel oxide film can be obtained for each memory cell. By using these methods, variations in characteristics of memory cells are suppressed, variations in device performance are suppressed, control is facilitated, and cost reduction is realized.

[Brief description of drawings]

FIG. 1 is a plan view showing a memory cell array of an EEPROM having a floating gate as a charge storage layer in a semiconductor memory device of the present invention.

FIG. 2 EEP having a floating gate as a charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 3 EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 4 EEP having a floating gate as a charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 5: EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 6 EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 7: EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 8: EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 9 is a MON having a laminated insulating film as a charge storage layer.
FIG. 3 is a plan view showing a memory cell array having an OS structure.

FIG. 10 is a plan view showing a memory cell array having a DRAM structure having a MIS capacitor as a charge storage layer.

FIG. 11 is a plan view showing a memory cell array having an SRAM structure having a MIS transistor as a charge storage layer.

FIG. 12 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer in the semiconductor memory device of the present invention.

FIG. 13 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 14 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 15 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.

16 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 17 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 18 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 19 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 20 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 21 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

22 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

23 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 24 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 25 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 26 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 27 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 28 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 29 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 30 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 31 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 32 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 33 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 34 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 35 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

36 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

37 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

38 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

39 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 40 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of the semiconductor memory device having the laminated insulating film as the charge storage layer.

41 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of the semiconductor memory device having the laminated insulating film as the charge storage layer.

42 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of another semiconductor memory device having a laminated insulating film as a charge storage layer.

43 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of another semiconductor memory device having a laminated insulating film as a charge storage layer.

44 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

45 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

46 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

47 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

48 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

49 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

50 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

51 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a laminated insulating film as a charge storage layer.

52 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 11 of the semiconductor memory device having the MIS capacitor as the charge storage layer.

53 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 11 of the semiconductor memory device having the MIS capacitor as the charge storage layer.

54 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 11 of another semiconductor memory device having a MIS capacitor as a charge storage layer.

55 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 11 of another semiconductor memory device having a MIS capacitor as a charge storage layer.

[FIG. 56] AA ′ in FIG. 11 of still another semiconductor memory device having a MIS capacitor as a charge storage layer.
It is sectional drawing corresponding to a sectional view.

57 is a sectional view taken along line BB ′ in FIG. 11 of still another semiconductor memory device having a MIS capacitor as a charge storage layer.
It is sectional drawing corresponding to a sectional view.

58 is a cross-sectional view corresponding to the J1-J1 ′ cross-sectional view in FIG. 12 of the semiconductor memory device having the MIS transistor as the charge storage layer.

59 is a cross-sectional view corresponding to the J2-J2 ′ cross-sectional view in FIG. 12 of the semiconductor memory device having the MIS transistor as the charge storage layer.

FIG. 60 is a cross-sectional view corresponding to the K1-K1 ′ cross-sectional view in FIG. 12 of another semiconductor memory device having a MIS transistor as a charge storage layer.

61 is a cross-sectional view corresponding to the K2-K2 ′ cross-sectional view in FIG. 12 of another semiconductor memory device having a MIS transistor as a charge storage layer.

FIG. 62 is an equivalent circuit diagram of the semiconductor memory device of the present invention.

FIG. 63 is another equivalent circuit diagram of the semiconductor memory device of the present invention.

64 is another equivalent circuit diagram of the semiconductor memory device of the present invention. FIG.

FIG. 65 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the MONOS structure of the present invention.

FIG. 66 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the MONOS structure of the present invention.

67 is another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the DRAM structure of the present invention. FIG.

68 is another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the DRAM structure of the present invention. FIG.

FIG. 69 is another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the DRAM structure of the present invention.

70 is another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the DRAM structure of the present invention. FIG.

71 is a further equivalent circuit diagram of the semiconductor memory device of the present invention. FIG.

72 is another equivalent circuit diagram of the semiconductor memory device of the present invention. FIG.

FIG. 73 is another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the SRAM structure of the present invention.

FIG. 74 is another equivalent circuit diagram of the semiconductor memory device having the memory cell array having the SRAM structure of the present invention.

FIG. 75 is a diagram showing an example of a timing chart at the time of reading of the semiconductor memory device of the present invention.

FIG. 76 is a diagram showing an example of a timing chart at the time of reading of the semiconductor memory device of the present invention.

FIG. 77 is a diagram showing an example of a timing chart at the time of reading of the semiconductor memory device of the present invention.

FIG. 78 is a diagram showing an example of a timing chart at the time of writing in the semiconductor memory device of the present invention.

FIG. 79 is a diagram showing an example of a timing chart at the time of writing in the semiconductor memory device of the present invention.

FIG. 80 is a diagram showing an example of a timing chart at the time of erasing of the semiconductor memory device of the present invention.

81 is a diagram showing an example of a timing chart at the time of erasing of the semiconductor memory device of the present invention. FIG.

FIG. 82 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 83 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 84 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 85 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 86 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a first manufacturing example of the semiconductor memory device of the present invention.

FIG. 87 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

88 is a cross-sectional (AA 'line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention. FIG.

FIG. 89 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 90 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 91 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 92 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 93 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 94 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 95 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

96 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention. FIG.

97 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention. FIG.

98 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention. FIG.

99 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention. FIG.

FIG. 100 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

101 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention. FIG.

102 is a sectional (AA 'line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention; FIG.

103 is a sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention; FIG.

FIG. 104 is a sectional (AA ′ line in FIG. 1) process diagram showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 105 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 106 is a sectional (AA ′ line in FIG. 1) process diagram showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 107 is a sectional (AA ′ line in FIG. 1) process diagram showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 108 is a sectional (AA ′ line in FIG. 1) process diagram showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 109 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

110 is a sectional (AA 'line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention; FIG.

111 is a sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

112 is a sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

113 is a sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 114 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

115 is a sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 116 is a sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

117 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

118 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 119 is a sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

120 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 121 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

122 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 123 is a sectional (BB ′ line in FIG. 1) process diagram showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 124 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 125 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

126 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

127 is a sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 128 is a sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 129 is a sectional (BB ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 130 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention.

131 is a cross-sectional (AA 'line in FIG. 1) process drawing showing Production Example 3 of the semiconductor memory device of the present invention. FIG.

132 is a sectional (AA 'line in FIG. 1) process drawing showing a third example of manufacturing the semiconductor memory device of the present invention. FIG.

FIG. 133 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 3 of the semiconductor memory device of the present invention.

FIG. 134 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 3 of the semiconductor memory device of the present invention.

FIG. 135 is a cross-sectional (AA 'line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention.

FIG. 136 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention.

137 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention. FIG.

138 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention. FIG.

139 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 140 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention.

141 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 142 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 3 of the semiconductor memory device of the present invention.

FIG. 143 is a sectional (BB ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention.

FIG. 144 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 4 of the semiconductor memory device of the present invention.

FIG. 145 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a fourth example of manufacturing the semiconductor memory device of the present invention.

FIG. 146 is a sectional (BB ′ line in FIG. 1) process drawing showing a fourth manufacturing example of the semiconductor memory device of the present invention.

FIG. 147 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 4 of the semiconductor memory device of the present invention.

148 is a sectional (AA ′ line in FIG. 9) process drawing showing a fifth example of manufacturing the semiconductor memory device of the present invention. FIG.

FIG. 149 is a sectional (BB ′ line in FIG. 9) process drawing showing a fifth example of manufacturing the semiconductor memory device of the present invention.

FIG. 150 is a cross-sectional (AA ′ line in FIG. 9) process drawing showing a sixth manufacturing example of the semiconductor memory device of the present invention.

151 is a cross-sectional (AA 'line in FIG. 9) process drawing showing a sixth manufacturing example of the semiconductor memory device of the present invention. FIG.

152 is a cross-sectional (BB ′ line in FIG. 9) process drawing showing Production Example 6 of the semiconductor memory device of the present invention. FIG.

153 is a cross-sectional (BB ′ line in FIG. 9) process drawing showing a sixth manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 154 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a seventh manufacturing example of the semiconductor memory device of the present invention.

155 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a seventh manufacturing example of the semiconductor memory device of the present invention. FIG.

156 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 8 of the semiconductor memory device of the present invention. FIG.

157 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 8 of the semiconductor memory device of the present invention. FIG.

FIG. 158 is a sectional (AA ′ line in FIG. 1) process drawing showing a ninth example of manufacturing the semiconductor memory device of the present invention.

FIG. 159 is a sectional (BB ′ line in FIG. 1) process drawing showing a ninth example of manufacturing the semiconductor memory device of the present invention.

FIG. 160 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 10 of the semiconductor memory device of the present invention.

161 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 10 of the semiconductor memory device of the present invention. FIG.

162 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 11 of the semiconductor memory device of the present invention. FIG.

FIG. 163 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 11 of the semiconductor memory device of the present invention.

FIG. 164 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 12 of the semiconductor memory device of the present invention.

FIG. 165 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 12 of the semiconductor memory device of the present invention.

166 is a sectional (AA 'line in FIG. 1) process drawing showing a manufacturing example 13 of the semiconductor memory device of the present invention. FIG.

FIG. 167 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 168 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 14 of the semiconductor memory device of the present invention.

FIG. 169 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 14 of the semiconductor memory device of the present invention.

170 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention. FIG.

171 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention. FIG.

172 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention. FIG.

173 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention. FIG.

FIG. 174 is a sectional (AA ′ line in FIG. 1) process drawing showing a sixteenth manufacturing example of the semiconductor memory device of the present invention.

175 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 16 of the semiconductor memory device of the present invention. FIG.

176 is a sectional (BB ′ line in FIG. 1) process drawing showing a sixteenth manufacturing example of the semiconductor memory device of the present invention; FIG.

177 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a sixteenth manufacturing example of the semiconductor memory device of the present invention. FIG.

178 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention. FIG.

179 is a sectional (AA ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention; FIG.

180 is a sectional (AA 'line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention. FIG.

181 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.

182 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.

183 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.

184 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.

185 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.

FIG. 186 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention.

187 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention. FIG.

188 is a sectional (HH ′ line in FIG. 8) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention. FIG.

189 is a sectional (I1-I1 ′ line in FIG. 8) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention; FIG.

190 is a sectional (I2-I2 ′ line in FIG. 8) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention. FIG.

191 is a sectional (I3-I3 ′ line in FIG. 8) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention. FIG.

192 is a sectional (I4-I4 ′ line in FIG. 8) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention; FIG.

193 is a sectional (I5-I5 ′ line in FIG. 8) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention. FIG.

FIG. 194 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 20 of the semiconductor memory device of the present invention.

195 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 20 of the semiconductor memory device of the present invention. FIG.

196 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 20 of the semiconductor memory device of the present invention. FIG.

197 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 20 of the semiconductor memory device of the present invention. FIG.

FIG. 198 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 21 of the semiconductor memory device of the present invention.

199 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 21 of the semiconductor memory device of the present invention; FIG.

200 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 21 of the semiconductor memory device of the present invention. FIG.

201 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 21 of the semiconductor memory device of the present invention. FIG.

FIG. 202 is a plan view showing a conventional EEPROM.

203 is a cross-sectional view taken along the line AA ′ and the line BB ′ of FIG. 202.

FIG. 204 is a step sectional view showing the method of manufacturing the conventional EEPROM.

205 is a process sectional view showing the manufacturing method of the conventional EEPROM. FIG.

FIG. 206 is a process cross-sectional view showing the method of manufacturing the conventional EEPROM.

FIG. 207 is a process cross-sectional view showing the method of manufacturing the conventional EEPROM.

FIG. 208 is a plan view of a conventional EEPROM and a corresponding equivalent circuit diagram.

FIG. 209 is a cross-sectional view of a conventional MNOS structure memory cell.

FIG. 210 is a cross-sectional view of another conventional MNOS structure memory cell.

211 is a cross-sectional view of a semiconductor device in which a plurality of memory cells are formed in one columnar silicon layer. FIG.

[Explanation of symbols]

100, 3100 Silicon substrate (semiconductor substrate) 101 SOI semiconductor substrate (semiconductor substrate) 110, 3110 Island semiconductor layers 210, 220 Groove parts 400, 410, 420, 431, 432, 441, 4
42, 443, 450, 460, 461, 462, 46
3, 464, 465, 471, 481, 484, 49
0, 491, 492, 491, 492, 495, 49
9, 3420, 3431, 3434, 3471 Silicon oxide films 310, 321, 322, 323, 324, 331, 3
40, 341, 342, 343, 350, 351, 35
2,353 Silicon nitride films 500, 510, 511, 512, 513, 514, 5
20, 521, 522, 523, 524, 530, 35
11, 3512, 3513, 3514 polycrystalline silicon films 612, 613 interlayer insulating films 622, 623 laminated insulating films 710, 721, 722, 723, 724, 725, 7
26, 727, 3710, 3721, 3724 Impurity diffusion layers 810, 821, 824, 832, 833, 840, 3
840, 3850 Wiring layers 910, 921, 932, 933, 924 Contact portions R1, R11, R12 Resist

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/115 H01L 27/10 671C 29/788 29/792 (72) Inventor Takuji Tanigami Osaka City, Osaka Prefecture 22-22 Nagaike-cho, Abeno-ku, Sharp Corporation (72) Inventor Kei Yokoyama 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture 72, Inventor, Noboru Takeuchi 22, Nagaike-cho, Abeno-ku, Osaka No. 22 F-term in Sharp Corporation (reference) 5F083 AD03 AD04 BS02 EP02 EP18 EP22 EP55 EP56 EP76 ER03 ER05 ER09 ER19 ER23 ER30 HA02 JA04 LA12 LA16 PR39 PR40 5F101 BA01 BA29 BA36 BA45 BA46 BB02 BC02 BC11 BD10 BD16 BD22 BD30 BD30 BE06 BH19

Claims (10)

[Claims] 1. A step of forming at least one island-shaped semiconductor layer on a semiconductor substrate, a step of forming a tunnel insulating film on the surface of the island-shaped semiconductor layer, and a division in the height direction on the tunnel insulating film. Forming a side wall spacer made of the separated first conductive film, forming an impurity diffusion layer by introducing impurities into the divided first conductive film in a self-aligned manner, and By including a step of forming an interlayer capacitance film and a second conductive film on the film, the semiconductor substrate, at least one island-shaped semiconductor layer, and all or part of the periphery of the sidewall of the island-shaped semiconductor layer are formed. And a at least one memory cell including a charge storage layer and a control gate, wherein at least one of the memory cells is electrically insulated from the semiconductor substrate. The method of manufacturing a semiconductor memory device that. 2. A step of forming at least one island-shaped semiconductor layer on a semiconductor substrate, a step of forming a tunnel insulating film on the surface of the island-shaped semiconductor layer, and a charge made of a laminated insulating film on the tunnel insulating film. A step of forming a storage layer, a step of forming a sidewall spacer made of a first conductive film divided in the height direction on the charge storage layer, and a self-alignment with the divided first conductive film And the step of forming an impurity diffusion layer by introducing impurities into the semiconductor substrate, at least one island-shaped semiconductor layer, and all or part of the periphery of the sidewall of the island-shaped semiconductor layer. A semiconductor memory device having at least one memory cell including a charge storage layer and a control gate, wherein at least one of the memory cells is electrically insulated from the semiconductor substrate. The method of manufacturing a semiconductor memory device according to. 3. A step of forming at least one island-shaped semiconductor layer on a semiconductor substrate, a step of introducing impurities into a part of the surface of the island-shaped semiconductor layer to form an impurity diffusion layer, and the island-shaped semiconductor. A step of forming a sidewall spacer made of a first conductive film divided in the height direction on the surface of the layer with an insulating film interposed between the semiconductor substrate, the at least one island-shaped semiconductor layer, and the island. At least one memory cell composed of a charge storage layer and a control gate formed on all or part of the periphery of the sidewall of the semiconductor layer, and at least one of the memory cells is electrically connected to the semiconductor substrate. A method of manufacturing a semiconductor memory device, which comprises manufacturing an insulated semiconductor memory device. 4. A step of diffusing impurities in the island-shaped semiconductor layer so that the impurity diffusion layers are connected in a direction horizontal to the semiconductor substrate surface so that the memory cells are electrically isolated from each other. The method for manufacturing a semiconductor memory device according to claim 1, further comprising: 5. The width of the island-shaped semiconductor layer in one direction is formed by forming the island-shaped semiconductor layer in a plurality of matrix shapes, further oxidizing the sidewalls of the island-shaped semiconductor layer, and removing the oxide film. 5. The method for manufacturing a semiconductor memory device according to claim 1, wherein the distance is smaller than the distance between the island-shaped semiconductor layers. 6. A channel layer formed immediately below the first conductive film facing the island-shaped semiconductor layer is electrically connected to an adjacent channel layer when processing the first conductive film into a sidewall shape. The first conductive film is divided into two or more so that the first conductive films are arranged close to each other to the extent that they are formed.
A method of manufacturing a semiconductor memory device according to any one of 1. 7. The third conductive film is further provided between the divided first conductive films.
7. The method for manufacturing a semiconductor device according to claim 2, further comprising the step of disposing the conductive film. 8. An insulating film is formed on a part of the surface of the island-shaped semiconductor layer, and another insulating film is formed on another part of the surface, and the first conductive film is formed on the insulating film and the other insulating film. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed on a film. 9. A charge storage layer made of an interlayer insulating film is formed in a part of the surface of the island-shaped semiconductor layer, and another insulating film is formed in another part of the surface, and the first conductive film is The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed on a charge storage layer and another insulating film. 10. A semiconductor substrate, at least one island-shaped semiconductor layer, at least one memory cell including a charge storage layer formed on all or part of the periphery of the sidewall of the island-shaped semiconductor layer, and a control gate. And a part of the charge storage layer and the control gate electrode are formed of different materials, and at least one of the memory cells is electrically insulated from the semiconductor substrate. Semiconductor memory device.