JP2003092299A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the deterioration and variance of dielectric strength and a leak current of an element by improving the planarity of the surface of a conductive thin film, and to form a thin insulating film layer by using it as a base electrode layer. SOLUTION: A main metal layer 303 is deposited first, and an element 305 is supplied and stuck on the metal as a surfactant and then annealed to planarize the surface of electrode layer.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method of forming a conductive thin film layer such as an electrode layer or a wiring layer on a semiconductor substrate by attaching a surfactant to the surface of a main metal and annealing it. TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device that flattens the surface of a thin film layer.

[0002]

2. Description of the Related Art Conventionally, there are various conductive thin film layer forming steps in the manufacturing process of a semiconductor device. For example, the electrode metal layers of the source, gate, and drain parts of the field-effect transistor element part, the upper electrode layer and the lower electrode layer of the capacitor element part, and the wiring layer for connecting each of these elements within and between layers. Is.

As an example of how various conductive thin film layers exist in a semiconductor device, the first document "UL
SI process technology: Baifukan, H. Hara ”. Figure 1 corresponds to Figure 1.2 shown on page 2 of the first document. This diagrammatically shows a cross section in the vicinity of one element unit of a CMOS (mutual compensation type MOS structure field effect type) transistor constituting a ULSI which is a typical example of a semiconductor device.

A region shown by hatching in FIG. 1 is a conductive thin film layer. First, it can be seen that the conductive thin film 104 made of TiSi alloy metal is formed on the source and drain of the transistor to establish an electrical connection. Then, on top of that, for connecting to the upper conductive layer, W
A conductive thin film layer 105 made of (tungsten) metal is formed. Further, a wiring layer 106, which is a conductive thin film layer made of Al (aluminum) metal, is formed on the top of the wiring layer for connection between elements and between layers. Furthermore, a conductive thin film layer 107 made of W metal is formed again on the upper part of
Finally, the wiring layer 10 which is a conductive thin film layer made of Al metal again
8 is formed. In addition, a conductive thin film layer having a laminated structure of poly-Si (polysilicon: polycrystalline Si, which is made conductive by doping) and WSi (tungsten silicide) is formed above the gate portion of the transistor. There is. As described above, a single semiconductor device has a complicated shape and a large number of elements connected to each other by a conductive thin film layer, although the details of use, function, and shape are different.

The formation of these conductive thin film layers is mainly performed by the sputtering method. In addition, a CVD (chemical vapor deposition) method, an EB (electron beam) heating vapor deposition method, a plating method and the like are also performed. The material selection of the conductive thin film is mainly determined by conductivity, heat resistance, coverage (covering performance), element diffusion preventing performance (barrier effect), suitability for a forming method, and the like. For example, TiSi, W, Al, and WSi are formed by a sputtering method, and poly-Si is formed by a plasma CVD method. Further, for example, one of them may be formed by the CVD method.

The formation of a conductive thin film using these methods has been devised carefully, and optimized to achieve the above performance.

By the way, no attention has been paid to the flatness of the surface (or interface) in the step of forming the conductive thin film in the conventional semiconductor device manufacturing method. Whether the sputtering method, the CVD method, or the EB heating vapor deposition method is used, the flatness (roughness) of the metal layer surface is about 10 nm or more. It is thought that this is because in the microscopic area, fine metal crystals are formed and aggregated during deposition in the microscopic region and crystallize in a so-called polycrystalline state, so that irregularities are formed in the order of the minimum grain size. . On the other hand, the film thickness of the conductive thin film layer and other layers such as an insulating film layer generally laminated on the conductive thin film is usually 100 to 500 nm. Therefore, it could be considered that the flatness of the surface with respect to those film thicknesses was sufficiently high. That is, it could be considered that the surface roughness was sufficiently small.

For example, in one of the capacitor structures actually used at present, the lower electrode metal layer is a conductive thin film layer made of AlCu (aluminum-copper alloy) with a thickness of 300 nm, and the upper 90
An insulating film layer of Si ₃ N ₄ of 300 nm is laminated, and a conductive thin film layer of AlCu of 300 nm is further laminated on the insulating film layer. At this time, the lower electrode layer AlCu is formed by the sputtering method, and the surface thereof also has a roughness of 10 nm or more (root mean square value: Rms> 10 nm). However, in this case, the Si ₃ N ₄ insulating film layers sandwiched between them are required to have a leak current of 10 ⁻⁶ cm ⁻² or less and a breakdown voltage of 1 MV / cm or more. 90n
Even if the surface roughness of the lower electrode layer is 10 nm or more with respect to a certain Si ₃ N ₄ insulating film, both performances are not significantly deteriorated and no problem occurs.

[0009]

However, when considering further performance development of the semiconductor device and development of a new semiconductor device, the roughness of about 10 nm on the surface of the conductive thin film may become a problem.

For example, in the capacitor structure composed of the AlCu upper electrode / Si ₃ N ₄ insulating film layer / AlCu lower electrode installed on the above-mentioned semiconductor substrate, the charge accumulated in the capacitor structure is proportional to the area, and the insulating film layer Inversely proportional to the thickness of. Since the design rules of LSI decrease year by year, it is necessary to reduce the capacitor area accordingly. However, due to the operation of the circuit, it is required not to reduce the storage capacitance even if the area is reduced. Therefore, it becomes necessary to cover the decrease in the capacitor area by reducing the thickness of the insulating film layer. As a result, the required insulating film thickness becomes less than 100 nm and becomes as small as 2 to 30 nm. In that case, the surface roughness of the conductive thin film layer, which is the lower electrode layer, of 10 nm is considerably larger than the insulating film thickness. That is, even if the target value of the insulating film thickness is formed to be 30 nm, the presence of the roughness of the lower electrode layer causes a portion having a thickness of 20 nm or 40 nm to exist. That is, the insulating film layer thickness is 30%
Means that there will be variations. The leakage current density and withstand voltage of a capacitor change logarithmically with the film thickness. Therefore, in such a film thickness region of the insulating film layer, 10
The film thickness variation of nm has a very large influence on the performance of the device.

The object of the present invention is currently 10 in view of such a point.
It is to reduce the roughness of the surface of the conductive thin film layer having a thickness of about nm to half or less. Therefore, in addition to the main metal thin film that constitutes the conductive thin film layer, a surfactant material is supplied and added to reduce the surface energy of the thin film layer, and annealing is performed to reconstruct and flatten the surface.

[0012]

FIG. 2 is a phase diagram relating to a binary system of Al and Ga. The abscissa represents the concentration of Al with respect to Ga, the ordinate represents the temperature, and the upper convex curve 201 indicates that both exist in a mixed liquid, and the lower 202 indicates that the liquid and Al solid are mixed. Represents coexistence. Also Ga
In the region where the temperature is lower than the melting point of, all Al and Ga exist in the solid state.

According to this, it can be seen that the melting point of Al, which is usually 660 ° C., decreases as Ga is mixed, and in the region where Ga becomes 60%, it decreases to around 480 ° C.

Now, consider forming an Al thin film as a main constituent element of the conductive thin film layer on the semiconductor substrate. Using sputtering, EB heating evaporation or CVD method
Al is deposited in an appropriate film thickness on the semiconductor substrate. Then, Ga is deposited on this Al metal thin film layer. The deposition method may be any of sputtering, EB heating evaporation, and CVD. The semiconductor substrate having the laminated structure of Ga / Al is annealed in nitrogen or a mixed gas atmosphere of argon and nitrogen. The surface of the stacked Ga melts and liquefies from the initial stage of annealing because the melting point of Ga is very low at around 30 ° C. At the interface between liquefied Ga and solid Al, it is considered that a GaAl alloy with a very high Ga concentration is pseudo-formed.
Since the melting point of the GaAl alloy is close to that of Ga, it begins to melt very slowly from the interface with Ga, though it is considerably lower than the melting temperature of Al. In this way, the Al thin film layer whose surface is covered with Ga is dissolved from the Ga surface and gradually liquefied. However, by incorporating Al into liquid Ga, the concentration of Al relative to Ga increases and the melting point rises with respect to Ga, and the composition has the same melting point as the annealing temperature well below 660 ° C. By the way, liquefaction stops. At this time, the solid part of the Al thin film, which is the main conductive layer, and the mixed liquid part that is liquefied by mixing with Ga are alloys of almost the same composition, so both are completely wet and their surface Becomes flat. Since the flatness at this time is the flatness as a liquid, it is on the atomic order. The sample, heated to a temperature and annealed, then begins to cool slowly. Then, the liquefied portion gradually begins to solidify from the interface with the Al solid portion. At this time, the rate of temperature decrease should be slow enough. As a result, the thin film, which had a roughness of about 10 nm because it was polycrystalline at the time of deposition, becomes a polycrystalline with even smaller crystal grains when re-solidified. Therefore, the roughness is significantly smaller than 10 nm and is several nm to 5 nm or less.

The present invention derived from the above consideration will be described below.

According to the method for forming a semiconductor device of the present invention, in the step of forming a conductive thin film layer on a semiconductor substrate, first, a main metal layer is deposited, and then an element which becomes a surfactant is added to the metal. It is a method of forming a semiconductor device, characterized in that the surface of the electrode layer is flattened by annealing after supplying and attaching.

In the method of forming a semiconductor device of the present invention, in the step of forming a conductive thin film layer on a semiconductor substrate,
The method for forming a semiconductor device is characterized in that the temperature drop rate at the end of annealing is slower than 3 ° C./min.

Further, in the method for forming a semiconductor device of the present invention, in the step of forming the conductive thin film layer on the semiconductor substrate, an insulating film layer is provided between the semiconductor substrate and the electrode layer. A method for forming a characteristic semiconductor device.

In the method of forming a semiconductor device, in the step of forming a conductive thin film layer on a semiconductor substrate, a second insulating film layer is provided on the electrode layer.

In the method of forming a semiconductor device of the present invention, in the step of forming the conductive thin film layer on the semiconductor substrate, the element serving as the surfactant is one of the constituent elements of the second insulating film layer. A method for forming a semiconductor device is characterized by the following.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of a method for forming a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 3 is a schematic diagram showing the method of flattening a conductive thin film according to the embodiment of the present invention step by step. FIG. 3A is a diagram showing the state of the substrate before the conductive thin film is deposited. In this case, the insulating film 302 is formed on the semiconductor substrate 301. The composition of the insulating film layer 302 is typically SiO ₂ , Si ₃ N ₄ , SiON, or the like.
₂ and ZrO ₂ , Al ₂ O ₃ , Gd ₂ O ₃ etc. are also used for La ₂ O ₃ . In the embodiment of the present invention, the insulating film layer 302 may have any composition.

Next, as shown in FIG. 3B, a metal thin film layer 303, which is the main material of the target conductive thin film layer, is deposited on the insulating film layer 302. As this deposition method, various sputtering methods, CVD methods, various vapor deposition methods, and the like are used.
In the embodiment of the present invention, this deposition method may be any method. The surface of the metal thin film layer deposited by either method has an Rms value (root mean square value) of 10
It has a roughness 304 of around nm or more. The composition of this metal thin film is Al, AlCu, AlSiCu or Pt, Ni, Ti, W, C.
As for u, the most suitable material may be selected depending on its melting point and reactivity with the surfactant element. In the embodiment of the present invention, Al is used as the simplest example, but any other material may be used.

Next, the element 305 serving as the surfactant is supplied and adhered to the laminated Al metal thin film layer 303. At this time, the surfactant is a substance that lowers the surface energy of Al. In addition to its original meaning, a substance having a low melting point with respect to Al and capable of lowering the entire melting point below that of a simple substance of Al by mixing with Al is also included in a broad sense. Stipulate. When considering the mixture of two substances,
Considering that there is a case where the melting points may be higher than each other due to the mixing, the lowering of the melting point after mixing is at least higher than the melting point higher than each other by the mixing, which means that the total energy and thus the surface energy are decreased. It can be considered that it is decreasing, so I think that the expansion of such terms is allowed. Although Ga is used as the surfactant element in the embodiment of the present invention, Mg
In, Sn, Bi, etc., or two or more of them may be mixed and used.

Next, by gradually raising the temperature of the laminated body shown in FIG. 3 (c) to start annealing, 30 ° C. near room temperature is obtained.
At such a low temperature, the Ga thin film part liquefies first. When the temperature is further raised, liquefaction occurs at the Al / Ga interface at 400 ° C to 450 ° C as shown in Fig. 3 (d). The liquefaction at the interface between Al and Ga is pseudo Ga because the two are in contact with each other at the interface between molten Ga and solid Al.
This occurs because an alloy of Al and Al is formed and its melting temperature is significantly lower than the melting point of Al (306). That is, the interface between molten Ga and Al is considered to be an AlGa alloy with 50% Ga, and the melting point determined from the position of 50% composition in FIG. In reality, Al begins to melt at a temperature much lower than the melting point of this composition of 50%. This is because there is Al that melts into Ga at a temperature lower than the melting temperature of the composition of 50% due to energy fluctuations of Al and Ga, and once Al dissolves into Ga, the Ga concentration with a very low Al concentration. This is because a GaAl alloy with a very high temperature is formed, and due to its low melting point, solidification does not occur, but only melting occurs. Therefore, the melting start temperature is 450 ° C or lower. However, its melting rate is very slow.

By further increasing the annealing temperature, the Al surface is melted and the state shown in FIG. 3 (e) is obtained. Here, all of the supplied and deposited Ga is alloying with Al and liquefying. In this state, the temperature rise is stopped and left for a while. The molten GaAl and Al solids are completely wet and in the equilibrium state of liquefaction and singulation. If this is left for a sufficiently long time, 10n generated due to the presence of crystal grains
The roughness of the Al surface, which was around m or more, is remarkably reduced and flattened like a gas-liquid interface. This state is shown in FIG. 3 (f).

Next, the alloy portion which has been flattened but melted is solidified (307). The solidification is performed by slowly lowering the temperature of the sample that has been heated. If the temperature lowering rate is inappropriate, the surface that has been flattened will generate fine crystal grains, which will cause surface roughness close to the original state. It is desirable that the cooling rate be extremely high or extremely low. If the rate of temperature decrease is extremely high, the entire melted portion is solidified in an amorphous state and fine particles are not generated, so there is no risk of roughness occurring. When the rate of temperature decrease is extremely small, crystallization occurs so that the entire melted portion forms a large crystal that is almost a single crystal, and fine crystal grains are not formed, so there is no fear of surface roughness. Since the temperature lowering rate may be set to be extremely high or low in this manner, either one may be selected within a range permitted by the process conditions. Under normal conditions, it is easier to make the temperature lowering rate extremely small, so in the embodiment, the temperature lowering rate is made extremely slow. The actual value of the cooling rate is preferably about 3 ° C./min or less, but it may be 5 ° C./min in some cases or 0.5 ° C./min or less depending on the substance and structure.

FIG. 3 (g) shows a state after the melted portion is solidified by a sufficiently slow cooling rate. Since the smoothness of the interface at the time of melting is maintained and individualized (307), the smoothness of the surface of the conductive thin film layer after individualization is also significantly smoother than when the metal thin film layer is deposited, and the roughness Rms is It is less than 3 nm.

FIG. 3 (h) shows that the second insulating thin film layer 308 and the upper conductive thin film layer 309 are further laminated on the smoothed conductive thin film layer. Since the insulating film layer 308 is formed on the sufficiently smooth lower conductive thin film layer 307, the insulating film layer 308 itself is sufficiently smooth. Therefore, the thickness of the insulating thin film layer is sufficiently constant, and the leakage characteristics and breakdown voltage of the formed capacitor are not deteriorated. The material of the second insulating thin film layer 308 is the same as that of the first insulating thin film layer 3 described above.
It may be the same as 02 or may be different. For example, SiO ₂ and Si ₃ N ₄ , SiON and HfO ₂ , ZrO ₂ , Al ₂ O ₃ and La
₂ O ₃ , Gd ₂ O _3, etc. are considered. Further, the second insulating thin film layer may be an insulating thin film containing as a constituent element the element used as a surfactant for smoothing the conductive thin film layer 307. For example, when Ga is used as a surfactant, Ga ₅ Gd ₃ O ₁₂ (GGG: gallium gadolinium garnet) is used as the second insulating thin film layer. This GG
G is produced by further supplying Gd and oxygen to the surface of the planarized conductive thin film layer. That is, after flattening the conductive thin film layer, it mixes with Al and does not become GaAl, but Ga that remains as Ga only combines Gd and oxygen to become GGG. Also, the excessively supplied Gd and oxygen are
Form d ₂ O ₃ . Both GGG and Gd ₂ O ₃ are good insulating film layers, so the leakage characteristics of the capacitor are not deteriorated,
Moreover, the simple substance of Ga having a low melting point is eliminated, which is advantageous in terms of process.

Next, a similar process will be described with reference to the drawings focusing on the relationship between time and temperature. FIG. 4 is a temperature step diagram for flattening the surface of the conductive thin film layer in the embodiment of the present invention.

First, the area corresponding to FIG. 3C is the area to the left of the time t _A in FIG. The Al metal thin film layer, which is the main structure of the conductive thin film layer, is laminated on the upper part of the semiconductor substrate through the first insulating film layer, and Ga, which is a surfactant, is further supplied and adhered thereon, but its temperature Is room temperature. Then, annealing is started to raise the temperature of the sample. Let this start time be t _A. The rate of temperature increase may be any rate as long as there is no temperature overshoot. The annealing device may be controlled within the range that is the simplest and most reliable, and is usually around 20 ° C / min. Next, when the temperature reaches T ₂ , Al at the interface between Ga and Al begins to melt. This temperature T ₂ is below the melting point of 480 ° C. of a 1: 1 mixture of GaAl. The time at this time is defined as t _B, and on the left side of t _B in FIG.
In the region represented by, Ga and Al are all in the solid state, or
Only Ga is molten. After that, further increase the temperature
When the temperature reaches T ₃ , the temperature rise is stopped and the temperature is kept constant.
The temperature T ₃ at this time is sufficiently lower than the melting point T ₄ of Al = 660 ° C,
It is usually around 450 ℃. By keeping the temperature T ₃ , melting of Al gradually progresses, and at the same time, smoothing of the interface between Ga and Al proceeds. When the smoothing is sufficiently performed, the temperature is gradually lowered. The time at this time is t _C. The cooling rate is extremely slow as described above, and is 3 ° C./min or less, and in some cases, 0.5 ° C./min or less. Molten Ga and Al
The alloy layer begins to Coca than a little delay time t _C 'than the time t _C. It takes a sufficiently slow time, and at time t _D , the temperature becomes T ₂ 'and the crystallization of the molten portion ends. The temperature T ₂ 'is slightly lower than the temperature T ₂ due to supercooling. After this, the melted portion is completely individualized, so the temperature lowering rate may be any faster. The rate of temperature decrease depends on the heat dissipation rate of the device, and is usually -2.
It is about 0 ° C / minute. At time t _E the temperature T ₁ returns to room temperature (RT).

[0032]

According to the process of forming a conductive thin film of the present invention, the flatness of the surface of the conductive thin film can be remarkably improved, and this is used as a base electrode layer to form an insulating film layer which is several times thinner than before. As a result, it is possible to significantly reduce the leakage current of the device, the breakdown breakdown voltage, and the variation. As a result, a very high performance capacitor structure or transistor structure can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a conductive thin film layer in a CMOS LSI device used for showing a conventional example.

FIG. 2 is a phase diagram showing the relationship between the composition of Al and Ga, the temperature, and the phase used to study the principle of the present invention.

FIG. 3 is a diagram schematically showing a process example of a method of flattening a conductive thin film phase surface in the present invention.

FIG. 4 is a diagram showing an example of the relationship between elapsed time and temperature in the method of flattening the surface of a conductive thin film layer according to the present invention.

[Explanation of symbols]

101 Si substrate 102 n-type transistor 103 p-type transistor 104 TiSi contact metal layer 105 W contact plug metal layer 106 Al wiring metal layer 107 W contact plug metal layer 108 Al wiring metal layer 201 Liquid area 202 GaAl mixed liquid + Al solid region 301 Si substrate 302 Insulating film layer 303 Al metal layer 304 Al metal layer surface 305 Ga metal layer 306 Layer in which a little Al is dissolved in molten Ga 307 Layer in which GaAl once melted is individualized 308 Second insulating film layer 309 Upper conductive thin film layer (upper electrode)

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a step of forming a conductive thin film layer on a semiconductor substrate, wherein a main metal layer is first deposited, and then an element which becomes a surfactant for the metal. A method of manufacturing a semiconductor device, characterized in that the surface of an electrode layer is flattened by supplying and adhering the above and then annealing. 2. The temperature drop rate at the end of annealing is 3 ° C. /
The method for manufacturing a semiconductor device according to claim 1, wherein the method is slower than the minute. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a first insulating film layer is provided between the semiconductor substrate and the electrode layer. 4. The method for manufacturing a semiconductor device according to claim 1, wherein a second insulating film layer is provided on the electrode layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the element that becomes a surfactant is one of the constituent elements of the second insulating film layer.