JP2002237493A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of an electrode or wiring of a polyside structure by making preventable the reaction generated between a high-melting- point metal and polycrystal silicon even when oxidizing the surface of the electrode or wiring, and by eliminating the local intrusion of the high-melting- point metal into the polycrystal silicon. SOLUTION: In a manufacturing method of a semiconductor device, there are provided a step for forming on a silicon substrate 601 a polycrystal silicon film 603 of 100 nm in its thickness via a silicon oxide film 602 of 10 nm in its thickness; a step for forming thereafter on the polycrystal silicon film 603 a W silicide film 604 of 200 nm in its thickness which contains in it nitrogen of 0.1-5%; a step for so subjecting subsequently an intermediate product to heat treatment of 800-900 deg.C as to form in the interface between the polycrystal silicon film 603 and the W silicide film 604 a WSixNy layer 605 (reaction preventing layer) of about 5 nm in its thickness wherein nitrogen having high concentration not lower than 1021 cm-3 is segregated; and a step for so processing next the respective films 603-605 as to form a gate electrode pattern of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a polycide-structured electrode or wiring in which a refractory metal silicide is laminated on polycrystalline silicon.

[0002]

2. Description of the Related Art Hitherto, a method has been adopted in which a wiring layer and another wiring layer or a portion for electrically contacting an element are contacted with a layer called a barrier metal interposed therebetween. This aims at preventing a reaction and diffusion between wirings or between an element and a wiring and obtaining a good and highly reliable contact. Also, this barrier metal layer
It is used not only for contact portions but also for forming wirings and electrodes on insulating films.

At present, TiN is used as a barrier metal material.
And TiW are used. These materials are formed by a sputtering method or the like, and the formed film is a polycrystal and is a columnar crystal having a crystal grain boundary perpendicular to the underlayer. Therefore, there is a crystal grain boundary in which diffusion is likely to occur in a direction in which diffusion is to be prevented, and the structure is not suitable for securing barrier properties.

[0004] Further, it is desired to reduce the resistance of the wiring layer in order to improve the performance of the element. For that purpose, the barrier metal layer in the future must realize a lower resistance by further reducing the thickness. The barrier property of the thinned barrier metal layer is worse than that of a thick film. Therefore, it is expected that the barrier properties are insufficient with the currently used barrier metal layer forming method. Further, in order to obtain complete barrier properties, it is necessary to use a single crystal thin film. However, creating a single-crystal thin film without any defects is
Extremely difficult and impossible with current technology.

In addition, although polycrystalline silicon is used for a conventional gate electrode, its electrical resistance is high, so that the parasitic resistance of the device is increased, which causes deterioration of device characteristics. Therefore, an attempt has been made to use metal or silicide as a material having low resistance. However, when a metal film is formed on a gate insulating film, since a film is formed into a polycrystalline material by ordinary sputtering or the like, the crystal function is not a single crystal plane, and the work function differs depending on each crystal plane. .
For this reason, the work relationship difference exerted on the semiconductor under the gate insulating film is not constant, and the threshold voltage is not stable, so that the device cannot be used.

For example, when a W film is used as a gate electrode, the work functions are 5.25 eV, 4.63 eV, and 4.4 for the plane orientations (110), (100), and (111) of W.
7 eV. Therefore, W in contact with the gate insulating film
It is important that the bottom surfaces of the films have the same plane orientation in controlling the threshold value of the transistor.

[0007] Also, recently, on a polycrystalline silicon as a gate structure, an M layer having lower resistance and relatively higher heat resistance is used.
OSI _x, now polycide structure obtained by laminating a refractory metal silicide such as WSi _x is generally used. These refractory metal silicides are well suited for processes using polycrystalline silicon and are very good in that they do not require many changes even if a polycide structure is introduced.

For example, it is well known that the gate withstand voltage and long-term reliability are improved by oxidizing polycrystalline silicon after processing it into the shape of a gate electrode and increasing the thickness of the oxide film at the gate end. Even if polycrystalline silicon is oxidized simultaneously with the high melting point metal silicide in such a process, if the composition is excessive in Si than the stoichiometric composition, no metal oxide is formed on the surface and SiO ₂ is formed. You.

However, for this purpose, it is necessary to keep the composition of the refractory metal silicide in excess of the stoichiometric composition as described above. Oxidation consumes Si, and the composition becomes more excessive in metal components. This composition change becomes larger as the wiring width of polycide becomes narrower. Initial composition is WSi _2.50
And using the WSi _x film 300nm is WSi _2.65, the average composition of the WSi _x film when forming the SiO ₂ of 85nm on the surface was plotted against the line width is 33.

When the wiring width becomes 0.8 μm or less, the composition approaches the stoichiometric normal composition WSi ₂ , and W becomes excessive. The reason is that as the line width becomes smaller, the area ratio of the surface (upper surface and side surface) per unit volume increases, and the ratio of Si consumed in oxidation increases. That is, when the amount of oxidation increases, in the polycide structure, Si is supplied from the lower layer polycrystalline silicon in order to maintain the normal composition, so that the high melting point metal silicide bites into the polycrystalline silicon, and as shown in FIG. As shown, the gate breakdown voltage deteriorates.

[0011]

As described above, in the conventional polycide structure, when the amount of oxidation is larger than the amount of the refractory metal silicide, Si is supplied from the lower polycrystalline silicon, and the gate breakdown voltage is deteriorated. This phenomenon becomes more conspicuous as the line width becomes narrower, because the ratio of Si consumption on the side surface increases. Further, this withstand voltage deterioration does not occur uniformly on the entire surface of the gate electrode, but is caused by local penetration of the high-melting metal silicide. In other words, it is considered that this occurs due to uneven concentration of the refractory metal silicide and rapid diffusion of silicon at the grain boundaries.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for forming a polycide-structured electrode or wiring even when the surface thereof is oxidized. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can prevent a reaction and eliminates local penetration of a high-melting metal silicide, thereby improving reliability.

[0013]

(Structure) In order to solve the above-mentioned problem, the present invention employs the following structure.

That is, according to the present invention, there is provided a method of manufacturing a semiconductor device having a polycide structure, wherein a step of forming a refractory metal silicide layer to which nitrogen is added on a polycrystalline silicon layer; Forming a layer having a higher nitrogen concentration than the refractory metal silicide layer at the interface between the silicide layer and the polycrystalline silicon layer.

According to the present invention, in the polycide structure, a ternary or quaternary metal-Si-nitrogen or metal-Si-nitrogen-oxygen is used as a high melting point metal silicide / polycrystalline silicon reaction prevention layer. By forming a system layer, it is stable even after a thermal process and does not cause deterioration in gate breakdown voltage.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(Embodiment 1) FIG. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment of the present invention and showing a step of forming an embedded wiring.

First, as shown in FIG. 1A, an SiO ₂ film 1 is formed as an insulating film on a semiconductor substrate 11 by a CVD method or the like.
2 is deposited, and a groove 13 is formed on the surface of the SiO ₂ film 12 by RIE or the like. Here, SiO 2 is used as the insulating film.
_{Although 2} was used, polyimide or the like may be used instead. The surface of the groove 13 is desirably smoothed by a method such as CDE or polishing. In this case, the average roughness is desirably 1 nm or less as the smoothness.

Next, as shown in FIG. 1B, a TiSiN film (barrier metal layer) 14 which is a ternary compound of Ti, Si and N is formed as a diffusion barrier film and an adhesion layer by 25 nm.
Form. The formation method is to use a DC magnetron sputtering apparatus, a target of Ti silicide, and to carry out chemical sputtering with a flow rate of argon and N ₂ in a range of 10 and 30 sccm to 30 and 100 sccm, a pressure of 0.3 Pa and a power of about 1 kW. Is formed. The sputtered film is
XRD analysis confirmed that it was amorphous.

The method of forming the TiSiN film 14 and its conditions are not limited to the above, and can be changed as appropriate according to the specifications. For example, there is a sputtering method using a target in which Ti, Si, and N are arranged in a mosaic pattern.

Here, the composition ratio of Ti and Si in the TiSiN film 14 greatly affects the stress of the film. By changing the composition ratio X (Si / Ti) of Ti and Si variously, TiSiN
After forming the film and measuring the compressive stress in each case,
The result shown in FIG. 2 was obtained. From this figure, it can be seen that when the composition ratio X of Si and Ti is set to 1 or more, the compressive stress sharply decreases. If the compressive stress is high, there are problems such that the device characteristics are deteriorated (device characteristics: device speed, electrical reliability, etc.), and the film is peeled off and cannot be laminated.
Therefore, it is desirable that the composition ratio X of Si and Ti is larger than 1.

As for the composition ratio of Ti, Si and N, the higher the ratio of Ti, the lower the resistance tends to be. However, if the composition ratio is reduced, even if the resistance is somewhat high, the wiring resistance is not affected. Therefore, there is no problem even if it is Si-rich as described above. In addition, a thin film of Ti or the like may be formed in advance to improve adhesion.

As described above, since the ternary compound of Ti, Si and N is amorphous, the film stress is low (for example, 1.7 × 10 ⁹ dyn / cm ² ), which adversely affects the device. It is unlikely to affect. Moreover, there is no crystal grain boundary as in the word of amorphous (for example, like glass). For this reason, diffusion of impurities due to grain boundary diffusion, which has been a problem in thin films having a polycrystalline structure such as TiN and TiW as conventionally used, can be prevented, and ideal barrier properties can be obtained.

For reference, characteristics of a thin film formed by changing the composition ratio of TiSiN are shown in Table 1 below.

[0025]

[Table 1]

Next, as shown in FIG. 1C, a Cu film 15 serving as a main wiring layer is deposited by a 400 nm sputtering method. At this time, the Cu film 15 and the TiSiN film 14
May be deposited continuously without exposure to the atmosphere. Subsequently, as shown in FIG. 1D, Cu is reflowed and buried flat by performing annealing at about 200 to 700 ° C. during or after sputtering.
In this case, the atmosphere for annealing may be, for example, an atmosphere excluding an oxidizing gas (eg, oxygen or water) (1 ppm or less) or an atmosphere adding a reducing gas (eg, hydrogen).

Next, as shown in FIG.
Is etched to form a buried wiring layer made of Cu. This etching is performed by RIE, ion milling, polishing, or the like. Thereby, a highly reliable wiring is formed.

As described above, according to the present embodiment, the ternary compound of Ti, Si and N (TiSiN
Since the film 14) is used and is made richer in Si than Ti, the barrier metal layer becomes amorphous up to a high temperature. In the experiments of the present inventors, the ternary compound of Ti, Si, and N was thermally stable, remained amorphous even after annealing at 750 ° C. for 30 minutes, and did not crystallize. For this reason, there is no diffusion through the crystal grain boundary as in the case of using TiN, and the barrier property can be improved. Furthermore, since the metal is made Si-rich, the film stress can be sufficiently reduced, which is effective for improving the device characteristics.

(Embodiment 2) FIG. 3 is a cross-sectional view for explaining a semiconductor device according to a second embodiment of the present invention, showing a wiring forming step.

First, as shown in FIG. 3A, an SiO ₂ film 32 as an insulating film is formed on a semiconductor substrate 31, and a barrier metal layer and an adhesion layer are formed on the SiO ₂ film 32 as Ti, Si and N. TiSiN film (barrier metal layer)
34 is formed to a thickness of 10 to 25 nm by a sputtering method. Further, a Cu film 35 having a thickness of 400 nm is formed as a main wiring layer. Note that also in the present embodiment, the TiSiN film 3
The composition in No. 4 was made Si-rich.

Next, as shown in FIG. 3B, a pattern of a resist 36 is formed on the Cu film 35 by photolithography. Subsequently, as shown in FIG. 3C, using the resist 36 as a mask, the Cu film 35 and the TiSiN film 34 are used.
RIE or ion milling using chlorine-based gas,
Selective etching is performed by a wet etching method using an acid or the like.

Next, as shown in FIG. 3D, the resist 36 is removed by down-flow ashing using an organic solvent or a mixed gas of oxygen and a fluoride, or RIE using an oxygen gas. Thereby, a wiring using TiSiN as a barrier metal layer is formed.

As described above, also in the present embodiment, a wiring using a ternary compound of Ti, Si and N can be formed as the barrier metal layer 34, and the same effect as that of the first embodiment can be obtained. Can be

(Embodiment 3) FIG. 4 is a cross-sectional view for explaining a semiconductor device according to a third embodiment of the present invention and showing a wiring forming step.

First, as shown in FIG. 4A, an SiO ₂ film 42 is formed as an insulating film on a semiconductor substrate 41, and a barrier metal layer and an adhesion layer are formed on the SiO ₂ film 42 as Ti, Si, and N.
Film (barrier metal layer) 4 which is a ternary compound of
4 was formed to a thickness of 10 to 25 nm by a sputtering method, and a Cu film 45 was formed to a thickness of 40 nm as a main wiring material. Up to this point, the operation is the same as in the second embodiment. Subsequently, the Cu film 4
TiSiN which is a ternary compound of Ti, Si and N
A film 47 is formed to a thickness of 10 to 25 nm by a sputtering method, and a carbon film 48 is formed to a thickness of 10 nm. Then, a resist 4 is formed thereon by a photolithography process.
6 are formed.

Next, as shown in FIG. 4B, using the resist 46 as a mask, the carbon film 48 is patterned by RIE using oxygen gas, and then the laminated film thereunder is formed using a chlorine-based gas. It is processed by the conventional RIE method, ion milling method, or wet etching method using an acid.

Next, after the resist 46 is stripped by downflow ashing using a mixed gas of oxygen and a fluoride, as shown in FIG. 4C, Ti, Si and N
Is deposited by a sputtering method of 10 to 30 nm.

Next, as shown in FIG.
The iN film 49 is etched by RIE or ion milling, leaving the TiSiN film 49 on the side surface. Finally,
The carbon film 48 is peeled off by ashing using a mixed solution of hydrogen peroxide and sulfuric acid or oxygen plasma, or by RIE using oxygen gas. Thereby, Ti, Si and N
Using the ternary compound as a barrier metal, a wiring having a structure in which the main wiring layer is completely covered with the barrier metal is formed.

In this embodiment, the same effects as those of the second embodiment can be obtained. In addition, the main wiring is completely covered with the barrier metal layers 44, 47 and 49. The reliability of the wiring can be further improved.

In the first to third embodiments,
Although Cu was used as the wiring, the present invention is not limited to this.
Other metal materials such as g and Au can be used. Furthermore, when a Cu-Ag alloy is used, the resistance is low (1.
9 to 2.2 μΩcm) and a low melting point (770 ° C.), so that good properties that can be reflowed at a low temperature can be obtained. As a film forming method, a stacked film of Ag / Cu or Cu / Ag, a method of directly depositing a Cu-Ag alloy by a sputtering method, or the like is used. The following Table 2 shows the composition ratio of Ag and Cu, and the hardness, melting point, and resistivity.

[0041]

[Table 2]

The hardness is an important physical property value when selectively leaving only the opening of the groove or the contact by chemical mechanical polishing. According to experiments by the present inventors, it has been found that a melting point of 640 ° C. and a pour point of 720 ° C. are obtained in the case of an alloy containing 5% of Ag, 7% of P, and 88% of Cu. The void alloy can be poured into the groove.

The refractory metal forming the barrier metal layer is not necessarily limited to Ti, but may be Zr, Hf, M
o, W or the like can be appropriately selected and used. Ti
In the case of using any of the above metals other than the above, if the composition ratio of the ternary compound layer is made Si-rich, the film stress is reduced, and the same effect as that of the embodiment can be obtained.

In the embodiment, the wiring on the insulating film has been described as an example. However, the present invention can be applied to a contact portion with another wiring or element. Further, the present invention can be applied not only to wiring but also to formation of an electrode. In addition, various modifications can be made without departing from the scope of the present invention.

(Embodiment 4) Next, a fourth embodiment of the present invention will be described. In this embodiment, before forming the barrier metal layer, the surface on which the barrier metal layer is formed is smoothed. This smoothing can be performed by a method such as CDE or polishing. In this case, the average roughness is desirably 1 nm or less as the smoothness.

For example, the surface of the BPSG film formed by the CVD method has irregularities of about 5 nm on average and about 50 nm at maximum.
The flatness is about 6 nm, up to about 13 nm. By depositing a barrier metal layer of TiN or the like on this smoothed film, the barrier metal layer also has an increased thickness uniformity, does not form an extremely thin portion, does not deteriorate the barrier property, and has a barrier property. Is obtained.

Specifically, as shown in FIG. 5A, a BPS as an insulating film is formed on a semiconductor substrate 51 by a CVD method.
When the G film 52 is formed, minute irregularities are formed on the surface. For example, TiN
When the barrier metal layer 54 made of is deposited by the sputtering method, the thickness of the side surface becomes extremely thin due to the shadowing effect. Then, the barrier property of this part is deteriorated, which leads to the deterioration of the barrier property of the barrier metal layer.

On the other hand, as shown in FIG.
When the barrier metal layer 54 is deposited on the smoothed surface by the sputtering method as shown in FIG. 3B, the thickness of the barrier metal layer 54 becomes uniform, and the barrier property does not deteriorate. In addition, this method can be said to be a particularly effective method for future wiring in which the barrier metal layer is further thinned to reduce the wiring resistance.

Next, the wiring forming step after the surface of the insulating film is smoothed will be described in more detail. First, as a barrier metal layer, a composition ratio of Ti to N is 0.95 to 1.05 to 1.05 to 0.95 on the smoothed insulating film.
Is formed. As a method for forming TiN, a DC magnetron sputtering apparatus was used, and Ti: N
Use a target of a compound within the above range. Then, it is formed by sputtering at an argon flow rate of 40 sccm, a pressure of 0.3 Pa, and a power of about 1 kW. By using this method, a film having a stable composition ratio can be formed.

When chemical sputtering is carried out using Ti as a target and a gas containing N, the conditions must be finely adjusted because the composition ratio changes depending on the state of the substrate on which the film is formed. For example, Ti on a Si substrate
Under the conditions of chemical conversion sputtering of TiN with a composition ratio of N to 1: 1, the flow ratio of argon to nitrogen is 1: 1. However, Ti: N has a composition ratio of 1: 1 to TiN on the SiO ₂ film.
It is necessary to adjust the composition ratio of argon and nitrogen to 1.5 to 1 under the conditions for chemical sputtering. Therefore, by changing the film forming conditions according to the state of the substrate, TiN within the above composition range is formed.

By stabilizing the composition ratio in this manner, the crystallinity is improved and the barrier property is improved.

Subsequently, Ti is used as the barrier metal layer.
The surface is forcibly oxidized by performing oxygen plasma treatment on N. An oxygen plasma processing apparatus is used for the oxidation, and the oxidation conditions include, for example, an oxygen flow rate of 500 sccm, a high-frequency output of 800 W, a pressure of 1 Torr, a temperature of room temperature, and a time of 10 minutes. Alternatively, the surface is oxidized by performing ozone treatment. By this processing, the barrier property of TiN is greatly improved.

Here, the reason why the barrier property of TiN is improved by the present embodiment will be described with reference to FIGS. In FIG. 6, reference numeral 61 denotes a semiconductor substrate;
Is a SiO ₂ film as an insulating film, 64 is a TiN film as a barrier metal layer, 65 is a Cu film as a main wiring layer, 67
Is a crystal grain boundary of TiN, and 69 is a metal (Ti) oxide layer (TiO ₂ film) constituting a barrier metal.

As shown in FIG. 6A, the TiN film 64
When the Cu film 65 is continuously deposited, T
iO_TwoThe film 69 is not formed, and Cu is a grain boundary of TiN.
Easily diffuses through. In contrast, the present embodiment
Forcibly and uniformly oxidize the surface at low temperature, as in
As a result, as shown in FIG. _Two
By covering with the film 69 and further filling the crystal grain boundaries
The barrier property of the TiN film 64 can be improved. Furthermore, low
Because it can be formed at a high temperature, this method
The method can be used.

FIG. 7 shows TiO between Cu and TiN.
₂ is formed in various thicknesses, the amount of Cu diffused in W,
5 shows a contact resistance between wirings between an upper layer (Cu) and a lower layer (W).
From this figure, it can be seen that the diffusion is suppressed by forming a small amount of the TiO ₂ film. Therefore, TiO
_It can be seen that the _two films themselves also have a barrier property, and this effect improves the barrier property.

On the other hand, it can be seen that the contact resistance sharply increases when the TiO ₂ film thickness exceeds about 2 nm, which leads to an increase in wiring resistance and deterioration of device characteristics. This is TiO ₂
This is because the film itself has a high resistance and does not appear when the film thickness is small. Therefore, it can be said that the condition of the optimum film thickness that has low contact resistance and suppresses diffusion is preferably 2 nm or less.

In this embodiment, the surface is smoothed and
The combination of the limitation of the composition ratio of Ti and N and the method of forcibly forming an oxide film at a low temperature was used. However, if the conditions required for each element are satisfied, each step is independently performed. They may be used, or two or more may be used in combination.

In the present embodiment, Cu is used for the wiring, but the present invention is not limited to this, and other metal materials such as Al, Ag, and Au, and a Cu-Ag alloy can be used. Further, the high melting point metal constituting the barrier metal layer is not necessarily limited to Ti, and Zr, Hf, Mo, W, or the like can be appropriately selected and used. Further, in the embodiment, the wiring on the insulating film has been described as an example, but the present invention can be applied to a contact portion with another wiring or element.
Further, the present invention can be applied not only to wiring but also to formation of an electrode. In addition, various modifications can be made without departing from the scope of the present invention.

(Embodiment 5) Next, a fifth embodiment of the present invention will be described. This embodiment relates to the formation of an embedded wiring, and is basically the same as the first embodiment.

First, as shown in FIG. 1A, an SiO ₂ film 12 is formed on a semiconductor substrate 11 by a CVD method or the like. Here, a SiO ₂ film was used as the insulating film,
In addition, for example, polyimide, fluorine-added SiO ₂
Can be used. Subsequently, a groove 13 is formed in the SiO ₂ film 12 by RIE or the like. Then, FIG.
As shown in (b), T is used as a diffusion barrier film and an adhesion layer.
A ternary compound 14 of i, Si and N is formed to a thickness of 25 nm.

Here, the reason for using Ti will be described. Conventionally, amorphous Ta ₃₆ S has been used as a barrier metal material.
i ₁₄ N ₅₀ is known (E. Kolawa et al "Sputte
red Ta-Si-N Diffusion Barriers in Cu Metallization
s for Si ”, EDL. Vol. 12 No.6 June 1991 pp321-32
3). This alloy uses Ta, and has relatively excellent thermal stability. However, as shown in FIG. 8, the standard free energy of formation of nitride is higher for metals such as Ti and Zr than for Ta at all temperatures. Indicates that the bond is more stable on the minus side. In addition, the standard enthalpy of formation of various silicides (-ΔHf) (kcal / meta
l, atom) are shown in the following (Table 3).

[0062]

[Table 3]

A larger value of the enthalpy indicates that the bond is more stable. Therefore, Ti, Zr, Hf, etc. show that the standard formation enthalpy is larger on the negative side for all silicide compositions than Ta, indicating that the bond is more stable. That is, T is greater than Ta
It can be seen that the use of i, Zr, Hf or the like makes it possible to form a more stable and excellent barrier metal for both nitrogen and semiconductor.

The barrier metal used for the semiconductor device is required to be further thinned in order to reduce the wiring resistance.
Since the stability is more strongly demanded, a barrier metal that can withstand a severe environment is required.

Therefore, the barrier property against Al is changed to Ta-S
As compared with i-N and Ti-Si-N, a film thickness of 30 nm and a Ta-Si-N
With -N, Al and Ta reacted to generate an intermetallic compound, and good barrier properties could not be obtained. On the other hand, Ti-Si-N does not show any reaction with Al, shows stable film properties, and has been found to be a better barrier metal. That is, this experiment proved that Ti is a more stable barrier metal than Ta. Therefore, here, Ti is used as the high melting point metal.

The formation method is such that a DC magnetron sputtering apparatus is used, a Ti silicide target is used, and the flow rates of argon and N are set to 0 and 40 SCCM to 39 and 1 SCCM, respectively.
In this range, it is formed by chemical sputtering at a pressure of 0.3 Pa and a power of about 1 kW. XRD analysis confirmed that the sputtered film was amorphous.
It was also confirmed that the film was amorphous and stable even when heated at 750 ° C. Further, the composition ratio after annealing was stable, and as shown in the following (Table 4), a large amount of nitrogen was not released and the composition ratio was not largely shifted.

[0067]

[Table 4]

The formation of the barrier layer is not limited to the above-mentioned method, but may be other conditions and methods. For example, in the case of the sputtering method, a target in which Ti, Si, and N are arranged in a mosaic pattern is used. There are a sputtering method and a sputtering method using a collimator.
In the case of the CVD method, TiCl ₄ , NH ₃ and SiH
₄ gas, or an organic gas source instead of TiCl ₄ , such as TMAT (Tetrakis-demethyl-
Amino Titanium) and SiH ₄ or SiCl ₄ or SiH
by a CVD method using a mixed gas atmosphere of _x Cl _y (may be used plasma or excited species), 35 as film forming conditions
0 ° C., 0.5 Torr and the like. When burying trenches, holes and the like having a high aspect ratio, the CVD method is generally effective because it is conformally deposited.

The resistance also changes depending on the composition ratio of Ti, Si and N. As shown in FIG. 9A, the resistance tends to decrease as the ratio of the N ₂ partial pressure during sputtering decreases. Furthermore, as shown in FIGS. 9B and 9C, the higher the power, the lower the resistance tends to be. That is, the resistance tends to decrease as the composition ratio of N decreases. In addition, although the crystallinity is all amorphous after sputtering, if the N ₂ concentration is very low, it tends to crystallize by annealing (about 600 ° C.) and the barrier property tends to be low.

However, if the film is made thinner, even if the resistance is high to some extent, the wiring resistance is not affected, so that the composition ratio is not limited as long as the barrier property can be maintained. However, in order to reduce the contact resistance in the LSI wiring, it is desirable to have as low a resistance as possible.

Here, the composition ratio of Ti and Si, X (Si / T
A TiSiN film was formed by changing i) variously, and the compressive stress in each case was measured. The result shown in FIG. 10 was obtained. This figure is substantially the same as FIG. 2, but more accurately measured by increasing the number of measurement points. From these results, it is desirable that the composition ratio of Si to Ti is 0.7 or more in order to reduce the stress and the load on the device characteristics. Further, it is understood that the above composition ratio is more preferably 1 or more. However, the composition is not limited at all, as long as the method does not cause a problem of stress.

In this case, a thin film of Ti or the like may be formed in advance to further improve the adhesion. Adhesion is higher than TiN and TiN / Ti
TiSiN is very good. For example, a film in which TiN and TiSiN are deposited on a SiO ₂ or Si ₃ N ₄ film is used as a CM.
When etching is performed by the P (chemical mechanical polishing) method, when the etching conditions are a load of 400 g / cm ² and silica is used as abrasive particles, TiSiN does not cause film peeling, but TiN does. Therefore, TiSiN
It can be seen that is easier to process and more stable.

As described above, since the ternary compound of Ti, Si and N is amorphous, the film stress is lower than that of a crystalline film (for example, 1.7 × 10 ⁹ dyn /). cm ² ),
Low possibility of adversely affecting the device. Moreover, there is no crystal grain boundary as in the word of amorphous (for example, like glass). Therefore, diffusion of impurities due to grain boundary diffusion, which has been a problem in a thin film having a polycrystalline structure such as TiN or TiW as conventionally used, can be prevented, and ideal barrier properties can be obtained.

However, as the amorphous metal, NiNb,
There are alloys that do not contain nitrogen, such as MgZn and CuZr.
Since these amorphous metals are forcibly generated by using an unstable process such as quenching, they lack thermal stability and are easily crystallized and unstable. There is a problem that a compound is formed and wiring resistance is increased. Therefore, among these amorphous metals, a barrier metal made of a compound of a high melting point metal, a semiconductor and nitrogen, which is thermally stable, is not suitable as a barrier metal.

Next, as shown in FIG. 1C, a Cu film 15 serving as a main wiring layer is deposited to a thickness of 400 nm by a sputtering method or the like. At this time, the Cu film 15 and Ti
By continuously depositing the SiN film 14 without exposing it to the air, the adhesion is significantly improved as compared with TiN or the like. This effect appears when Cu is annealed in the next step. When the adhesiveness to Cu is good, repulsion and aggregation due to the surface tension of Cu are reduced, and it is possible to satisfactorily fill the grooves and holes.

Next, as shown in FIG.
By performing annealing at about 00 ° C., Cu is reflowed and buried flat. Next, as shown in FIG. 1E, the portion other than the groove 13 is etched to form a buried wiring layer made of Cu. This etching is R
It is performed by IE, ion milling, CMP, polishing, or the like. Thereby, a highly reliable wiring is formed.

In such a wiring, T with respect to Cu
When the barrier of the compound of i, Si and N was examined, the junction area was measured to find that the contact area was 300 × 8
0 μm ² , 0.2 μm diffusion layer depth, 600 ° C., 30 minutes, the leakage current under the reverse bias did not increase until after annealing in a forming gas, showing good barrier properties.
Further, when the diffusion of Cu into the Si substrate was examined by an atomic absorption method, the Cu concentration was still at the detection limit (2 × 10 ¹²⁾ even after annealing in a forming gas at 600 ° C. for 30 minutes.
/ Cm ³ ) or less, and it is known that good barrier properties are exhibited. Further, the thickness of the compound of Ti, Si and N shows the above-mentioned barrier property even at 5 nm.

Therefore, this film is an excellent film as a barrier metal from the viewpoint of the ability to prevent the diffusion of Cu, the adhesion to the base, and the contact resistance with the upper and lower layers. Moreover,
Since it has a sufficient barrier property even with a thin film and shows a good barrier property even when it is continuously sputtered, it is effective for simplifying the process.

In this embodiment, trench wiring is used. However, the present invention is not limited to the above method, and Ti (or Zr, H
It is sufficient to use a compound of f), a semiconductor and N, and a method of performing patterning after laminating with Cu may be used.
Further, Si was used as the semiconductor, but any semiconductor may be used, and a group IV or compound semiconductor III-V, II-VI
Group, II-IV-VI group, II-IV-V group, III-IV-VI group, I-III-V
Group I and II-V-VII semiconductors may be used. Further, although Cu is used for the wiring, it may be combined with other substances such as Al, Ag, Au, W, or an alloy thereof.

(Embodiment 6) FIG. 11 is a cross-sectional view for explaining a semiconductor device according to a sixth embodiment of the present invention and showing a wiring forming step.

First, as shown in FIG. 11A, a SiO ₂ film or an ONO film (SiO ₂ / Si ₃ N ₄ / SiO ₂ structure) 72 as a gate insulating film having a thickness of 6 nm is formed on a Si substrate 71.
Form. Subsequently, as shown in FIG. 11B, an alloy film 73 of Ti, Si, and N, which is an amorphous metal, is formed.
An amorphous film generally has less surface irregularities and less interface states. Also, unlike the polycrystal, there is no difference in work function depending on the crystal orientation, the threshold voltage is stable, and stable device characteristics can be obtained.

Next, as shown in FIG. 11C, a W film 74 is formed to a thickness of 100 to 150 nm as a gate electrode.
At this time, the alloy film of Ti, Si, and N, which is an amorphous metal, has a good barrier property against W, so that deterioration of the gate insulating film due to W can be prevented. Subsequently, as shown in FIG. 11D, photolithography and RI
Process using the E method. Thereby, a gate electrode is formed.

As a result of operating the MOSFET using the gate electrode thus formed, it was confirmed that the threshold voltage of both the n-channel type and the p-channel type was as low as 0.6 eV, which was suitable for low-voltage operation. Was done. In a structure in which polycrystalline silicon is provided immediately above a gate insulating film, in order to obtain such a low threshold voltage, n
^Since it is necessary to form ⁺⁺ Si for p-channel and p ⁺ poly-Si for the p-channel, the configuration of the present invention can greatly reduce the number of steps.

In this embodiment, an alloy of Ti, Si and N is used as the amorphous metal, but the constituent material is not particularly limited as long as it is amorphous. Further, although W is used as the gate electrode, it may be combined with another substance such as Al, Ag, Au, Cu, W, or an alloy thereof. Further, the amorphous metal itself may be used as the gate electrode.

(Embodiment 7) FIG. 12 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment of the present invention, showing a wiring forming step.

First, as shown in FIG. 12A, an SiO ₂ film 82 is formed on a semiconductor substrate 81. Further, a ternary compound 83 of Ti, Si and N is formed to a thickness of 10 nm as a barrier metal layer and an adhesion layer by a sputtering method.
Subsequently, an Al-Cu alloy film or Al-S
An i-Cu alloy film 84 is formed to a thickness of 400 nm. Further, a ternary compound 85 of Ti, Si, and N is formed thereon to a thickness of 10 nm by sputtering as a film for reducing reflection during photolithography. Since this alloy has a sufficiently low reflectance at all wavelengths used for photolithography than a metal film such as Al or Cu and has a sufficient effect of reducing reflection, it is effective to use this alloy for this purpose.

Next, as shown in FIG. 12B, a photoresist 86 is formed, and the wiring layer is patterned using a photolithography process. Further, the main wiring layer 84
Then, the barrier metal layers 83 and 85 are processed by an RIE method using a chlorine-based gas, an ion milling method, a wet etching method using an acid, or the like. Unlike TiN, the ternary compound of Ti, Si, and N has resistance to SH (a mixed solution of sulfuric acid and hydrogen peroxide), so that resist can be stripped off at the time of lithography, etc. It is. Further, since it has the property of being etched with dilute hydrofluoric acid, dilute hydrofluoric acid is effective as a wet etching solution.

Next, as shown in FIG. 12D, the resist 86 is formed by downflow ashing using an organic solvent, a mixed gas of oxygen and a fluoride, or R resist using an oxygen gas.
Peeling is performed by an IE method, a plasma ashing method of exposing to oxygen plasma, or the like. Thus, a wiring using a ternary compound of Ti, Si and N as a barrier metal is formed.

(Embodiment 8) FIG. 13 illustrates a semiconductor device according to an eighth embodiment of the present invention, and shows a wiring forming step.

As shown in FIG. 13A, an element isolation insulating film 92 and a diffusion layer 93 of a second conductivity type impurity are formed on a semiconductor substrate 91 containing a first conductivity type impurity, and W or W is formed thereon.
A conductor film 94 having silicide as an upper layer is formed. Further, an interlayer insulating film 95 is formed so as to cover the substrate, and contact openings 96 and 97 are formed in the insulating film 95. Then, the alloy film according to the present invention is applied to such a structure.

As shown in FIG. 13B, Ti-Si-
An alloy film 98 made of N, Zr-Si-N, or Hf-Si-N is formed with a thickness of 5 to 100 nm. The thickness to be formed is changed according to the aspect ratio of the contact hole (the ratio of the depth to the contact opening size). Then, the alloy film 98
0 (continuous vacuum transfer without breaking vacuum)
An Al film 99 having a thickness of 4 to 0.8 μm is deposited by sputtering.

Next, a heat treatment is performed. Heating temperature is 50
0 ° C to 600 ° C, heating time is 30 seconds to 5 minutes, Al
By performing the treatment in a high vacuum so that the film surface is not oxidized, the Al film 9 having a flat surface as shown in FIG.
9 is formed. Thereafter, by processing the Al film 99 into a desired wiring pattern, a contact and a wiring are simultaneously formed.

Usually, TiN / Ti or Ti / TiN / Ti is used as a barrier metal used for heating Al.
Is used. The reason is that TiN and S
It is necessary to form a silicide at the interface with a Ti layer interposed due to the high contact resistance of i. Also, TiN oxidizes the surface and closes the grain boundaries, so that the wettability of Al deteriorates. This is because a Ti layer is required at the interface of TiN. When the structure according to the present invention is used, the barrier metal may be a single layer, which can greatly reduce the number of steps and reduce the cost.

The above method is an example of a method of forming a wiring using a barrier metal, and forming a wiring having the above-described structure by using another method may be used. Further, although a compound of Ti, Si and N is used as the barrier metal, the present invention is not limited to the above method, and a compound of a high melting point metal (Zr, Hf, W, Mo, etc.), a semiconductor and N may be used as the barrier metal. Further, although Si was used as the semiconductor, any semiconductor may be used, and it is a group IV or compound semiconductor.
III-V, II-VI, II-IV-VI, II-IV-V, III-IV-V
Group I, I-III-VI, and II-V-VII semiconductors may be used. Although Al-Si-Cu is used as the wiring, a combination with other substances such as Cu, Al, Ag, Au, W, or an alloy thereof may be used.

In these embodiments, the wirings and electrodes have been described as examples. However, the present invention can be applied to contact portions with other wirings and elements. In addition, various modifications can be made without departing from the scope of the present invention.

(Embodiment 9) FIG. 14 is a sectional view showing a schematic structure of a semiconductor device according to a ninth embodiment of the present invention. 15 to 18 are cross-sectional views showing the steps of manufacturing the semiconductor device.

First, as shown in FIG. 15A, ions of B (boron) are implanted into a silicon substrate 201, followed by thermal diffusion to form a p-type region 202 having a depth of about 1 μm. Subsequently, as shown in FIG. 15B, an oxide film 203 having a thickness of about 600 nm is formed in a predetermined region to form an element isolation region. Thereafter, as shown in FIG. 15C, an oxide film 204 having a thickness of about 10 nm is formed, and ion implantation 205 for adjusting the threshold value of the transistor is performed.
Then, after removing the oxide film 204, FIG.
As shown in (d), the gate oxide film 2 having a thickness of about 10 nm is again formed.
Next, polycrystalline silicon 207 of about 200 nm is formed. And 850 in POCl ₃
By performing heat treatment at about 60 ° C. for about 60 minutes, P (phosphorus) is introduced into the polycrystalline silicon. The element introduced in this case is n depending on the desired threshold value of the transistor.
Type or p-type impurities can be introduced. At this time, as a method for introducing the impurity element, diffusion from a gas phase or a solid phase may be used, or ion implantation may be used, but the impurity concentration is set to be about 2 × 10 ²⁰ cm ⁻³ or more. I do.

[0098] Then, for example, after removing the oxide film such as a natural oxide film formed on the polycrystalline silicon during the process by performing processing such as dilute hydrofluoric acid, using a target of WSi _x Ar and N ₂ Chemical sputter in an atmosphere containing
As shown in FIG. 16 (e), a thickness of about 5 nm WSi _x
An _Ny film 208 is formed. WSi _x N _y is WF ₆ + Si
It may be formed by a CVD method using a gas system such as H ₄ + NH ₃ . Subsequently, sputtering with an Ar atmosphere using a target of WSi _x, a thickness of about 200- 300nm WS
to form a i _x film 209.

[0099] Then, as shown in FIG. 16 (f), the resist pattern 210 is formed in the shape of a desired gate electrode or a gate wiring by photolithography, WSi _x and the resist pattern 210 as a mask, WSi
_x N _y and polysilicon RIE techniques (reactive ion e
patterning by using (tching).

Next, as shown in FIG. 17G, the resist pattern 210 is removed by using an asher to form a gate electrode or a wiring. Subsequently, 80 in an O ₂ atmosphere
Oxidation is performed at 0 ° C. for about 30 minutes to form an oxide film 21 on the side and top surfaces of the substrate and the gate electrode as shown in FIG.
Form one. Here, the reason for forming the oxide film is as follows. When ions are directly implanted into the substrate, defects are easily formed in the substrate in a subsequent thermal process, but this can be prevented by forming an oxide film in this manner.

Here, as an example, an nMOS manufacturing process is described.
However, when manufacturing CMOS, the resist
A mask is formed and ion implantation is performed separately.
Film also plays a role in preventing contamination from resist at that time
You. By this heat process, WSi _xN_yPart of the membrane 208
Reacts with native oxide film on polycrystalline silicon surface_xN_y
O_zA film 213 is formed._xN_yBali similar to
Has the property.

Then, As Ke 60 KeV, 5 × 10¹⁵c
m^-2Ion implantation is performed to form an n-type diffusion layer 212.
After that, O_TwoOxidation at 900 ° C for about 60 minutes in an atmosphere
Then, an oxide film 214 is formed as shown in FIG.
You. This step is performed by the gate
It has the effect of increasing the thickness of the oxide film on the
You. The amount of oxidation is appropriately determined according to the required gate breakdown voltage.
Should be, WSi_xSi in the stoichiometric composition
X may be slightly less than 2
Without sucking up Si, and W
The amount of stress increase due to excess⁹dy
n / cm^TwoIt is not a small problem. WSi _1.8Than
And when it becomes W rich, WO_ThreeIs formed due to volume expansion
The gate electrode may come off due to tension. Therefore,
WSi of the gate electrode_xConsidering the composition, thickness, line width, etc. of
It is necessary to perform oxidation so that x does not fall below 1.8
You.

Thereafter, FIG.
As shown in (j), after depositing the interlayer insulating layer 215, a contact hole 216 is opened in a predetermined region, and after Al is deposited, the contact hole 216 is processed into a predetermined shape to complete the wiring 217.

FIG. 34B shows the IV characteristics of the gate manufactured in this manner. The gate withstand voltage does not deteriorate as indicated in the prior art.

Although the manufacturing steps of the nMOS have been described in the above embodiment and the following embodiments, the pMOS can be manufactured by replacing the n-type and the p-type of the impurity conductivity type by ion implantation or the like. . In addition, a CMOS can be similarly manufactured by forming a resist mask in a predetermined region and performing ion implantation.

(Embodiment 10) FIGS. 19 to 22 are sectional views showing steps of manufacturing a semiconductor device according to a tenth embodiment of the present invention.

First, as shown in FIGS. 19A to 19C, a p-type region 302 and an oxide film 3 for element isolation are formed on a silicon substrate 301 just like the ninth embodiment.
03, an oxide film 304 is further formed, and ion implantation 305 for adjusting the threshold value of the transistor is performed. Further, similarly to the ninth embodiment, the oxide film 30
After removing 4, polycrystalline silicon 307 is formed via gate oxide film 306 as shown in FIG.
Then, heat treatment or the like is performed to introduce P (phosphorus) into the polycrystalline silicon.

Next, an oxide film such as a natural oxide film formed on the polycrystalline silicon during the process is removed by performing a treatment with, for example, diluted hydrofluoric acid, and then, using a W target, Ar and N ₂ are used. Chemical sputtering is performed in an atmosphere including the WN _x film 3 having a thickness of about 5 nm as shown in FIG.
08 is formed. Subsequently, the sputtering in an Ar atmosphere using a target of WSi _x, thickness 200nm about W
Forming a Si _x film 309.

[0109] Then, by photolithography, as shown in FIG. 20 (f) to form a resist pattern 310 in the shape of a desired gate electrode or the gate wiring, WSi _x, WN _x and using the resist pattern 310 as a mask The polycrystalline silicon is patterned using the RIE method.

Next, as shown in FIG.
The pattern 310 is removed using an asher and the gate is removed.
An electrode or a wiring is formed. Then, O_Two80 in the atmosphere
Oxidation is performed at 0 ° C. for about 30 minutes, and as shown in FIG.
As described above, the oxide film 31 is formed on the side and upper surfaces of the substrate and the gate electrode.
Form one. By this heat process, WN_xOf membrane 308
Some are polycrystalline silicon and natural acids on the surface of polycrystalline silicon
Reacts with the oxide film to form WSi _xN_yOr WSi_xN_yO_zMembrane 3
13 is formed.

Then, 60 KeV of As, 5 × 10 ¹⁵ c
After ion implantation of about m ⁻² to form a diffusion layer 312, oxidation is performed at 900 ° C. for about 60 minutes in an O ₂ atmosphere to form an oxide film 314 as shown in FIG. This step has the effect of increasing the thickness of the oxide film at the gate end and improving the gate breakdown voltage as described in the section of the prior art. The amount of oxidation should be appropriately determined depending on the required gate withstand voltage. However, _if Si in WSix is less than x = 1.8, W is oxidized and WO ₃ is formed, so that the gate electrode is peeled off due to volume expansion. Sometimes. Therefore, the composition of the gate electrode WSi _x, thickness, in consideration of the line width and the like, x
It is necessary to carry out the oxidation so as not to fall below 1.8.

After that, FIG.
As shown in (j), after depositing an interlayer insulating film 315, a contact hole 316 is opened in a predetermined region, Al is deposited, and then processed into a predetermined shape to complete a wiring 317.

(Embodiment 11) FIGS. 23 to 26 are sectional views showing the steps of manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

First, as shown in FIGS. 23A to 23C, a p-type region 402 and an oxide film 4 for element isolation are formed on a silicon substrate 401 in exactly the same manner as in the ninth embodiment.
03, an oxide film 404 is further formed, and ion implantation 405 for adjusting the threshold value of the transistor is performed.

[0115] Then, as shown in FIG. 24 (d), after removing the oxide film 404, again to form a tunnel oxide film 406 of about 10 nm, 1000 ° C. in an NH ₃ atmosphere,
After performing nitriding treatment for about 30 seconds,
Perform re-oxidation treatment for about 2 seconds. This nitridation and reoxidation treatment has an effect of reducing the interface state of the tunnel oxide film and traps in the oxide film. Subsequently, polycrystalline silicon 200 nm
407 is formed, and heat treatment is performed in POCl ₃ at 850 ° C. for about 60 minutes to introduce P (phosphorus) into the polycrystalline silicon.

Next, as shown in FIG. 24E, an oxide film 408 of about 10 nm is formed on the polycrystalline silicon by thermal oxidation, and subsequently, a SiN film 409 of about 10 nm is formed by LPCVD. Then, the SiN surface is
Oxidation is performed at 0 ° C. for about 30 minutes to form an oxide film 410. Subsequently, a polycrystalline silicon film 411 of 200nm as shown in FIG. 24 (f), in a POCl ₃ atmosphere 850
By performing heat treatment at about 60 ° C. for about 60 minutes, P (phosphorus) is introduced into the polycrystalline silicon.

Next, after removing an oxide film such as a natural oxide film formed on the polycrystalline silicon during the process by performing a treatment with, for example, dilute hydrofluoric acid, Ar and N ₂ are removed using a W target. Chemical sputter in an atmosphere containing
As shown in (g), WN _x 412 having a thickness of about 5 nm is formed. Subsequently sputtered in an Ar atmosphere using a target of WSi _x, a thickness of 200 nm WSi _x film 413
To form

[0118] Next, FIG. 25 as shown in (h), a resist pattern 414 is formed in the shape of a desired gate electrode or a gate wiring by photolithography, WSi _x and the resist pattern 414 as a mask, WN _x
And two layers of polycrystalline silicon are patterned using RIE. Subsequently, as shown in FIG. 25I, the resist is removed using an asher to form a floating gate and a control electrode or a wiring 415 of the EEPROM.

Next, O_Two800 ° C in atmosphere for about 30 minutes
26J, the substrate and the substrate are oxidized as shown in FIG.
An oxide film 416 is formed on the side and top surfaces of the gate electrode.
WN previously formed by this heat process_xIs the lower polycrystalline
Silicon and ultra-thin native oxide film formed on its surface
Reacts with polycrystalline silicon and WSi_xWSi at the interface of_xN
_yOr WSi_xN_yO_z417 is formed. This and
Come, WN_xMost of N is desorbed from W and W or WSi_x
become. Subsequently, As ke60, 5 × 10 ¹⁵cm^-2
Ion implantation is performed to a degree.

Next, as shown in FIG. 26 (k), oxidation is performed in an O ₂ atmosphere at 900 ° C. for about 60 minutes to form an oxide film 419.
To form This step has the effect of increasing the thickness of the oxide film at the gate end and improving the gate breakdown voltage as described in the section of the prior art. The amount of oxidation should be appropriately determined depending on the required gate withstand voltage. However, _if Si in WSix is less than x = 1.8, W is oxidized and WO ₃ is formed, so that the gate electrode is peeled off due to volume expansion. Sometimes. Therefore, the composition of the gate electrode WSi _x, thickness, it is necessary to carry out the oxidation so as not to fall below the x = 1.8 in consideration of the line width and the like.

Thereafter, FIG.
As shown in (l), after depositing an interlayer insulating film 420, a contact hole 421 is opened, and a wiring 422 made of Al is formed.
Is completed by forming

(Embodiment 12) FIGS. 27 to 30 are sectional views showing the steps of manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

First, as shown in FIGS. 27A to 27C, a p-type region 502 and an oxide film 5 for element isolation are formed on a silicon substrate 501 in exactly the same manner as in the ninth embodiment.
03, an oxide film 504 is formed, and ion implantation 505 for adjusting the threshold value of the transistor is performed.

Next, as in the ninth embodiment, FIG.
As shown in (d), after the oxide film 504 is peeled off, polycrystalline silicon 507 is formed via the gate oxide film 506, and P (phosphorus) is introduced into the polycrystalline silicon. further,
In as shown in FIG. 28 (e) as in the ninth embodiment, after removing the oxide film such as a natural oxide film, a WSi _x N _y film 508 is formed by chemical sputtering, WSi _x film 509 by further sputtering To form

Next, as shown in FIG.
A 200 nm SiN film 510 is deposited using the D method, and a resist pattern 511 is formed in a desired gate electrode or gate wiring shape using a photolithography technique.
SiN, WSi using resist pattern 511 as a mask
_x, patterned by RIE method to WSi _x N _y and polycrystalline silicon.

Next, as shown in FIG. 29 (g), the resist is removed using an asher to form a gate electrode or a wiring 512. Here, the SiN deposited in FIG. 29F means that ions to be implanted into the source / drain later are prevented from penetrating into the channel region, and that WSi _x
Has the meaning of preventing the upper surface of the substrate from being oxidized.

Next, oxidation is performed at 800 ° C. for about 30 minutes in an O ₂ atmosphere to form an oxide film 513 on the side surfaces of the substrate and the gate electrode as shown in FIG. This step has the effect of increasing the thickness of the oxide film at the gate end and improving the gate breakdown voltage as described in the section of the prior art. The oxidation amount should be determined appropriately depending on the required gate breakdown voltage.
When Si in WSi _x is below x = 1.8 W is oxidized, there may be a gate electrode peels off due to the volume expansion for WO ₃ is formed. Accordingly, the gate electrode WSi _x
In consideration of the composition, thickness, line width, and the like, it is necessary to perform oxidation so that x does not fall below 1.8.

[0128] The heating step WN _x previously formed by reacts with extremely thin natural oxide film formed on the lower layer of polycrystalline silicon and the surface, the interface between the polycrystalline silicon and WSi _x WSi _x N _y or WSi _x N _y O _z is formed. At this time, most of N is desorbed from WN _x and W or WS
will i _x.

Next, 40 KeV of As, 5 × 10 ¹⁴ c
After ion implantation of about m ⁻² is performed and an n-type diffusion layer is formed, 100 nm is formed by a CVD method as shown in FIG.
Deposit nm SiN515.

Next, as shown in FIG.
The SiN is anisotropically etched using E to form a sidewall 516 at the step of the gate. Then, at 800 ° C, 3
After oxidizing for about 0 minutes to form an oxide film, FIG.
As shown in (k), As is ion-implanted,
A high-temperature short-time annealing of about 30 seconds is performed to form a diffusion layer 518.
To form The short channel effect can be suppressed by making the portion in contact with the gate inside the side wall shallow, and the sheet resistance of the diffusion layer can be reduced and the driving force of the transistor can be improved by forming the outside outside the side wall deep.

After that, FIG.
As shown in (l), after depositing an interlayer insulating film 519, a contact hole 520 is opened in a predetermined region, Al is deposited, and then processed into a predetermined shape to complete a wiring 521.

(Embodiment 13) Next, a thirteenth embodiment of the present invention will be described. FIG. 31 is a process sectional view for describing this embodiment.

As shown in FIG. 31 (a), a thickness of 1
Silicon 6 on which a 0 nm silicon oxide film 602 is formed
A polycrystalline silicon film 603 having a thickness of 100 nm and a W silicide film 604 having a thickness of 200 nm containing 0.1% to 5% of nitrogen were stacked on the substrate 01. Then, as a result of heating at 800 to 900 ° C., as shown in FIG. 31B, nitrogen at a high concentration of 10 ²¹ cm ⁻³ or more is present at the interface between the W silicide film 604 and the polycrystalline silicon film 603. segregated WSi _x N _y
A layer (reaction prevention layer) 605 was formed with a thickness of about 5 nm.

Using this method, the gate electrodes described in Embodiments 9 to 12 can also be formed. Further, although the present invention has been described WSi _x as an example, similar effects are Mo,
It can also be obtained in a metal silicide containing at least one of V, Nb, Ta, Co, and Ti as a main component.

(Embodiment 14) FIG. 40 shows the first embodiment of the present invention.
FIG. 14 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to the fourth embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, as shown in FIG. 40A, an SiO ₂ film 12 is deposited as an insulating film on a semiconductor substrate 11 by a CVD method or the like, and a groove 13 is formed on the surface of the SiO ₂ film 12 by an RIE method or the like. Form. Here, Si is used as the insulating film.
Although O ₂ is used, polyimide, fluorine-added SiO _2, or the like may be used instead. The surface of the groove 13 has C
It is desirable to perform smoothing by a method such as DE and polishing. In this case, the average roughness is desirably 1 nm or less as the smoothness.

Next, as shown in FIG. 40B, a TiSiN film (barrier metal layer) 14 ', which is a ternary compound of Ti, Si and N, is formed as a diffusion barrier film and an adhesion layer.
nm. Here, Ti is used as the refractory metal, but other refractory metals (Zr, Hf, V, Nb,
Ta, Cr, Mo, W, etc.) does not cause any problem. The formation method uses a DC magnetron sputtering apparatus,
Using a silicide target (eg, TiSi _0.6 ), the flow rates of argon and N are 32 and 8 sccm, and the pressure is 0.3 P.
a, formed by chemical sputtering at a power of about 1 kW.

The TiSiN film formed by the above method has a structure in which fine crystals are scattered in an amorphous state, as shown in FIGS. That is, when the formed film was examined by TEM (transmission electron microscope) analysis,
As shown in FIG. 36, 2
It was confirmed that the film had a structure in which TiN microcrystals of about nm were present. FIG. 36 (a) is a TEM photograph showing the planar crystal structure of the film, and FIG. 36 (b) is a further enlarged TEM photograph. With such a structure, since the crystal grain boundary does not exist so as to cross the film, the barrier property is kept good. Furthermore, since the presence of the microcrystals of TiN lowers the resistance,
A barrier metal having excellent barrier properties and electrical resistance is formed.

FIG. 37 is a cross-sectional TEM photograph of Cu / TiSi _0.6 / Si. Similar to the TEM photograph of the plane of the film described above, black dots (TiN) look sparse, and TiN microcrystals are scattered in the amorphous Ti-Si-N film. Since this TiN has small grains and low density and is sparse, there is no crystal grain boundary extending from top to bottom in the film thickness direction.

FIGS. 38 and 39 are characteristic diagrams showing XPS spectra of the TiSiN film formed according to the present invention.
The following can be seen from these figures. Since the Ti—Si—N film is oxidized when left in the air, SiO ₂ and TiO
_Although the peak of FIG. ₂ is visible, the bonding state of the internal Ti—Si—N film itself is TiN, Si ₃ N _4, and Ti—Si—N
It can be seen that it is composed of Also, TiS
i ₂ , TiSi ₁ and when the ratio of Si to Ti decreases,
It can be seen from the N peak in FIG. 38C that the ratio of the TiN peak to the Si ₃ N ₄ peak increases. Therefore, it shows that the bonding of TiN increases in Ti-Si-N. As a result, no TiN microcrystals were observed in the Ti—Si—N film using TiSi ₂ and TiSi ₁ as targets. However, when TiSi _0.6 was used as a target, the bonding of TiN increased, so
It can be seen that TiN microcrystals are observed in the -N film.

Here, microcrystals of TiN were confirmed, but similarly when other high-melting-point metals are used, they have a structure in which microcrystals of nitrides of the high-melting-point metals are present. Since these microcrystals do not grow even by high-temperature annealing (750 ° C.), stable microcrystals are formed without a crystal grain boundary crossing the film, and the barrier property is deteriorated. I will not do it.

The method of forming the TiSiN film 14 'and its conditions are not limited to the above, but can be changed as appropriate according to the specifications. For example, in the case of the sputtering method, a method of sputtering using a target in which Ti, Si, and N are arranged in a mosaic pattern, a sputtering method using a Ti collimator, and in the case of the CVD method, TiCl
₄ , NH ₃ and SiH ₄ gas. Further, instead of TiCl ₄ , an organic gas source such as TM
CV using AT (tetradimethylaminotitanium)
The film forming conditions in the method D include 350 ° C. and 0.5 Torr. However, when burying trenches or holes having a high aspect ratio, the CVD method is generally effective because it is conformally deposited.

Here, in order to further improve the adhesion, a thin film of Ti may be previously formed. Further, generally, an amorphous substance has low stress, and the ternary compound of Ti, Si and N is also amorphous, so that the film stress is lower than that of a crystalline film (for example, 1.7 × 10 ⁹ dyn). / Cm ² ), which is unlikely to adversely affect the device.

Next, as shown in FIG. 40 (c), the Cu film 15 to be the main wiring layer is
nm. At this time, the Cu film 15 and the TiSiN film 1
By depositing 4 'continuously without exposing it to the atmosphere, the adhesion is dramatically improved as compared with TiN.

The effect appears when Cu is annealed in the next step. When the adhesiveness to Cu is good, repelling and agglomeration due to the surface tension of Cu are small, and it is possible to satisfactorily fill the grooves and holes.

Next, as shown in FIG. 40D, during sputtering or after sputtering, 200 to 700
By performing annealing at about ° C, Cu is reflowed and buried flat. In this case, the atmosphere for annealing is
For example, an atmosphere in which an oxidizing gas (eg, oxygen or water) is excluded (1 ppm or less) or an atmosphere in which a reducing gas (eg, hydrogen) is added can be used.

Next, as shown in FIG.
3 is etched to form a buried wiring layer made of Cu. This etching is performed by RIE, ion milling, polishing, or the like. Thereby, a highly reliable wiring is formed.

In such a wiring, T with respect to Cu
When the barrier properties of the compound of i, Si, and N were examined, the junction leak was measured to find that the contact area was 300 ×
At 80 μm ² and a diffusion depth of 0.2 μm, the leakage current under the reverse bias did not increase until after annealing in a forming gas at 600 ° C. for 30 minutes, showing good barrier properties. Further, when the diffusion of Cu into the Si substrate was examined by an atomic absorption method, the Cu concentration was still at the detection limit (2 × 1) even after annealing in a forming gas at 600 ° C. for 30 minutes.
0 ¹² / cm ³ ) or less, and it is known that good barrier properties are exhibited. Further, the thickness of the compound of Ti, Si and N shows the above-mentioned barrier property even at 5 nm.

Therefore, this film is a very excellent film as a barrier metal, and has a sufficient barrier property even if it is a thin film.
Further, even if the sputtering is performed continuously, the barrier property is excellent, which is effective for simplifying the process.

In the above embodiment, the trench wiring is used.
Any structure may be used as long as microcrystals having a thickness equal to or less than the film thickness exist inside the amorphous structure as shown in FIG. 7. No problem. Further, although the semiconductor Si is used as a constituent element, other semiconductors may be used, such as a compound semiconductor such as a group IV semiconductor such as Si, Ge, and C.
Group V semiconductor GaAs, InP, InSb, BN, Ga
P and other II-VI semiconductors such as ZnSe, ZnS, CdS, and C
II-IV-V group, I-III which are ternary compound semiconductors such as dTe
A -VI group, II-V-VII group semiconductor or the like may be used. Although Cu is used for the wiring, a combination with other substances such as Al, Ag, Au, W, or an alloy thereof may be used.

(Embodiment 15) FIG. 41 shows the first embodiment of the present invention.
FIG. 35 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to the fifth embodiment; The same parts as those in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, as shown in FIG. 41A, an ONO film (SiO ₂ / S) is formed on a Si substrate 71 as a gate insulating film.
(i ₃ N ₄ / SiO ₂ ) 72 is formed to a thickness of 60 nm.

Next, as shown in FIG. 41 (b), an alloy film 73 'of Ti, Si and N, which is a metal in which TiN microcrystals smaller than the film thickness exist inside the amorphous layer, is formed. An amorphous film generally has less surface irregularities and less interface states. Also, unlike the polycrystal, there is no difference in work function depending on the crystal orientation, the threshold voltage is stabilized, and stable device characteristics can be obtained. Further, the presence of the TiN microcrystals therein lowers the resistance of this film, thereby increasing the speed by lowering the resistance of the gate electrode.

Next, as shown in FIG. 41C, a W film 74 having a thickness of 300 nm is formed as a gate electrode. At this time, since the alloy film of Ti, Si, and N shows a good barrier property against W, it is possible to prevent the gate insulating film from being deteriorated by W.

Next, as shown in FIG. 41D, processing is performed using photolithography and RIE. Thus, a gate electrode is formed.

In the fifteenth embodiment, an alloy of Ti, Si and N is used. However, as shown in FIG. 35, FIG. The constituent substance is not particularly limited. Although W was used as the gate electrode, Al, A
A combination with other substances such as g, Au, Cu, W, or an alloy thereof may be used. Further, the alloy itself may be used as the gate electrode.

(Embodiment 16) Next, a sixteenth embodiment of the present invention will be described with reference to FIG. This embodiment is different from the fourteenth embodiment described above in that W is used instead of Ti as the high melting point metal.

First, as shown in FIG.
In the same manner as in the first embodiment, the CVD method
SiO2 as an insulating film_TwoA film 12 is deposited and this S
iO _TwoGroove 13 is formed on the surface of film 12 by RIE or the like.
You.

Next, as shown in FIG. 40B, a WSiN film (barrier metal layer) 14 ', which is a ternary compound of W, Si and N, is formed as a diffusion barrier film and an adhesion layer by 25 nm.
Form. Here, WSiN is formed by chemical sputtering using a DC magnetron sputtering apparatus, using a W silicide target, generating plasma in an atmosphere in which N ₂ and Ar are mixed, and performing sputtering. As for the composition of the target, as the x / y ratio of W _x Si _y increases, the specific resistance of WSiN after chemical sputtering decreases. Also, x /
When the ratio of y becomes 5/3 or more, WSi after chemical sputtering
Microcrystals such as W, WN, and W ₂ N exist in the N film in a size of several μm.

This is the same when a Ti _x Si _y target is used. When the x / y ratio becomes 5/3 or more, T
Many TiN microcrystals are present within the i-Si-N film in a size of several nm. If the ratio is smaller than this, the presence of TiN microcrystals is not seen from the TEM observation, and the size is at least 0.8 nm or less.

The Ti—Si—N film formed by chemical conversion sputtering using a Ti _x Si _y target is almost Ti _x Si _y N _z , and the ratio of x to y is almost the same. This can be said for films formed from not only Ti but also all silicides. This is shown in Table 5 below.

[0162]

[Table 5]

The pressure during sputtering was 0.3 Pa, the power was 0.5 to 1/5 kW, and the flow ratio of Ar / N ₂ was 0 /
Perform in the range of 40 to 39/1.

[0164] The sputtered films were all non-
Although it was confirmed to be crystalline, W_x
Si_yX / y = 5/3 or more, W, W
N, W _TwoMake sure that microcrystals such as N exist.
It has been certified.

In the present embodiment, the barrier layer is formed by the sputtering method. However, the present invention is not limited to the above-described method, and the point is that the formed film is a compound of W, Si, and N, and W,
Any film may be used as long as microcrystals such as WN, W ₂ N, W ₅ Si ₃ , and WSi ₂ exist.

Thereafter, in the same manner as in the fourteenth embodiment, the Cu film 1 serving as a main wiring layer is formed as shown in FIG.
40 was deposited by sputtering to a thickness of 400 nm, and FIG.
As shown in (d), Cu is reflowed and buried flat by annealing, and as shown in FIG. 40 (e), a portion other than the groove 13 is etched to form a buried wiring layer made of Cu. Thereby, a highly reliable wiring is formed.

In such a wiring, as in the fourteenth embodiment, the barrier property of the compound of W, Si and N with respect to Cu was examined by measuring the junction leak and determining the diffusion of Cu by the atomic absorption method. Good barrier properties were obtained. Further, the thickness of the compound of W, Si and N is 5 n
It was also found that m exhibited the above barrier properties.

Therefore, this film is a very excellent film as a barrier metal, and has a sufficient barrier property even if it is a thin film.
Further, even if the sputtering is performed continuously, the barrier property is excellent, which is effective for simplifying the process.

The present invention is limited to the above embodiments.
It is not done. For example, used in the first embodiment
By repeatedly using the method, as shown in FIG.
May be formed. 701 in the figure is a substrate, 702 is an element
703 is TiSi _TwoLayers, 704, 707, 7
11, 714, 718 are interlayer insulating layers, and 705, 712 are
The polycrystalline silicon films 706, 710, 713 and 717 are
Si_ThreeN_FourLayers 708 and 715 are Ti-Si-N layers, 7
09 and 716 are Cu layers.

Further, by repeatedly using the method used in the first embodiment, a multilayer structure having two or more layers can be formed. Furthermore, as a high melting point metal,
Two or more types of elements such as Ti, Zr, Hf, W, and Mo may be used in combination. As the refractory metal, Ti, Zr, Hf, W, Mo, V, Nb, Ta,
Two or more kinds of elements such as Cr and Co may be used in combination. In addition, various modifications can be made without departing from the scope of the present invention.

[0171]

As described above in detail, according to the present invention, even when the surface of a gate electrode is oxidized in a gate electrode or wiring having a polycide structure, a reaction between a high melting point metal silicide and polycrystalline silicon is prevented. Therefore, the gate withstand voltage can be prevented from deteriorating without causing local high-melting-point metal silicide to bite, and a highly reliable element can be formed.

[Brief description of the drawings]

FIG. 1 is an exemplary sectional view showing a step of forming a buried wiring of a semiconductor device according to a first embodiment;

FIG. 2 is a characteristic diagram showing a change in compressive stress with respect to a composition ratio of Ti / Si.

FIG. 3 is a sectional view showing a wiring forming step of the semiconductor device according to the second embodiment;

FIG. 4 is a sectional view showing a wiring forming step of the semiconductor device according to the third embodiment;

FIG. 5 is a cross-sectional view for explaining the fourth embodiment, showing an example in which a barrier metal is deposited on a surface having large irregularities and a smoothed surface.

FIG. 6 is a view for explaining a fourth embodiment;
Example of forming Cu directly on N and TiO ₂ on TiN
Sectional drawing which shows the example which formed Cu via the.

FIG. 7 shows the relationship between the amount of diffusion of Cu and the contact resistance between the upper and lower wiring layers.
FIG. 4 is a characteristic diagram showing the O ₂ film thickness dependence.

FIG. 8 is a graph showing the temperature dependence of the standard free energy of formation of nitride.

FIG. 9 is a diagram showing a change in resistance with respect to the N ₂ partial pressure.

FIG. 10 is a characteristic diagram showing a change in compressive stress with respect to a composition ratio of Ti / Si.

FIG. 11 is a sectional view showing a wiring forming step of the semiconductor device according to the sixth embodiment;

FIG. 12 is a sectional view showing a wiring forming step of the semiconductor device according to the seventh embodiment;

FIG. 13 is a sectional view showing a wiring forming step of the semiconductor device according to the eighth embodiment.

FIG. 14 is a sectional view showing a schematic structure of a semiconductor device according to a ninth embodiment;

FIG. 15 is a sectional view showing a manufacturing step of the semiconductor device according to the ninth embodiment;

FIG. 16 is a sectional view showing a manufacturing step of the semiconductor device according to the ninth embodiment;

FIG. 17 is a sectional view showing a manufacturing step of the semiconductor device according to the ninth embodiment;

FIG. 18 is a sectional view showing a manufacturing step of the semiconductor device according to the ninth embodiment;

FIG. 19 is a sectional view showing a manufacturing step of the semiconductor device according to the tenth embodiment;

FIG. 20 is a sectional view showing the manufacturing process of the semiconductor device according to the tenth embodiment;

FIG. 21 is a sectional view showing a manufacturing step of the semiconductor device according to the tenth embodiment;

FIG. 22 is a sectional view showing a manufacturing step of the semiconductor device according to the tenth embodiment;

FIG. 23 is a sectional view showing a manufacturing step of the semiconductor device according to the eleventh embodiment;

FIG. 24 is a sectional view showing a manufacturing step of the semiconductor device according to the eleventh embodiment;

FIG. 25 is a sectional view showing a manufacturing step of the semiconductor device according to the eleventh embodiment;

FIG. 26 is a sectional view showing a manufacturing step of the semiconductor device according to the eleventh embodiment;

FIG. 27 is a sectional view showing a manufacturing step of the semiconductor device according to the twelfth embodiment;

FIG. 28 is a sectional view showing a manufacturing step of the semiconductor device according to the twelfth embodiment;

FIG. 29 is a sectional view showing a manufacturing step of the semiconductor device according to the twelfth embodiment;

FIG. 30 is a sectional view showing a manufacturing step of the semiconductor device according to the twelfth embodiment;

FIG. 31 is a process sectional view for illustrating the semiconductor device according to the thirteenth embodiment;

FIG. 32 is a sectional view showing a modification of the present invention.

Figure 33 is a diagram showing a wiring dependence after oxidation of WSi _x according to the conventional manufacturing method.

FIG. 34 shows the I of the gate electrode according to the conventional method and the method of the present invention.
The figure which shows -V characteristic.

FIG. 35 illustrates a structure including microcrystals inside an amorphous structure.

FIG. 36 is a micrograph showing a planar crystal structure of a TiSiN film.

FIG. 37 is a micrograph showing a crystal structure of a cross section of a TiSiN film.

FIG. 38 is a characteristic diagram showing an XPS spectrum of a TiSiN film.

FIG. 39 is a characteristic diagram showing an XPS spectrum of a TiSiN film.

FIG. 40 is a sectional view showing a manufacturing step of the semiconductor device according to the fourteenth embodiment;

FIG. 41 is a sectional view showing a manufacturing step of the semiconductor device according to the fifteenth embodiment;

[Explanation of symbols]

11,31,41,51,61,71,81,91 ... semiconductor substrate 12,32,42,62,72,82 ... SiO ₂ film (insulating film) 13 ... grooves 14,34,44,47,49, 73, 83, 85, 9
8 TiSiN film (barrier metal layer) 15, 35, 45, 65 Cu film 36, 46 Resist 48 Carbon film 52 BPSG film 54, 64 TiN film (barrier metal layer) 67 Crystal grain boundary 69 TiO ₂ film (metal oxide layer) 74 W film 84 main wiring layer 86 resist 92 element isolation insulating film 93 diffusion layer 94 conductor film 95 insulating films 96 and 97 contact openings 99 Al film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Hisako Ono 1st, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba R & D Center (72) Inventor Yasushi Akasaka Toshiba Komukai, Sai-ku, Kawasaki-shi, Kanagawa No. 1 in the Toshiba R & D Center (72) Inventor Shinichi Nakamura 1 in Komukai Toshiba-cho, Koyuki-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba R & D Center 4M104 BB01 BB36 CC05 DD37 DD42 DD78 DD83 DD86 EE05 EE09 EE17 FF16 HH05 5F033 HH04 HH08 HH09 HH11 HH12 HH13 HH14 HH19 HH25 HH26 HH27 HH28 HH29 HH32 HH33 HH34 HH35 JJ08 JJ09 JJ11 JJ13 MM19 JJ13 JJ13 MM19 QQ08 QQ09 QQ13 QQ14 QQ19 QQ37 QQ46 QQ48 QQ59 QQ65 QQ73 QQ75 QQ76 QQ89 RR04 VV06 XX28

Claims (1)

[Claims] A step of forming a refractory metal silicide layer to which nitrogen is added on a polycrystalline silicon layer; and performing a heat treatment to form an interface between the refractory metal silicide layer and the polycrystalline silicon layer. Forming a layer having a higher nitrogen concentration than the refractory metal silicide layer.