JP2003091498A - Data transferring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a data transferring device capable of reducing the stand-by time of a CPU at the time of performing DMA transfer. SOLUTION: This data transferring device is provided with a 0 length packet holding register 3 for latching the VLD signals of FIFO 1 and 2. In the case of zero length packets, data which are not less than the number of the FIFO 1 and 2 in an end point can be held by using the register 3.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device, and more particularly, to a data transfer device with an improved DMA transfer speed. 2. Description of the Related Art In the prior art, when data is written to an end point via a universal serial bus (USB), a FIFO (Fi
rstIn First Out). But in that case, if the FIFO is full,
Even writing a zero-length packet with no actual data had to wait for the FIFO to go empty. When processing is performed by the CPU, it is still possible to perform other processing during the waiting time by using an interrupt or the like. However, DMA (Direct Mem)
Ory Access) and the DM
When the bus is occupied during A and the CPU stops,
In such a conventional technique, the CPU cannot operate until the writing of the zero-length packet is completed, resulting in a large time loss. [0003] As described above, when data is written to an endpoint using a conventional universal serial bus (USB), a FIFO is used even for a zero-length packet, and DMA transfer is performed. In the case, the time was lost. The present invention solves this problem in a relatively simple manner, and
It is an object to realize a data transfer device capable of reducing the waiting time of U. SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a FIFO type data transfer device for an endpoint for a universal serial bus, wherein the flip-flop latches a VLD signal of the FIFO. The flip-flop means is provided, and in the case of a zero-length packet or the like, data can be stored in an amount equal to or greater than the number of FIFOs contained in the endpoint. Thereby, C at the time of DMA
The waiting time of the PU can be reduced. Hereinafter, a data transfer apparatus according to the present invention will be described in detail with reference to the accompanying drawings. In the present invention, utilizing the fact that there is no data in the zero-length packet and no data is actually written to the FIFO, the FF holding this state is focused on only that the data is valid. By providing
When the writing to the FF is completed, the DMA is terminated and the CPU starts the next processing. If the FIFO is empty during the processing by the CPU, data is automatically written from the data valid holding FF to the FIFO and the processing is performed. FIG. 1 shows the USB data structure.
The data size of the FIFO is a value defined by the USB standard (Full-speed: 8, 16, in BULK,
32, 64) (High-speed: 5 in BULK)
12), and when transferring data exceeding that size, the data is output for each maximum packet size. Then, in the USB, the last data is always terminated with a short packet (a packet smaller than the maximum packet size) in order to notify the transfer destination of the end of the data. As shown in FIG. 1, if the data to be transferred has just reached the maximum packet size, a zero-length packet is transferred in the next transfer cycle. For this reason, in the case of FIG. 1, when data is transferred by DMA or the like, assuming that the number of FIFOs at the end point is two, it is necessary to keep waiting for an empty FIFO to transfer the last zero-length packet. However, there is no point in stopping the CPU for a zero-length packet that has no actual data. Therefore, in the present invention, when a zero-length packet is generated during DMA, the DMA is terminated by setting a data valid bit, and the occurrence of the zero-length packet is maintained. If the data valid bit is set when the FIFO becomes empty, the FULL bit of the FIFO is set, the empty bit is cleared, and the number of data is set to zero. The endpoint clears the FULL bit and sets the empty bit when outputting data from the zero data FIFO. S
The IE (Serial Interface Engine) receives a PID (Packet Identif.)
), CRC (Cyclic Red)
(Under Check) code is output. FIG. 2 shows an actual configuration. In FIG.
Symbol 1 is FIFO-0, symbol 2 is FIFO-2, symbol 3
Is a 0-length packet holding register, 4 is a 2-input AND gate, and 5 to 7 are flip-flops or registers. One input of the two-input AND gate 4 is provided with a Hi-true 0-length packet valid signal.
The other input receives the empty signal of the Hi True FIFO. The 0-length packet holding register 3 is reset by this AND signal, and the FULL signal and the EMPTY signal are sent to the respective FIFOs 1 and 2. Thus, clearing and setting of the FIFO are executed. As described above, the present invention provides a FIFO for an endpoint for a universal serial bus.
In the data transfer apparatus of the system, flip-flop means for latching a VLD signal of a FIFO is provided, and in the case of a zero-length packet or the like, data can be held in a number equal to or greater than the number of FIFOs included in the endpoint in the case of a zero-length packet. enable. Thus, it is possible to realize a FIFO data transfer device for a universal serial bus that can reduce the waiting time of the CPU during DMA.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram of a data structure of a universal serial bus (USB). FIG. 2 is a block diagram of a data transfer device of the present invention. [Explanation of Signs] 1 FIFO-0 2 FIFO-2 3 0 Length packet holding register 4 2-input AND gates 5 to 7 Flip-flop or register

Claims (1)

Claims: 1. A FIFO (FirstIn First) for an endpoint for a universal serial bus.
Out) type data transfer device, comprising flip-flop means for latching a VLD (valid) signal of a FIFO, and using this flip-flop means, in the case of a zero-length packet or the like, the number of FIFOs contained in the endpoint or more A data transfer device characterized in that data can be retained in the data transfer device.