JP2003085126A - Input data processor and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize the hardware constitution by preventing an enlargement and a cost increase of the hardware constitution in an input data processor and a method. SOLUTION: A master processor 10 outputs commands 1 and 10 to a slave processor 30. The slave processor 30 responds to these commands, and samples data to input groups 11 and 12 by processing of a specific period divided into two parts in the timing according to a processing switching signal, and arithmetically executes slave processing on the basis of the data. Arithmetic processing results 1 and 2 and responses 1 and 2 are returned to the master processor 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input data processing apparatus and method, and more particularly, to a plurality of master processors and one master processor.
The present invention relates to an input data processing device and method for sampling and processing input data using a plurality of slave processors.

[0002]

2. Description of the Related Art An example of a multiprocessor type hardware configuration for performing control using a microprocessor is shown in FIG.
Shown in. The conventional input data processing device shown in FIG. 3 includes a master microprocessor and a slave microprocessor.

A master microprocessor (hereinafter, referred to as a master processor) 100 issues a command to a slave microprocessor (hereinafter, referred to as a slave processor) 110, and the slave processor 110 responds to the command and within a fixed period T. In the processing, data sampling is performed on the input group I, and slave processing is executed based on the data. The calculation result / response is returned to the master processor 100.

An example of the timing of this processing is shown in the timing chart of FIG.

[0005]

In the above-mentioned conventional hardware configuration and its processing timing, the input data sampling period of the slave processor is long,
When the arithmetic processing period is relatively short, there are the following problems. The overall hardware configuration becomes unnecessarily large. The cost increases. Even if the slave has an extra processing time within the cycle T, no other processing can be performed in that extra time (see FIG. 4), and the hardware configuration cannot be optimized.

An object of the present invention is to unify the system of slave hardware configurations so that a plurality of master processors have a common slave configuration, and to perform data sampling required for slave processing depending on each master processor to another. An object of the present invention is to provide an input data processing device and method which solve the above problems by performing the slave processing during execution.

[0007]

In order to achieve the above object, the invention of claim 1 responds to a command from a master processor to sample input data at a predetermined cycle to perform slave processing, and obtain a calculation result. In the input data processing device having a slave processor for returning to the master processor, n (n is a natural number of 2 or more) of the master processors and processing switching means for switching processing by each master processor are provided, and the slave processor is An input data processing device is implemented which is characterized in that the slave process is executed in accordance with a switching timing by the switching means in response to a command from each master processor.

According to a second aspect of the present invention, in the input data processing device according to the first aspect, the processing switching means is configured such that a processing period obtained by dividing the predetermined cycle by n for the n master processors is the predetermined cycle. The input data processing device is characterized in that the slave processor performs switching of the processing so as to be repeated and performs arithmetic processing on another master processor during a sampling period in response to one of the n master processors. Carried out.

According to a third aspect of the invention, in response to a command from n (n is a natural number of 2 or more) master processors, the slave processors sample the input data at a predetermined cycle and perform slave processing. In the input data processing method for returning to each master processor, n (n is 2
A first step for switching processing by each master processor and a slave processor for executing the slave processing according to a switching timing in the first step in response to a command from each master processor; An input data processing method characterized by comprising two steps was implemented.

According to a fourth aspect of the present invention, in the input data processing method according to the third aspect, in the second step, n
Switching the processing so that a processing period obtained by dividing the predetermined cycle by n is repeated at the predetermined cycle for each of the master processors;
An input data processing method is carried out, characterized in that arithmetic processing is performed on another master processor during a sampling period in response to one of the n master processors.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Description of Embodiments) FIG. 1 is a block diagram of an embodiment of an input data processing apparatus according to the present invention. In FIG. 1, the master processor 10 issues a command 1 to the slave processor 30, and the slave processor 30 responds to this command, performs data sampling on the input group I1 in a process of a fixed cycle, and based on the data. Executes slave processing. Then, the arithmetic processing result 1 and the response 1 are returned to the master processor 10.

The master processor 20 issues a command 2 to the slave processor 30, and the slave processor 30
Responds to this command, performs data sampling on the input group I2 in a process of a constant cycle, and executes a slave process based on the data. Then, the arithmetic processing result 2 and the response 2 are returned to the master processor 20.

When the slave processor 30 performs the above arithmetic processing, the slave processor 30 performs the arithmetic processing at a timing corresponding to the processing switching signal, and the respective arithmetic processing results and responses in response to the master processors 10 and 20 are responded to the processing switching signal. The master processor 1 is synchronized with the interrupt 1 and the interrupt 2 obtained by inverting the process switching signal by the inverter 40.
Return to 0 and 20.

The timing of the above-mentioned processing is shown in the timing chart of FIG. The slave processor 30 performs processing in accordance with a temporally symmetrical and periodical processing switching signal that is inverted twice within a fixed cycle T. Here, the period in which the process switching signal is at the low level is the master 1 processing period, and the period in which the process switching signal is at the high level is the master 2 processing period.

That is, the slave processor 30 synchronizes with the input group I2 in synchronization with the first falling edge of the processing switching signal.
Data sampling (data sampling 2) and arithmetic processing 1 are executed. Next, slave processor 30
Is data sampling of the input group I1 (data sampling 1) in synchronization with the first rising edge of the processing switching signal.
And the arithmetic processing 2 is executed.

Then, in synchronization with the next falling edge of the processing switching signal, the slave processor 30 executes the data sampling 2 and the arithmetic processing 1. Further, the data sampling 1 and the arithmetic processing 2 are executed in synchronization with the next rising edge of the processing switching signal.

As described above, in this embodiment, the data sampling 1 and 2 for each arithmetic processing 1 and 2 are changed to another master processing period by using the processing switching signal for switching the processing by dividing the fixed period T into two. I am doing this. In order to implement such processing timing, it is necessary to strictly manage the processing period of each slave processing in time series.

(Effects of the Embodiment) According to the present embodiment, the system of the hardware configuration of the slave processors is unified and the two master processors are configured as a common slave configuration, and the slave processing corresponding to each master processor is performed. Since the necessary data sampling is performed during the execution of other slave processes, the one slave processor is time-divided into two processing periods (of course, n (n is 2
Since the above natural number) (may be divided) event-independent processing can be performed, application management of the entire system can be simplified. Further, the larger the number n of masters that commonly use the same slave processor is, the greater the effect can be obtained, the large scale of the hardware configuration and the cost increase can be prevented, and the hardware configuration can be optimized. . Further, by strictly managing the time-series processing period of each slave process, the accuracy of each processing period is improved, and at the same time, the sampling accuracy of the input data is also improved, so that the calculation accuracy is also improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an embodiment of an input data processing device according to the present invention.

FIG. 2 is a timing chart showing the timing of processing by the input data processing device having the configuration shown in FIG.

FIG. 3 is a block configuration diagram of an example of a conventional input data processing device.

4 is a timing chart showing the timing of processing by the apparatus for processing the configuration input data shown in FIG.

[Explanation of symbols] 10 master microprocessor 20 master microprocessor 30 slave microprocessors 40 inverter 100 master microprocessor 110 slave microprocessors

Claims (4)

[Claims] 1. An input data processing device comprising a slave processor which samples input data in a predetermined cycle in response to a command from a master processor, performs slave processing, and returns an operation result to the master processor. n is a natural number of 2 or more), and processing switching means for switching processing by each master processor. The slave processor follows the switching timing by the switching means in response to a command from each master processor. An input data processing device, which executes the slave process. 2. The input data processing device according to claim 1, wherein the processing switching unit repeats a processing period obtained by dividing the predetermined cycle by n with respect to n master processors at the predetermined cycle. The input data processing device, wherein the processing is switched, and the slave processor performs arithmetic processing on another master processor during a sampling period in response to one of the n master processors. 3. In response to a command from n (n is a natural number of 2 or more) master processors, slave processors sample input data at a predetermined cycle and perform slave processing, and the calculation result is sent to each master processor. In a method of processing input data to be returned, a first (n) (n is a natural number of 2 or more) master processor and a process for switching processing by each master processor are switched.
An input data processing method comprising: a step; and a second step in which the slave processor executes the slave processing in accordance with a switching timing in the first step in response to a command from each master processor. 4. The input data processing method according to claim 3, wherein in the second step, a processing period obtained by dividing the predetermined cycle by n is repeated for the n master processors. The input data processing method, wherein the processing is switched, and the slave processor performs arithmetic processing on another master processor during a sampling period in response to one of the n master processors.