JP2003084720A - Voltage generating circuit, display device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of a circuit which generates voltages for signal electrodes and to suppress voltage fluctuation. SOLUTION: The voltage generating circuit is provided with a capacitor 4554 which holds the interline voltage of power feeding lines 4505 and 4506 when switches 4564 and 4568 are each closed between terminals a and c, a capacitor 4574 which back ups the holding voltage by the capacitor 4554 when the switches 4564 and 4568 are each closed between terminals b and c and an operational amplifier 4544 which conducts buffering for the intermediate voltage of power a feeding line 4504 and the power feeding line 4506. The back up voltage by the capacitor 4574 and the buffering voltage by the amplifier 4544 are made into parallel and outputted as (+Vx1) which is one of five voltages to be applied to the signal electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generation circuit for generating a voltage used for a signal electrode for defining display contents of a pixel when a plurality of scan electrodes for driving the pixel are selected at the same time. , A display device and an electronic device including the voltage generation circuit.

[0002]

2. Description of the Related Art As one of display devices, there is a passive matrix type liquid crystal display device which drives pixels without using switching elements such as transistors and diodes. The passive matrix type liquid crystal display device employs a driving method of simultaneously selecting a plurality of scanning electrodes and applying a signal voltage to a signal electrode in the selection in order to improve the image quality of a display image. In the driving method, since the quality of the display image is deteriorated due to the fluctuation of the signal voltage, the liquid crystal display device using the driving method is provided with the voltage generation circuit that suppresses the fluctuation and generates the voltage.

[0003]

However, the conventional voltage generating circuit has a problem that the circuit scale becomes large when the voltage fluctuation is further reduced. In order to solve the above problems, an object of the present invention is to provide a voltage generation circuit, a display device, and an electronic device that can achieve both reduction in fluctuations to generate a signal voltage and miniaturization of the circuit scale. To do.

[0004]

In order to achieve the above object, a display device according to the present invention has a predetermined pixel provided corresponding to the intersection of a scanning electrode and a signal electrode intersecting each other. According to the scanning pattern including the elements of m rows and n columns, the number of the m scanning electrodes is n for one vertical scanning period.
(M and n are integers greater than or equal to 2) times, and in each selection, the voltage corresponding to each of the m elements in the column corresponding to the selection in the scanning pattern is selected m scanning electrodes. A scanning electrode driving circuit applied to each of the scanning electrodes, an element indicating the display content of m pixels corresponding to the intersection of the signal electrode and the selected scanning electrode for one signal electrode, and the scanning pattern A signal electrode drive circuit that detects whether or not the m elements in the column corresponding to the selection match, and applies a voltage corresponding to the number of matches (or the number of mismatches); And a voltage generation circuit that generates a voltage that can be applied to the display device, the voltage generation circuit buffering an intermediate voltage between the voltage of the first power supply line and the voltage of the second power supply line. The buffering voltage An operational amplifier that outputs to a third power supply line for supplying as a voltage corresponding to a value other than the minimum value and the maximum value of the number of coincidences, and a first that holds the voltage between one end and the other end. Holding element and one end of the first holding element are separated from the first power supply line and connected to the third power supply line, and the other end of the first holding element is connected to the third power supply line. A first state of disconnecting from a power supply line and connecting to the second power supply line; and disconnecting one end of the first holding element from the third power supply line and connecting to the first power supply line, A switch for alternately switching between a second state in which the other end of the first holding element is disconnected from the second power supply line, and a switch in the other end of the first holding element in the second state. Voltage is held and the held voltage is used as the buffering voltage. It is characterized in configuration and a second retaining element which outputs the third feed line so as to be parallel for. According to this configuration, the first
In the state, the line voltages of the second and third power supply lines are held by the first holding element, and in the subsequent second state, the holding voltage is backed up by the second holding element, and the backup voltage is Is output to the third power supply line. Since the backup voltage is output to the third power supply line in parallel with the buffering voltage of the operational amplifier, voltage fluctuation is unlikely to occur in the third power supply line. Here, in comparison with the reference configuration in which only the backup voltage by the second holding element (using the first holding element and the switch) is output to the third power supply line, the present invention shows that the switch is configured by the parallelization. Since the resistance of the switch may be high, an empty space can be provided by reducing the area required for the switch. Considering the parallelization with the backup voltage, the capacity of the operational amplifier may be somewhat inferior, so that the element size of the operational amplifier can be relatively small. Therefore, the increase in area due to the addition of the operational amplifier to the reference configuration can be avoided by disposing the operational amplifier in the empty space. Furthermore, in this case, since the first holding element has a small capacity due to the parallelization, the area required for mounting the first holding element can be reduced. Therefore, according to the present invention, it is possible to reduce the circuit area required to generate one of the voltages required for the signal electrodes and prevent the generated voltage from changing, as compared with the reference configuration. .

In the above structure, when the scanning pattern is used, the frequency of the coincidence number taking a value other than the minimum value and the maximum value is higher than the frequency of the coincidence number taking the minimum value or the maximum value. Is preferred. According to this aspect,
Since the voltage corresponding to the frequently-matched number is supplied via the third power supply line, it is possible to suppress the voltage fluctuation due to a high load and prevent the display quality from being deteriorated due to the voltage fluctuation. Become.

Further, the state in which the number of coincidences takes a value other than the minimum value and the maximum value includes a state in which all m pixels corresponding to the intersection with the selected scan electrode are turned on or off. Is preferably included. this is,
Assuming that the character is displayed with the pixels in the on or off state as the background, the state in which all m pixels are on or off is dominant, and the load on the voltage corresponding to the state is considered to be the highest. Because it will be done.

Further, since the electronic apparatus according to the present invention has the above-mentioned display device, it is possible to reduce the circuit scale and prevent the display quality from deteriorating. Examples of such electronic devices include mobile phones and digital still cameras.

Further, the voltage generating circuit according to the present invention is the first
Buffering the intermediate voltage between the voltage of the power supply line and the voltage of the second power supply line, and setting the buffering voltage to the third voltage.
A first holding element that holds a voltage between one end and the other end, and one end of the first holding element are separated from the first power feeding line, And a second state in which the other end of the first holding element is disconnected from the third power feeding line and is connected to the second power feeding line while being connected to the second power feeding line. One end is separated from the third power supply line and connected to the first power supply line, and the other end of the first holding element is connected to the second power supply line.
A switch for alternately switching between a second state in which the power supply line is disconnected from the second power line, and the first state when in the second state.
A second holding element that holds the voltage at the other end of the holding element and outputs the holding voltage to the third power supply line in parallel with the buffering voltage. I am trying. According to this configuration, it is possible to reduce the scale of the circuit required to generate one of the voltages required for the signal electrodes and prevent the generated voltage from fluctuating.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

<Structure> First, the structure of the display device according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of this display device. As shown in the drawing, in the display device 100, 160 strip-shaped scanning electrodes (common electrodes) 312 are arranged along the row (X) direction, while strip-shaped signal electrodes (segment electrodes) 212 are arranged in columns ( 120 pixels are arranged along the (Y) direction, and the pixel 1 is provided corresponding to each intersection of the signal electrode 212 and the scanning electrode 312.
30 is formed. Therefore, the resolution of the display device 100 is 160 vertical × 120 horizontal dots.

The scan voltage generating circuit 460 includes a scan electrode 31.
The voltages + Vy, Vc, and -Vy that 2 can take are respectively generated. The signal voltage generation circuit 450 which is a characteristic part of the present case
Is the voltage that can be taken by the signal electrode 212 + Vx2, + Vx
1, Vc, -Vx1, and -Vx2 are generated, respectively.

The timing signal generation circuit 106 generates various control signals and clock signals necessary for driving.
The scan code generator 108 includes the timing signal generation circuit 1
Scan codes CY1 to CY4, which will be described later, are generated according to the signal generated by 06. Scan electrode drive circuit 3
Reference numeral 50 denotes voltages + Vy, Vc, -V generated by the scan voltage generation circuit 460 according to various signals generated by the timing signal generation circuit 106 and the scan codes CY1 to CY4 generated by the scan code generation unit 108.
Any one of y is selected, and the selected voltage is supplied as scanning signals Y1, Y2, Y3, ..., Y160 to the corresponding scanning electrodes 312. Signal electrode drive circuit 2
Reference numeral 50 denotes a voltage + V generated by the signal voltage generation circuit 450 according to the display content of the pixel corresponding to the intersection with the scan electrode 312 selected by the scan electrode drive circuit 350.
One of x2, + Vx1, Vc, -Vx1, and -Vx2 is selected, and the selected voltage is set to the data signal X1, X.
2, X3, ..., X120 are supplied to the corresponding signal electrodes 212. Details of various signals generated by the timing signal generation circuit 106, CY1 to CY4 generated by the scan code generation unit 108, the scan electrode drive circuit 350, and the signal electrode drive circuit 250 will be described later.

<Signal Voltage Generation Circuit> Next, the signal voltage generation circuit 450 will be described in detail. FIG. 2 shows the signal voltage generation circuit 45.
It is a circuit diagram which shows the structure of 0. As shown in this figure, the signal voltage generation circuit 450 includes the power supply lines 4502 and 45.
From the line voltage (Vcc-Gnd) of 06, three voltages +
Vx2, + Vx1, and -Vx1 are generated, the reference potential Gnd is set to the voltage -Vx2, and the voltage Vcc is set to the voltage Vc.
, These five voltages are applied to the signal electrode drive circuit 2 respectively.
Supply 50.

The signal voltage generating circuit 450 has a switch 452 for generating the voltage + Vx2 among the three voltages.
2, 4524 and capacitors 4512, 4522.
In the switches 4522 and 4524, the clock signal CK1
In order to charge and discharge the capacitor 4512 by interlocking according to the above, the terminal a of the switch 4522 is connected to the power supply line 4502 kept at the potential Gnd which is the reference of the voltage.
The terminal b is connected to the power supply line 4504 to which the voltage Vcc is applied, and the terminal a of the switch 4524 is connected to the power supply line 4504, while the terminal b is at the voltage +
It is connected to a power supply line 4506 which is an output line of Vx2.
The capacitor 4512 charges the voltage Vcc of the power supply line 4504 with the potential Gnd of the power supply line 4502 as a reference, and applies the charging voltage to the power supply line 4506 by adding the charging voltage with the voltage Vcc of the power supply line 4504 as a reference. One end thereof is connected to the terminal c of the switch 4522, and the other end thereof is connected to the terminal c of the switch 4524. In addition, the capacitor 4514 holds the voltage applied to the power supply line 4506 by the capacitor 4512, so that one end thereof has a power supply line 4502.
, And the other end is connected to the power supply line 4508, respectively.

Each of the switches 4522 and 4524 is closed between the terminal a and the terminal c as indicated by the solid line in the figure when the clock signal CK1 is at H level, while the clock signal CK1 is closed. Is at the L level, it is closed between the terminals b and c as shown by the broken line in the figure. Here, the clock signal CK1
3 is a signal obtained by dividing the clock signal YCK for defining one horizontal scanning period (1H) by two, as shown in FIG. When the clock signal CK1 is at the H level, the capacitor 4512 holds the voltage Vcc as a result of being charged by closing the terminals a and c of the switches 4522 and 4524. After the holding, when the clock signal CK1 shifts to the L level, the power supply line 4506 is closed by the closing of the terminals b and c of the switches 4522 and 4524.
The voltage Vcc of 504 is further added with the voltage Vcc held in the capacitor 4512 to obtain a voltage of 2 · Vcc. Even if the clock signal CK1 goes high again, the power supply line 45
06 is held at the voltage 2 · Vcc by the capacitor 4514. Therefore, when the clock signal CK1 repeatedly closes the terminals a and c and the terminals b and c in the switches 4522 and 4524, the power supply line 45
06 continues to hold the voltage 2 · Vcc, and the voltage 2 · Vcc
cc is supplied to the power supply line 4506 as the voltage + Vx2.

Since the signal voltage generation circuit 450 generates the voltage + Vx1 among the above three voltages, the resistance 453 is used.
6, 4538 and an operational amplifier 4544. The resistors 4536 and 4538 have a voltage of 2 · Vcc (= + Vx2)
To obtain an intermediate voltage between the voltage Vcc (= Vc) and the power supply lines 4504 and 4506 having the same resistance value.
Are connected in series between. Resistors 4536, 4538
The resistance value is set to be extremely high from the viewpoint of suppressing the power consumed by. Since the operational amplifier 4544 buffers and outputs the intermediate voltage, its positive input end is connected to the connection point of the resistors 4536 and 4538, while its output end is connected to the power supply line 4505 and its negative input. It has been returned to the end. Therefore, the voltage of the power supply line 4505 becomes an intermediate voltage between the power supply lines 4504 and 4506, that is, the voltage 3 · Vcc / 2, and the voltage 3 · Vcc / 2.
Vcc / 2 is used as the voltage + Vx1. In addition,
The potential Vcc of the power supply line 4504 is used on the low side of the power supply voltage of the operational amplifier 4544, and the voltage 2 · Vcc of the power supply line 4505 is used on the high side.

The signal voltage generation circuit 450 includes an operational amplifier 4
Voltage + V in parallel with buffering voltage by 544
switches 4566, 4568 to generate x1;
The capacitors 4554 and 4574 are also provided. In the switches 4566 and 4568, the capacitance 45
To charge and discharge 54, terminal a of switch 4566
Is connected to the power supply line 4505, its terminal b is connected to the power supply line 4504, and the switch 4568 is connected.
The terminal a is connected to the power supply line 4506, while the terminal b is connected to the power supply line 4505. Capacity 4554
Charges the voltage of the power supply line 4506 with the power supply line 4505 as a reference, while applying the charging voltage to the power supply line 4505 with the power supply line 4504 as a reference, one end thereof is connected to the terminal c of the switch 4566, The other end is connected to the terminal c of the switch 4568. Also, capacity 4
The capacitor 574 holds the voltage applied to the power supply line 4505 by the capacitor 4554, so that one end thereof has a power supply line 4504.
, And the other end is connected to the power supply line 4505, respectively.

Each of the switches 4566 and 4568 is closed between the terminal a and the terminal c as shown by the broken line in the figure when the clock signal CK2 is at H level, while the clock signal CK2 is closed. Is at the L level, it is closed between the terminals b and c as shown by the solid line in the figure. The clock signal CK2 is shown in FIG.
As shown in, the clock signal YCK for defining one horizontal scanning period (1H) is divided by two. When the clock signal CK2 is at H level, the switch 45
By closing the terminals a and c at 66 and 4568,
The capacitor 4554 holds the line voltage of the power supply lines 4505 and 4506, that is, the voltage Vcc / 2. When the clock signal CK2 transitions to the L level, the switch 4566,
At 4568, the terminals b and c are closed, so if the output of the operational amplifier 4544 is ignored, the power supply line 4505
Is the voltage Vcc / 2 held by the capacitor 4554.
Is added to the voltage Vcc of the power supply line 4504 to obtain a voltage of 3.
Vcc / 2 will be output. Clock signal CK
Even if 2 becomes H level again, the power supply line 4505 continues to hold the voltage 3 · Vcc / 2 due to the capacity 4574.
The operational amplifier 454 is connected to the power supply line 4505 as described above.
Since the buffering voltage of 4 is also output, the buffering voltage and the holding voltage of the capacitor 4574 are output in parallel.

The structure for generating the voltage −Vx1 is the same as the structure for generating the voltage + Vx1.
That is, the output voltage of the operational amplifier 4542 and the holding voltage of the capacitor 4572 are parallelized, and the parallelized voltage is the voltage −Vx1 (= Vcc / 2), which is the power supply line 4.
It is output to 503. Here, the output voltage from the operational amplifier 4542 is a voltage obtained by dividing the power supply lines 4502 and 4504 by the resistors 4532 and 4534 having the same resistance value and buffering the divided voltage. Further, the voltage held by the capacitor 4572 is set to the switch 456.
After holding the line voltage of the feeder lines 4503 and 4504 in the capacitor 4552 by closing the terminals a and c in 2, 4564, the holding voltage of the capacitor 4552 is closed by closing the terminals b and c in the switches 4562 and 4564. Is added to the power supply line 4502 and is backed up by the capacitor 4572. Also, the resistor 453
Similar to the resistors 4536 and 4536, the resistance values of the resistors 2 and 4534 are set to be extremely high.

The clock signal CK2 is the clock signal CK.
Since 1 is logically inverted with respect to each other as shown in FIG. 3, the capacitance 4554 (45) is charged during the period in which the capacitance 4512 charges the line voltage of the power supply lines 4502 and 4504.
52) is a feeder line 4504, 4505 (4502, 45
03) is supplied (pumped) with the holding voltage, and conversely,
During a period in which the capacitor 4512 supplies (pumps) the holding voltage to the power supply lines 4504 and 4506, the capacitor 4554 has a relationship of charging the line voltage of the power supply lines 4505 and 4506.

The voltage reference in the signal voltage generation circuit 450 is the potential Gnd in the power supply line 4502, but the polarity reference of the voltage in the signal electrode drive circuit 250 (including the scan electrode drive circuit 350) is not Gnd but the voltage Vnd.
c (= Vcc). That is, the signal electrode drive circuit 2
Voltage at 50 + Vx2, + Vx1, -Vx1, -V
The polarity of x2 and the polarities of the selection voltages + Vy and −Vy in the scan electrode drive circuit 350 are all defined by whether they are higher or lower than the voltage Vc.

Here, the generation of the voltage in the signal electrode drive circuit 450 has been described in detail, but the scan voltage generation circuit 46.
The generation of the voltages + Vy and −Vy at 0 will be summarized. A switch 452 in the signal voltage generation circuit 450.
2, 4524 and capacitors 4512, 4514 are used in multiple sets to multiply the voltage Vcc and generate one of the voltages + Vy, -Vy, and then this one voltage is inverted with the capacitor and the switch centering on the voltage Vc. Voltage + Vy, -V
The configuration is such that the other side of y is generated.

The voltages + Vx2, + Vx1, Vc, -Vx1, -Vx that can be generated in this way and applied to the signal electrodes.
2 and the reference voltage Gnd used in the signal voltage generation circuit 450 and the scan electrode generation circuit 460 based on the magnitude relation and polarity of the voltages + Vy, Vc, and −Vy generated by the scan voltage generation circuit 460 and applied to the scan electrodes. The comparison between the voltage and the voltage Vcc is as shown in FIG.

<Driving Circuit> The driving of the display device 100 is performed by simultaneously selecting a plurality of scanning electrodes and selecting the scanning electrodes in a plurality of times within one vertical scanning period (one frame). In this driving, the following scanning pattern is used when applying the selection signal to the scanning electrodes. That is, this scan pattern is a kind of matrix that defines the polarity of the selection signal to be applied to each of the simultaneously selected scan electrodes for each selection, and the rows in the scan pattern correspond to the simultaneously selected scan electrodes. , Column is 1
Corresponding to selection in the frame, each element defines the polarity of the selection voltage. For example, when the scanning pattern is represented by M rows and N columns (M and N are integers of 2 or more), the number of scanning electrodes to be simultaneously selected is M, and N selections are performed in one frame, and m rows are selected. Elements of n columns (m is an integer satisfying 2 ≦ m ≦ M and n is an integer satisfying 2 ≦ n ≦ N) are assigned to the m-th row scan electrode of the simultaneously selected scan electrodes and n of one frame. It defines the polarity of the selection voltage to be applied in the second selection.

The condition required for this scanning pattern is to satisfy normality and orthogonality. The "normality" is a property in which, when a scan electrode is selected according to a scan pattern and a select voltage is applied, the effective values of the select voltage applied to the scan electrodes are equal to each other in a unit of one frame. Say Further, “orthogonality” means that when a scan electrode is selected according to a scan pattern and a selection voltage is applied, a voltage amplitude applied to a scan electrode and a voltage applied to another arbitrary scan electrode. Amplitude and the sum of products for one frame are all zero.

In the present embodiment, the number of scanning electrodes selected at the same time is set to "4", so that the scanning pattern shown in FIG. 5B is used as an example. In the illustrated scanning pattern, for example, the element “−1” in the first row and third column is selected as the negative electrode in the first row scanning electrode among the four scanning electrodes simultaneously selected in the third selection. This means that a voltage should be applied. Also, for example, the element "+" in row 4 and column 2
"1" means that a positive selection voltage should be applied to the fourth row scan electrode among the four scan electrodes that are simultaneously selected in the second selection. It is easy to understand that the illustrated scanning pattern satisfies the normality and the orthogonality. There are two methods for selecting the scanning electrodes, that is, a method of performing temporal dispersion in one frame and a method of performing temporal integration in one frame. In this embodiment, the method will be described, and the method will be described in an application example described later.

In order to perform such driving, the timing signal generation circuit 106 generates necessary control signals and clock signals. More specifically, the timing signal generation circuit 106 in the present embodiment, the frame start pulse YD, the field start pulse FP, the frame signal F.
R and a clock signal YCK are generated respectively.

A brief description of these signals is as follows.
First, the frame start pulse YD is shown in FIG.
Alternatively, as shown in FIG. 10, the start of the frame is defined by its falling edge. Secondly, the field start pulse FP indicates the start of the fields f1, f2, f3, f4 obtained by equally dividing one frame (1F) into four, as shown in FIG. 5 (a), FIG. 9 or FIG. , Specified by the fall. Thirdly, the frame signal FR is
(A) As shown in FIG. 9 or FIG. 10, the level is inverted every frame (1F). Fourth, as shown in FIG. 7, the clock signal YCK has one horizontal scanning period (1
H) is a clock signal having a cycle. The clock signals CK1 and CK2 described above are the clock signals YCK.
Since it is necessary to be synchronized with, it is actually generated in the timing signal generation circuit 106.

Next, the scan code generator 108 scans the scan codes CY1 and CY based on the frame start pulse YD, the field start pulse FP and the frame signal FR.
2, CY3 and CY4 are output as shown in FIG. Here, scan codes CY1, CY2, CY
3 and CY4 are column elements in the scan pattern and correspond in time series to each of the fields f1, f2, f3 and f4. Specifically, the scan code CY1 during the period when the frame signal FR is at the L level corresponds to each of the elements in the 1st row, 1st column, 1st row 2, 2nd column, 1st row 3rd column, 1st row 4th column of the scanning pattern. , Fields f1, f2,
It is output at f3 and f4. Similarly, the frame signal FR
Scan codes CY2, CY3, and C during the period when is at the L level
Y4 is 2nd row to 1st row to 2nd row and 4th column of the scanning pattern,
Fields f1, f2, f3, and f correspond to the elements in the 3rd row, 1st column to 3rd row, 4th column, and the 4th row, 1st column, 4th row, 4th column, respectively.
It is output at 4. The scan codes CY1, CY2, C generated while the frame signal FR is at H level
In Y3 and CY4, as shown in the figure, the polarity of the code in the period when the frame signal FR is at L level is inverted.

<Scan Electrode Driving Circuit> Next, the details of the scan electrode driving circuit 350 will be described. FIG. 6 is a block diagram showing the configuration of the scan electrode driving circuit 350. In this figure, the shift register 3520 is a 40-bit shift register, and the field start pulse FP described above is used.
Are shifted every horizontal scanning period, and the transfer signals Ys1 to
It is sequentially output as Ys40 (see FIG. 7). Here, the transfer signal Ys1 is counted from the top in FIG.
Selection / non-selection (specifically, selection at H level, non-selection at L level) is instructed for the scanning electrodes 312 on the fourth row. Similarly, the transfer signal Ys2
Indicates the selection / non-selection of the scanning electrodes 312 on the fifth row to the eighth row. Generally, the ordinal number p of the horizontal scanning period in one frame (p is an integer satisfying 1 to 40)
, The transfer signal Ysp is counted from the top,
(P-1) +1} line, {4 (p-1) +2} line,
The {4 (p-1) + 3th line and the {4 (p-1) + th line
The selection / non-selection of the scanning electrode 312 on the 4th row is shown.

Next, in the decoder group 3540, the transfer signals Ys1 to Ys40 from the shift register 3520 and the scan code CY from the scan code generator 108 (see FIG. 1).
From 1, CY2, CY3 and CY4, the voltage + Vy,
Select signals a, b, and c indicating which of Vc and -Vy should be selected are output corresponding to each of 160 scan electrodes 312. Therefore, the decoder group 4404 includes the following decoders in one-to-one correspondence with the scan electrodes 312. That is, in general, the decoder corresponding to the scan electrode 312 on the {4 (p−1) + i} th row receives the transfer signal Y.
An AND circuit 3542 that outputs a logical product signal of sp and the scan code CYi as a selection signal a, and an inverter circuit 3 that outputs an inverted signal of the transfer signal Ysp as a selection signal b.
544 and an AND circuit 3546 for outputting a logical product signal of the transfer signal Ysp and the inversion signal of the scan code CYi as the selection signal c. Where i is 1,
An integer of either 2, 3 or 4 and the selected 4
It is used to distinguish the scan electrodes 312 of the book or to generally describe the scan code CY1, CY2, CY3 or CY4.

The selection signals a, b, and c corresponding to the scan electrode 312 in the {4 (p-1) + i} th row are in the following level states. That is, the transfer signal Ys
When p is at H level and the scan code CYi is at H level, only the selection signal a is at H level,
When the scan code CYi is L level, only the selection signal c becomes H level, while when the transfer signal Ysp is L level, only the selection signal b becomes H level regardless of the scan code CYi. In this way, the selection signals a, b, and c corresponding to one scan electrode 312 are exclusively at the H level.

Subsequently, the level shifter group 3560 expands the voltage amplitudes of the selection signals a, b and c, respectively, and outputs them as selection signals a ', b', c '. Next, selector group 3
580 is a voltage + in response to the selection signals a ′, b ′, and c ′.
Any one of Vy, Vc, and −Vy is actually selected and applied to the scan electrode 312. Therefore, the selector group 3580
Then, for one scan electrode 312, a switch that selects the voltage + Vy when the selection signal a ′ is at the H level, a switch that selects the voltage Vc when the selection signal b ′ is at the H level, and a selection signal. If c'is H level, voltage -V
A switch for selecting y is provided. Note that the selection signals a, b, and c corresponding to one scan electrode 312 are exclusively at the H level, so that a plurality of voltages are not simultaneously selected by one scan electrode 312.

<Signal Electrode Driving Circuit> As described above, this embodiment adopts a driving method in which a plurality of scanning electrodes are simultaneously selected and the scanning electrodes are selected in a plurality of times in one frame. In this driving method, j
The voltage to be applied to the signal electrode 212 in the (where j is an integer satisfying 1 ≦ j ≦ 120) column is omitted because a mathematical proof is required for details, but is outlined as follows. . That is, the voltage to be applied to the signal electrode 212 of the jth column is located at the intersection of the element of the column corresponding to the selection of the scanning pattern and the scanning electrode 312 selected at the same time as the signal electrode 212 of the jth column. This is a value obtained by multiplying the corresponding elements of the corresponding pixel by the corresponding elements, obtaining the sum of them (sum of products), and multiplying the sum by an appropriate coefficient. The element of the scanning pattern used in this embodiment is “+1” or “−1”, and the element of the pixel located at the intersection with the scanning electrode 312 selected at the same time as the signal electrode 212 of the j-th column is When the pixel is to be turned on, "+1" is set, and when the pixel is to be turned on, "-1" is set, and the product sum values of the four elements are "4", "2", "0", "-2",
It is one of five values of "-4". Therefore, the voltage corresponding to each of the product sum values “4”, “2”, “0”, “−2”, and “−4” is + Vx2 (= + 2 · Vx).
1), + Vx1, Vc (= 0), -Vx1, -Vx2
(= −2 · Vx1).

In this embodiment, the product sum value is not obtained in order to reduce the calculation load. That is, in the present embodiment, in the scan pattern,
The four elements in the column corresponding to the selection are scan codes CY1 and CY.
The four elements of the pixels, which correspond to 2, CY3, and CY4, and are located at the intersections with the scanning electrodes 312, which are selected at the same time as the j-th column signal electrode 212, have lines Aj and B as described later.
First, since it is represented by the logic levels of j, Cj, and Dj,
The logic levels of the scan codes CY1, CY2, CY3, and CY4 are compared with the logic levels of the lines Aj, Bj, Cj, and Dj, respectively, and secondly, according to the number of matching levels (or the number of mismatching levels) in the comparison. Determine the voltage to be applied to the signal electrode. Specifically, the sum of products value described above is “4”,
"2", "0", "-2", "-4" means that the number of matching levels is "4", "3",
Since it is equal to “2”, “1”, and “0”, the number of matching levels is “4”, respectively in the present embodiment.
If "3", "2", "1", "0" (the number of mismatches is "0", "1", "2", "3", "4"),
Voltage + Vx2, + Vx1, Vc, -Vx1,-, respectively
The configuration is such that Vx2 is applied to the signal electrode 212.

Next, the details of the signal electrode drive circuit 250 having such a configuration will be described. FIG. 8 is a block diagram showing the configuration of the signal electrode drive circuit 250. In this figure, a row address generation unit 2510 generates a row address Rad for reading four rows of on / off bits indicating on / off of pixels for each horizontal scanning period. Therefore, the row address generation unit 2510 causes the row address Rad
Is reset by a field start pulse FP (see FIG. 5A) supplied at the beginning of the fields f1, f2, f3, f4 and is stepped by a clock signal YCK having a cycle of one horizontal scanning period. Has become. That is, the row address generation unit 2510 is generally the p-th (where p is 1, 2, 3,
, 40) in the horizontal scanning period, the {4 (p-1) +1} -th line, the {4 (p-1) +2} -th line, and the {4 (p-1) +3} -th line counted from the top. Line and the fourth {4 (p-
1) The row address Rad for reading the on / off bits D for the four rows of pixels located in the +4} th row is generated.

Subsequently, the display memory 2520 has an area of 160 rows × 120 columns. On the writing side, the on / off bit D of the pixel is written in the address designated by the write address Wad, while on the reading side. Then the row address R
On-off bits for 4 rows designated by ad are read out collectively for 120 columns. The on / off bit D of the pixel is at the H level when the pixel is to be turned on (when white display is to be performed in the normally black mode), and when the pixel is to be turned off (normally In the case of black display in the case of black mode), the L level is set.

Further, in the display memory 2520, generally, the signal electrode 212 of the j-th column and the {4 (p-1) -th column.
The on / off bit of the pixel corresponding to the intersection with the scan electrode 312 in the (+1) th row is output to the line Aj. Similarly, the signal electrode 212 of the j-th column and the {4 (p-1) +2} th row, the {4 (p-1) +3} th row, and the {4 (p-1) + th row.
4}, the on / off bits of the pixels corresponding to the intersections with the scan electrodes 312 are the lines Bj, Cj, Dj, respectively.
Is output to.

Since the row address Rad is stepped by the clock signal YCK having a cycle of one horizontal scanning period, as shown in FIG. 9, the on / off bit supplied to the line Aj is one horizontal scanning period. There are four lines for each (1H), and there are 1, 5, 9, 13, ..., 157 lines, and j
It corresponds to the pixels located in the column. Similarly, the on / off bits supplied to the line Bj are also divided into four rows every one horizontal scanning period (1H), and 2, 6, 10, 14,
... This corresponds to the pixel located in the 158th row and the jth column, and the lines Cj and Dj are also as illustrated.

Next, referring to FIG. 8, a decoder group 2530
Is the voltage + Vx2, + Vx1, Vc, -Vx1, -Vx
A selection signal d indicating which of the two should be selected,
e, f, g, and h are output corresponding to each of the 120 signal electrodes 212. Specifically, the decoder group 2530 is
A decoder 2540 corresponding to the signal electrode 212 and one to one is provided. Here, the decoder 2540 corresponding to the signal electrode 212 of the j-th column firstly has an EX-OR circuit 2552 for obtaining an exclusive OR of the logic level of the line Aj and the logic level of the scan code CY1. 2, an EX-OR circuit 2554 for obtaining an exclusive OR of the logic level of the line Bj and the logic level of the scan code CY2, and third, the exclusive OR of the logic level of the line Cj and the logic level of the scan code CY3. An EX-OR circuit 2556 for obtaining a logical sum,
Fourthly, the EX-OR circuit 2 for obtaining the exclusive OR of the logic level of the line Dj and the logic level of the scan code CY4.
558, and fifthly, the number of L levels (that is, the number of coincidences) is counted in each exclusive OR, and any one of the selection signals d, e, f, g, and h is determined according to the count result. And a converter 2560 that outputs Among them, the converter 2560 sets only the selection signal d to the H level when the count result is “0”, sets only the selection signal e to the H level when the count result is “1”, and the count result is If it is "2", only the selection signal f is set to H level, if the count result is "3", only the selection signal g is set to H level, and if the count result is "4", only the selection signal h is set to H level. Level.

Subsequently, the level shifter group 2570 expands the voltage amplitudes of the selection signals d, e, f, g and h, respectively.
The selection signals d ', e', f ', g', and h'are output. Next, the selector group 2580 selects the selection signal d ′,
Voltage + Vx2, + V depending on e ', f', g ', h'
Any one of x1, Vc, -Vx1, and -Vx2 is actually selected and applied to the signal electrode 212. Therefore, in the selector group 2580, the voltage + Vx2, + Vx1, Vc, -Vx1,-is applied to one signal electrode 212 in accordance with the selection signals d ', e', f ', g', h '. Vx2
There are five switches for selecting.

<Operation of Display Device> Next, the operation of the above-described display device 100 will be described.

<Voltage Waveform of Scan Signal> First, the scan signals Y1 and Y output from the scan electrode driving circuit 350.
The voltage waveforms of 2, Y3, ..., Y160 will be examined focusing on the frame in which the frame signal FR is at the L level. In the field f1 of the frame, the scan code generating unit 108 corresponds to the elements of the first column in the scan pattern, “+1”, “−1”, “+1”, and “+1”, and the scan code CY1, CY2, CY3, and CY4 are set to H, L, H, and H levels, respectively, and output (FIG. 5).
(See (a)). On the other hand, when the field start pulse FP is supplied, the shift register 3520 sequentially latches the field start pulse FP at the rising edge of the clock signal YCK and transfers the transfer signals Ys1, Ys2, Ys3, as shown in FIG. Output as Ys40. Therefore, the shift register 3520 only shifts the transfer signal Ys1 to H during the first horizontal scanning period (p = 1).
Level. As a result, the first line, the second line, the third line
Selection of the scan electrodes 312 in the fourth and fourth rows is instructed.

Therefore, in the decoder group 3540, the selection signal a corresponding to the first row, the third row and the fourth row and the selection signal c corresponding to the second row become H level, respectively. For the other fifth to 160th lines, the transfer signals Ys2 to Ys40 are at the L level, so that the selection signal b is at the H level. Therefore, as shown in FIG. 10, in the first horizontal scanning period (1H) in the field f1, the scanning signal Y
1, Y2, Y3 and Y4 have voltages + Vy and −, respectively.
Vy, + Vy, and + Vy, while the other scanning signals have voltage Vc.

When one cycle of the clock signal YCK has elapsed, the shift register 3520 sets only the transfer signal Ys2 to the H level in the second horizontal scanning period (p = 2) as shown in FIG. As a result, the scanning electrodes 31 on the fifth, sixth, seventh and eighth rows are formed.
The selection of 2 is instructed. Therefore, the decoder group 354
0, the selection signal a corresponding to the fifth row, the seventh row, and the eighth row and the selection signal c corresponding to the sixth row become H level, and the other first row -For the 4th row and the 9th to 160th rows, since the transfer signals Ys1 and Ys3 to Ys40 are at the L level,
Each of the selection signals b becomes H level. For this reason,
As shown by 0, in the second horizontal scanning period (1H) in the field f1, the scanning signals Y5, Y
6, Y7 and Y8 are voltages + Vy, -Vy,
+ Vy and + Vy, while the other scanning signals are voltage V
c. Hereinafter, in the field f1, the similar operation is the fourth.
This is repeated until the 0th horizontal scanning period (p = 40).

Next, in the field f2, the scan code generator 108 scans in correspondence with the elements "+1", "+1", "-1", "+1" of the second column in the scan pattern. Codes CY1, CY2, CY3, and CY4 are set to H, H, L, and H levels and output (FIG. 5).
(See (a)). Therefore, first, in the first horizontal scanning period (p = 1) in which only the transfer signal Ys1 is at the H level, in the decoder group 3540, the selection signals corresponding to the first row, the second row, and the fourth row are selected. a and the selection signal c corresponding to the third row are at the H level, and the selection signals b corresponding to the other fifth to 160th rows are at the H level. As shown
The first horizontal scanning period (1
In H), the scanning signals Y1, Y2, Y3 and Y4 have the voltages + Vy, + Vy, -Vy and + Vy, respectively, while the other scanning signals have the voltage Vc. Subsequently, in the second horizontal scanning period (p = 2) in which only the transfer signal Ys2 is at the H level, the scanning signals Y5, Y6, Y7 and Y8.
Are the voltages + Vy, + Vy, -Vy and + Vy, respectively.
On the other hand, the other scanning signals have the voltage Vc. Hereinafter, in the field f2, the same operation is repeated until the 40th horizontal scanning period (p = 40).

Further, in the field f3, the scan code generator 108 corresponds to the scan column corresponding to the elements "-1", "+1", "+1", "+1" of the third column in the scan pattern. CY1, CY2, CY3, and CY4 are set to L, H, H, and H levels and output (FIG. 5).
(See (a)). Therefore, first, in the field f3, in the first horizontal scanning period (p = 1) in which only the transfer signal Ys1 is at the H level, as shown in FIG.
The scanning signals Y1, Y2, Y3 and Y4 have the voltages -Vy, + Vy, + Vy and + Vy, respectively, while the other scanning signals have the voltage Vc. Subsequently, the second horizontal scanning period (p = 2) in which only the transfer signal Ys2 is at the H level
Then, the scanning signals Y5, Y6, Y7, and Y8 have the voltages -Vy, + Vy, + Vy, and + Vy, respectively, while the other scanning signals have the voltage Vc. Hereinafter, in the field f3, the same operation is performed in the 40th horizontal scanning period (p =
It will be repeated until 40).

Then, in the field f4, the scan code generator 108 corresponds to the scan column corresponding to the elements "+1", "+1", "+1", "-1" of the third column in the scan pattern. CY1, CY2, CY3, and CY4 are set to H, H, H, and L levels and output (FIG. 5).
(See (a)). Therefore, first, in the field f4, in the first horizontal scanning period (p = 1) in which only the transfer signal Ys1 is at the H level, as shown in FIG.
The scanning signals Y1, Y2, Y3, and Y4 have the voltages + Vy, + Vy, + Vy, and -Vy, respectively, while the other scanning signals have the voltage Vc. Subsequently, the second horizontal scanning period (p = 2) in which only the transfer signal Ys2 is at the H level
Then, the scanning signals Y5, Y6, Y7, and Y8 have the voltages + Vy, + Vy, + Vy, and -Vy, respectively, while the other scanning signals have the voltage Vc. Hereinafter, in the field f4, the same operation is performed in the 40th horizontal scanning period (p =
It will be repeated until 40).

In the next frame in which the frame signal FR becomes H level, the scan code generator 108 causes the scan code CY in the period in which the frame signal FR is L level.
The polarities of 1, CY2, CY3, and CY4 are inverted and output (see FIG. 5A). Therefore, the frame signal FR is H
Scan signals Y1 and Y output in the level period
2, Y3, ..., Y160 are the polarity-inverted scan signals output during the period when the frame signal FR is at the L level.

<Voltage Waveform of Data Signal> Next, the data signals X1 and X output from the signal electrode drive circuit 250.
The voltage waveforms of 2, X3, ..., X120 will be examined by exemplifying the display contents of pixels. Here, the 1st to 8th lines
If the pixels located in the first column and the second column among the pixels located in the row have the display contents as shown in FIG. 10, what voltage is the data signal X1 and X2 respectively? It will be described focusing on whether or not.

In the field f1 of the frame in which the frame signal FR becomes L level, the scan codes CY1 and CY
2, CY3 and CY4 are H, respectively, as described above.
It becomes L, H, H level. On the other hand, in the first horizontal scanning period (p = 1) in the field f1, the on / off bits corresponding to the pixels in the first to fourth rows are read from the display memory 2520. Here, referring to FIG. 10, since the display contents of the pixels in the 1st row and 1st column, the 2nd row and 1st column, the 3rd row and 1st column, and the 4th row and 1st column are all on, the display memory 25
The on / off bit read from 20 corresponding to the pixel also becomes H level. The on / off bits are output to the lines A1, B1, C1, and D1, respectively, and set to 1 respectively.
EX-OR circuits 2552, 2554, 2 corresponding to the column
Scan code CY by 556 and 2558, respectively
When compared with 1, CY2, CY3, and CY4, the count result of the number of coincidences in the converter 2560 corresponding to the first column is “3”, and thus the voltage of the data signal X1 is −Vx1 during the horizontal scanning period. Become. Also, 1 row, 2 column, 2
The display contents of the pixels in the row 2 column, the 3 row 2 column, and the 4 row 2 column are ON, OFF, ON, and ON, respectively.
The on / off bits read from 520 corresponding to the pixel are also H, L, H, and H, respectively. Therefore, 2
As a result of counting the number of coincidences in the converter 2560 corresponding to the column becomes “4”, the voltage of the data signal X2 becomes −Vx2 in the horizontal scanning period. Similarly, for the third and subsequent columns, the data voltage is defined according to the display content of the pixel in the first one horizontal scanning period.

Next, the second horizontal scanning period (p =
In 2), on / off bits corresponding to the pixels of the fifth row to the eighth row are read from the display memory 2520. Here, referring to FIG. 10, 5 rows 1 column, 6 rows 1 column, 7 rows 1
Since the display contents of the pixels in the column and the 8th row and 1st column are ON, OFF, OFF, and OFF, the ON / OFF bits read from the display memory 2520 corresponding to the pixel are H, L, L, and L, respectively. Become. Therefore, as a result of counting the number of coincidences in the converter 2560 corresponding to the first column becomes “2”, the voltage of the data signal X1 becomes Vc in the horizontal scanning period. Also, 5 rows and 2 columns, 6 rows and 2
Since the display contents of the pixels in the column, the 7th row and the 2nd column, and the 8th row and the 2nd column are all off, the on / off bits read from the display memory 2520 corresponding to the pixel are all L.
Therefore, as a result of counting the number of coincidences in the converter 2560 corresponding to the second column becomes “1”, the voltage of the data signal X2 becomes + Vx1 in the horizontal scanning period.
The data voltage is similarly defined for the ninth and subsequent rows.

Next, in the field f2, the scan codes CY1, CY2, CY3 and CY4 are at H, H, L and H levels, respectively, as described above. On the other hand, the first horizontal scanning period (p =
In 1), the on / off bits corresponding to the pixels in the first to fourth rows are read again from the display memory 2520.
Therefore, the count result of the number of coincidences in the converter 2560 corresponding to the first column is “3”, and the voltage of the data signal X1 becomes −Vx1 in the horizontal scanning period.
In addition, since the count result of the number of coincidences in the converter 2560 corresponding to the second column is "1", the voltage of the data signal X2 becomes + Vx1 in the horizontal scanning period. In the subsequent second horizontal scanning period (p = 2), when the on / off bits corresponding to the pixels in the fifth to eighth rows are read out again from the display memory 2520, the first column and the second column are read. As a result of counting the number of coincidences in the converter 2560 corresponding to “2” and “1”, respectively, the data signals X1 and X2 in the horizontal scanning period are the voltage V respectively.
c, + Vx1.

Next, in the field f3, the scan codes CY1, CY2, CY3 and CY4 are at L, H, H and H levels, respectively, as described above. On the other hand, the first horizontal scanning period (p =
In 1), the on / off bits corresponding to the pixels in the first to fourth rows are read again from the display memory 2520. Therefore, the converters 256 corresponding to the first and second columns
The count result of the number of matches at 0 is "3",
As a result of becoming “2”, the data signals X1 and X2 become the voltages −Vx1 and Vc, respectively, in the horizontal scanning period.
In the subsequent second horizontal scanning period (p = 2), when the on / off bits corresponding to the pixels of the fifth row to the eighth row are read again from the display memory 2520, the first column, the second row, and the second row are read.
As a result of counting the number of coincidences in the converter 2560 corresponding to the column becomes “0” and “1”, respectively, the data signals X1 and X2 become the voltages + Vx2 and + Vx1 in the horizontal scanning period.

Then, in the field f4, the scan codes CY1, CY2, CY3 and CY4 are at H, H, H and L levels, respectively, as described above. On the other hand, the first horizontal scanning period (p =
In 1), the on / off bits corresponding to the pixels in the first to fourth rows are read from the display memory 2520 four times. Therefore, the converters 256 corresponding to the first and second columns
The count result of the number of matches at 0 is "3",
As a result of becoming “2”, the data signals X1 and X2 become the voltages −Vx1 and Vc, respectively, in the horizontal scanning period.
In the subsequent second horizontal scanning period (p = 2), when the on / off bits corresponding to the pixels of the fifth row to eighth row are read from the display memory 2520 four times, the first column, the second row
As a result of counting the number of coincidences in the converter 2560 corresponding to the column becomes “2” and “1”, respectively, the data signals X1 and X2 become the voltages Vc and + Vx1 in the horizontal scanning period, respectively.

In the frame in which the frame signal FR becomes H level, the ON / OFF bit read from the display memory 2520 is the same as the ON / OFF bit in the frame in which the frame signal FR becomes L level as long as the display contents are the same. . However, scanning codes CY1, CY2,
Since the polarities of CY3 and CY4 are inverted from the frame in which the frame signal FR becomes L level (see FIG. 5A), the data signals X1, X2, X3, ..., X120 in the frame in which the frame signal FR is H level are inverted. The voltage waveform is
As shown in FIG. 10, the voltage of the frame in which the frame signal FR is at the L level is inverted with respect to the voltage Vc.

As described above, in this embodiment, the four scan electrodes 312 are simultaneously selected, and the selected scan electrodes 3 are selected.
Polarity of scanning signal applied to 12 (logic signal indicating)
Then, the voltage applied to the signal electrode 212 is defined according to the number of coincidence of ON and OFF (logic signal indicating) of the four pixels located on the selected scan electrode. In the present embodiment, the scanning signals Y1, Y2, Y3, ..., Y160.
And the data signals X1, X2, X3, ..., X120 are
Since the polarity is inverted with respect to the voltage Vc for each frame, no DC component remains in the liquid crystal 160. Therefore, the deterioration of the liquid crystal 160 due to the application of the DC component can be prevented. Note that the configuration may be such that the period of the frame signal FR is extended and the polarity is inverted every two or more frames instead of every frame. Further, according to the present embodiment, the selection in one frame is dispersed four times in time, so that the non-selection period becomes short as shown in FIG. For this reason, the variation in the brightness of the ON pixels is particularly small, so that the reduction of the contrast ratio is prevented.

<Relationship between Content of Selected Pixel and Signal Voltage> In the above-described operation, the on / off state of the pixel located on the selected scan electrode 312 is limited to the content shown in FIG. In the form, there are 16 (= 2 ⁴ ) combinations of ON / OFF states of pixels because the number of scanning electrodes selected at the same time is “4”. Therefore, in FIG.
First, in all of these combinations, it is determined what voltage the signal electrode is defined in the fields f1 and f.
It is shown for every 2, f3, and f4. Note that this chart shows a frame in which the frame signal FR is at the L level.

As shown in this figure, if 16 kinds of on / off states appear with the same probability, the voltage most likely to be selected among the voltages taken by the signal electrodes is V.
c (24 times), then ± Vx1 (16 times each), ±
The order is Vx2 (4 times each). Here, the case where 16 kinds of on / off states appear with almost the same probability means that gradation display using the frame rate control method is performed for all pixels, and the gradation correlation between adjacent pixels is Is low (for example, when a photographic image or the like is displayed).

However, considering the use of a passive matrix type display device, it is rare to display a photographic image or the like on the whole surface, but rather to display a character or a line drawing against a white or black background. Is common. In the display of this character or the like, since the pixel serving as the background color is dominant, all four pixels among the 16 on / off states are turned on or off (see FIG. 1).
(Refer to the arrow in 1) appears with an overwhelming probability. That is, in the present embodiment, of the voltages taken by the signal electrodes,
The voltage most likely to be chosen is actually either -Vx1 or + Vx1. In this embodiment,
In the signal electrode drive circuit 250, 12 in one horizontal scanning period.
Since the voltage is simultaneously supplied to the zero signal electrodes 212, it is considered that the load on the voltage −Vx1 and the load on the voltage + Vx1 are both high. On the other hand, voltage + Vx
The appearance probability of 2, -Vx2 is extremely low without considering the content of the display image. Therefore, the voltage + Vx2, -V
The load on x2 is considered low.

The voltage + Vx2 is applied to the switches 4522, 45.
It is generated by doubling the voltage Vcc by a circuit composed of 24 and capacitors 4512 and 4514. When the clock signal CK1 is at the H level, the capacitor 4514 is discharged, so that the voltage Vx2 is actually slightly lower than the set value as shown in FIG. Conventionally, the voltage + Vx1 is generated only by the circuit (conventional configuration) including the switches 4566 and 4568 and the capacitors 4554 and 4574. Therefore, ideally, as shown in FIG. It should be an intermediate voltage with Vc (= Vcc). However, in practice,
Since the load on the voltage + Vx1 is higher than that on the voltage + Vx2, the discharge of the capacitor 4574 progresses further in the conventional configuration, and as a result, it decreases as indicated by the symbol B in the figure.

On the other hand, in the present embodiment, the voltage obtained by buffering the intermediate voltage by the operational amplifier 4544 is parallelized with the holding voltage of the capacitor 4574 and output as the voltage + Vx1. Therefore, capacity 4
The voltage drop due to the discharge of 574 is
Since the voltage + Vx1 is raised by the buffering voltage by 44, the voltage + Vx1 in the present embodiment hardly becomes a voltage drop as indicated by a symbol C in FIG. In addition, when a variation such as a voltage drop occurs, a difference in effective voltage value applied between pixels having the same content results in a difference in passing light amount.
So-called display unevenness occurs. In the present embodiment, since this voltage fluctuation is prevented, display unevenness is prevented beforehand.

Each of the switches 4566 and 4568 is actually formed by combining a plurality of transistors. For example, the switch 4566 can be simply described. An N-channel transistor whose gate is the clock signal CK2 is inserted between one end of the capacitor 4554 and the power supply line 4505, and a P-channel transistor whose gate is the clock signal CK2. The transistor is connected to one end of the capacitor 4554 and the power supply line 4.
It is the structure inserted between 504 and 504. In the present embodiment, there is no problem even if the transistors constituting the switches 4566 and 4568 (the on resistances thereof) have a higher resistance than the conventional one due to the parallelization with the operational amplifier 4544. Therefore, the area required for forming the transistor can be reduced. On the other hand, in the present embodiment, in order to generate the voltage + Vx1, an operational amplifier 4544 is separately required as compared with the conventional configuration, but most of the current transiently flowing to the pixel (capacitance) is supplied by the capacitor 4574. Therefore, high performance is not required for the operational amplifier 4544. Therefore, the area required for forming the operational amplifier 4544 can be reduced to such an extent that it can be arranged in an empty space generated by downsizing of the switches 4566 and 4568 (transistors forming the switches).
Note that the resistors 4536 and 4538 have extremely high resistance as described above, and thus the area required for formation can be almost ignored.

Therefore, in the present embodiment, the operational amplifier 4
The increase in circuit area due to the addition of 544 is avoided.
Further, in this embodiment, the size required for the capacitor 4554 can be made smaller than that of the conventional configuration by parallelizing the operational amplifier 4544. Therefore, in the present embodiment, the area required for the circuit for generating the voltage + Vx1 is reduced as compared with the above-described conventional configuration, and the voltage + Vx1 is used.
Is prevented, and display unevenness due to the variation is prevented. The same applies to the circuit that generates the voltage −Vx1, that is, the switches 4562 and 4564,
The operational amplifier 4542 is connected to the capacitors 4552 and 4572.
The same can be said about the circuit with the addition of.

<Application Example of First Embodiment> Next, an application example of the first embodiment will be described. In the above-described first embodiment, one frame is equally divided into four fields f1 to f4 and the selection is temporally dispersed, but the present invention is not limited to this. For example, as shown in FIG. 12, each selection may be temporally aggregated. Ie 4
The scanning electrodes 312 of the book are collectively selected every four horizontal scanning periods, and the selection voltage corresponding to the element of the column direction component in the scanning pattern is set to 1 in the four horizontal scanning periods.
A configuration may be adopted in which application is sequentially performed every horizontal scanning period (1H).

In order to centralize the selections in this way, the shift register 3520 (see FIG. 6) uses the frame start pulse YD instead of the field start pulse FP.
The transfer signal Ys1 is sequentially shifted every four horizontal scanning periods,
, Ys40, and the scan code generation unit 108 sequentially outputs the scan codes CY1, CY2, CY3, and CY4 in each horizontal scan period in the four horizontal scan periods. It may be configured.

However, in this configuration, as shown in FIG. 13B, the non-selection period becomes longer than that in the above-described embodiment. For this reason, the brightness variation of the ON pixel becomes large, and the contrast ratio is lowered, which is disadvantageous in the display quality in comparison with the embodiment. However, in this application example, the drive frequency of the shift register 3520 is reduced, which is advantageous in terms of power consumption as compared with the embodiment.

Whether to disperse the selections in time as in the embodiment or to aggregate the selections in time as in the application example should be decided by a matter to be prioritized. Therefore, it is desirable to have a configuration in which both the embodiment and the application example can be driven, and either one is selected according to various conditions.

<Application of Signal Voltage Generating Circuit> The signal voltage generating circuit 450 is not limited to the configuration shown in FIG.
Various configurations are possible. For example, in FIG. 2, the capacitor 4512 measures the voltage of the power supply line 4504 by changing the voltage of the power supply line 4504.
Although the configuration is such that the line voltage of 2, 4504 is raised, conversely, the voltage of the power supply line 4502 is changed to the power supply line 4502,
The line voltage of 4504 may be lowered.
In this configuration, the lowered voltage is -Vx2,
The voltage Vcc is used as it is as + Vx2, respectively.

Further, for example, as shown in FIG. 14, resistors 4582 and 4588 and an operational amplifier 4593 may be further provided. Specifically, power supply lines 4502 and 4506
Two resistors 4582 having the same resistance value between
4588 is connected in series, the voltage dividing point is connected to the positive input terminal of the operational amplifier 4593, and the output of the operational amplifier 4593 is supplied to the power supply line 4504 and fed back to its negative input terminal. Is also good. In this configuration, for example, even if the voltage + Vx2 of the power supply line 4506 fluctuates or is distorted, the voltage Vc of the power supply line 4504 is corrected to an intermediate value between the voltage + Vx2 and the voltage -Vx2 of the power supply line 4502. It Voltage + Vx1 is voltage + Vx2
Is generated to have an intermediate value between the voltage Vc and the voltage Vc, and the voltage −Vx1 is generated to have an intermediate value between the voltage Vc and the voltage −Vx2. Therefore, according to the configuration shown in FIG. Voltage + Vx2, + Vx1, Vc, -Vx1, -Vx
Even if there is a fluctuation or distortion in any of the two, the line voltage between the adjacent power supply lines can be constantly made uniform.

<Others> In the above embodiment,
The clock signals CK1 and CK2 are signals obtained by dividing the clock signal YCK by two. However, with this configuration,
In FIG. 3, a difference occurs between the voltages + Vx2 and + Vx1 in the odd-numbered horizontal scanning period and the even-numbered horizontal scanning period, which causes display unevenness. Therefore, actually, as shown in FIG. 15, the frequencies of the clock signals CK1 and CK2 are doubled (that is, the same as the clock signal YCK).
As a configuration, a configuration is adopted in which there is no difference between the voltages + Vx2 and + Vx1 in the odd-numbered horizontal scanning period and the even-numbered horizontal scanning period.

Further, in the above-described first embodiment and its application example, since the scanning pattern shown in FIG. 5B is used, the number of scanning electrodes 312 to be simultaneously selected is set to "4" and one frame is set. At the same scan electrode 312
However, the present invention is not limited to this. That is, any scanning pattern may be used as long as the normality and the orthogonality are satisfied.
Therefore, since the scanning pattern is not limited to the square matrix, it is naturally possible that the number of scanning electrodes selected at the same time does not match the number of times the same scanning electrode 312 is selected in one frame.

In addition to the above-described first embodiment and its application example, a technique of setting some of the scanning electrodes selected simultaneously as virtual electrodes and reducing the number of voltages that can be applied to the signal electrodes is applied. good. In summary, the number of matches between the on / off bits of the pixels located on the virtual electrode and the element indicating the voltage applied to the scan electrode is controlled, and the value that the total number of matches or the number of mismatches can have is kept within a certain range. By
This is a technique of reducing the number of voltages applied to the signal electrodes.

Further, in the above-described first embodiment and its application example, the case where the liquid crystal is the TN type or the STN type has been described, but BTN (Bi-stable Twisted Nematic) is used.
Type, ferroelectric type and other bistable type with polymer property, polymer dispersion type, and constant dye (guest) with anisotropy in visible light absorption in the major axis direction and minor axis direction of the molecule It is also possible to use a guest-host type liquid crystal in which dye molecules are dissolved in a liquid crystal (host) having the above molecular arrangement and the dye molecules are arranged parallel to the liquid crystal molecules. In addition, a configuration of vertical alignment (homeotropic alignment) in which liquid crystal molecules are arranged vertically to both substrates when no voltage is applied, while liquid crystal molecules are arranged horizontally to both substrates when voltage is applied It is good that the liquid crystal molecules are aligned horizontally with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned vertically with respect to both substrates when voltage is applied, which is a parallel (horizontal) orientation (homogeneous orientation). It may be configured.

As described above, various liquid crystals and alignment methods can be used as long as they are compatible with the driving method of the present invention. Furthermore, these liquid crystal devices can be applied to any of a transmissive type, a reflective type, and a semi-transmissive semi-reflective type that uses both of them. In addition, the present invention, in addition to these liquid crystal devices, electroluminescence for arranging a plurality of pixels in a matrix and emitting the light,
It can also be applied to self-luminous passive matrix devices such as fluorescent display tubes and plasma displays. That is, the present invention can be applied to all display devices that simultaneously select a plurality of scan electrodes.

<Electronic Device> Next, some electronic devices using the display device according to the above-described embodiment will be described.

<Part 1: Mobile Phone> First, an example in which the above-described display device 100 is applied to a display unit of a mobile phone will be described. FIG. 16 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 2100 includes a plurality of operation buttons 2102, an earpiece 2104, and a mouthpiece 210.
6 and the display device 100 described above. When the display device 100 is a liquid crystal device, in order to ensure visibility in a dark place, a backlight is a transmissive type or a semi-transmissive / semi-reflective type, and a front light is a reflective type (all are not shown). Are provided respectively.

<Part 2: Digital Still Camera> Next, a digital still camera in which the above-described display device 100 is used as a finder will be described. FIG. 17 is a perspective view showing the back surface of this digital still camera.
A normal silver halide camera exposes a film by an optical image of a subject, whereas a digital still camera 2200
Is a CCD (Charge Coupled Device) that captures the optical image of the subject.
An image pickup device such as the above performs photoelectric conversion to generate an image pickup signal.

Here, the digital still camera 2200
The display device 100 described above is provided on the back surface of the case 2202 in FIG.
It is configured to display. Therefore, the display device 10
0 will function as a finder for displaying the subject. A light receiving unit 2204 including an optical lens and a CCD is provided on the front surface side (back surface side in FIG. 17) of the case 2202. Here, when the photographer confirms the subject image displayed on the display device 100 and presses the shutter button 2206, the image pickup signal of the CCD at that time is transferred and stored in the memory of the circuit board 2208.

Incidentally, this digital still camera 220
Also in 0, when a liquid crystal device is used as the display device 100, a backlight is provided on the back surface (not shown) in order to ensure visibility in a dark place. Further, in this digital still camera 2200, a case 2202
Video signal output terminal 2 for external display on the side of
212 and an input / output terminal 2214 for data communication are provided.

<Summary of Electronic Equipment> As the electronic equipment, in addition to the mobile phone shown in FIG. 16 and the digital still camera shown in FIG. 17, a television, a viewfinder type, a monitor direct-viewing type video tape recorder, and a car. Navigation device, pager, electronic organizer, calculator, word processor,
Examples thereof include workstations, videophones, POS terminals, devices equipped with a touch panel, and the like. The display device 1 described above is used as the display unit of these various electronic devices.
It goes without saying that 00 is applicable.

[0082]

As described above, in the present invention, the voltage held by the second holding element and the output voltage from the operational amplifier are parallelized and output to the third power supply line.
Voltage fluctuations are suppressed, and the increase in area due to the addition of operational amplifiers is avoided.
Since the capacity of the holding element is small, the circuit area required to generate the output voltage on the third power supply line is also reduced.
Therefore, according to the present invention, it is possible to reduce the fluctuation and generate the signal voltage and to reduce the circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a signal voltage generation circuit in the display device.

FIG. 3 is a diagram showing waveforms of clock signals CK1 and CK2 supplied to the signal voltage generation circuit and voltage waveforms generated.

FIG. 4 is a diagram showing a relationship between voltages generated by a scanning voltage generation circuit and a signal voltage generation circuit in the display device.

FIG. 5A is a timing chart showing an output state of a scan code by a scan pattern generating section in the display device, and FIG. 5B is a diagram showing a scan pattern used in the display device.

FIG. 6 is a block diagram showing a configuration of a scan electrode driving circuit in the display device.

FIG. 7 is a timing chart showing an operation of a shift register in the scan electrode driving circuit.

FIG. 8 is a block diagram showing a configuration of a signal electrode drive circuit in the display device.

FIG. 9 is a timing chart for explaining the operation of the signal electrode drive circuit.

FIG. 10 is a timing chart showing a voltage waveform applied to a scanning electrode and a signal electrode in the display device in relation to display contents of pixels corresponding to intersections of both electrodes.

FIG. 11 is a chart showing a relationship between display contents of pixels corresponding to intersections of scanning electrodes and signal electrodes and voltages taken by the signal electrodes in each selection in the display device.

FIG. 12 is a timing chart showing a voltage waveform applied to a scanning electrode and a signal electrode in a display device according to an application example of the present invention in relation to display contents of pixels corresponding to intersections of both electrodes.

13A and 13B are diagrams showing optical responses in the embodiment and application example, respectively.

FIG. 14 is a circuit diagram showing an applied configuration of a signal voltage generation circuit in the display device.

FIG. 15 is a diagram showing waveforms of clock signals CK1 and CK2 supplied to a signal voltage generation circuit and voltage waveforms generated.

FIG. 16 is a perspective view showing a configuration of a mobile phone as an example of an electronic device to which the display device is applied.

FIG. 17 is a perspective view showing a configuration of a digital still camera as an example of an electronic apparatus to which the display device is applied.

[Explanation of symbols]

100 ... Display device 108 ... Scan code generator 212 ... Signal electrode 250 ... Signal electrode drive circuit 312 ... Scan electrode 350 ... Scan electrode driving circuit 450 ... Signal voltage generation circuit 4502-4506 ... Power supply line 4542, 4544 ... Operational amplifier 4552, 4554 ... Capacitance (first holding element) 4562, 4564, 4566, 4568 ... Switch 4572, 4574 ... Capacitance (second holding element) 2100 ... Mobile phone 2200 ... Digital still camera

Continued front page    F term (reference) 2H093 NA34 NC03 NC16 NC22 NC27                       NC28 NC34 NC35 ND42 ND49                 5C006 AC23 AF44 AF45 AF51 AF52                       AF53 BB12 BC03 BC12 BF14                       BF25 BF37 BF43 FA41                 5C080 AA10 BB05 DD22 FF03 FF09                       JJ02 JJ03 JJ04

Claims (5)

[Claims] 1. A pixel provided corresponding to an intersection of a scanning electrode and a signal electrode intersecting each other, and m scanning electrodes are arranged in accordance with a predetermined scanning pattern including elements of m rows and n columns. The selection is performed n times (m, n is an integer of 2 or more) per vertical scanning period, and in each selection, the voltage corresponding to each of the m elements in the column corresponding to the selection in the scanning pattern is selected. And a scan electrode driving circuit applied to each of the m scan electrodes, and an element indicating the display content of m pixels corresponding to the intersection of the signal electrode and the selected scan electrode for one signal electrode. , Detecting whether or not the m elements in the column corresponding to the selection in the scanning pattern match each other,
A display device comprising: a signal electrode drive circuit that applies a voltage corresponding to the number of matches (or the number of mismatches); and a voltage generation circuit that generates a voltage that can be applied to the signal electrodes. , Buffering an intermediate voltage between the voltage of the first power supply line and the voltage of the second power supply line, and changing the buffering voltage to a voltage corresponding to a value other than the minimum value and the maximum value of the matching number. An operational amplifier that outputs to a third power supply line for supplying any of them, a first holding element that holds a voltage between one end and the other end, and one end of the first holding element that connects the first holding element to the first holding element. In a first state in which the third holding line is separated from the third feeding line and the other end of the first holding element is separated from the third feeding line and connected to the second feeding line. And the first
A second state in which one end of the holding element is disconnected from the third power supply line and connected to the first power supply line, and the other end of the first holding element is disconnected from the second power supply line. A switch for alternately switching, and, in the second state, holding the voltage at the other end of the first holding element, so that the holding voltage is parallel to the buffering voltage. A display device having a second holding element for outputting to a third power supply line. 2. When the scanning pattern is used, the frequency of the matching number taking a value other than the minimum value and the maximum value is higher than the frequency of the matching number taking the minimum value or the maximum value. The display device according to claim 1. 3. The state in which the number of coincidences takes a value other than the minimum value and the maximum value includes a state in which all m pixels corresponding to the intersection with the selected scan electrode are turned on or off. The display device according to claim 2, wherein: 4. An electronic device comprising the display device according to claim 1. 5. An operational amplifier for buffering an intermediate voltage between the voltage of the first power supply line and the voltage of the second power supply line and outputting the buffering voltage to the third power supply line, and one end and the other end. And a first holding element that holds a voltage between the first holding element and one end of the first holding element, the first holding element being separated from the first power feeding line and connected to the third power feeding line, and the first holding element. A first state in which the other end of the element is separated from the third power supply line and connected to the second power supply line;
A second state in which one end of the holding element is disconnected from the third power supply line and connected to the first power supply line, and the other end of the first holding element is disconnected from the second power supply line. A switch for alternately switching, and, in the second state, holding the voltage at the other end of the first holding element, so that the holding voltage is parallel to the buffering voltage. A voltage generating circuit comprising: a second holding element for outputting to a third power supply line.