JP2003079135A - Dc-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC-DC converter that decreases noise peak, and in particular, to improve the quality of power. SOLUTION: This DC-DC converter is provided with a smoothing circuit 2, to the output side of which a ΔΣ modulation means 6 that performs the ΔΣmodulation of an analog signal or a multiple-bit digital signal is connected via an error amplifying means 4, to supply a pulse signal, the result of the output signal of the ΔΣ modulating means 6, to a power switching element 1. In this DC-DC converter, a frequency changing clock generating means 8 that outputs a clock signal by changing a sampling frequency timely is connected to the ΔΣ modulation means 6 so that the clock signal is inputted to the ΔΣ modulation means 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter provided with a ΔΣ modulation means and supplying a pulse signal resulting from the output signal of the ΔΣ modulation means to a power switch element. The present invention relates to a novel DC-DC converter that improves power supply quality.

[0002]

2. Description of the Related Art A DC-DC converter equipped with a conventional ΔΣ modulation means and supplying a pulse signal resulting from the output signal of the ΔΣ modulation means to a power switch element is equipped with a smoothing circuit 2 as shown in FIG. A ΔΣ modulator 6 for ΔΣ-modulating an analog signal or a multi-bit digital signal is provided on the output side of the smoothing circuit 2 via an error amplification circuit 4 that amplifies the difference voltage between the voltage output to the load 3 and the reference voltage 5. The error amplification circuit 4 is connected and the signal obtained by amplifying the difference voltage between the voltage output to the load and the reference voltage 5 is input to the ΔΣ modulator 6.

However, with this means, as shown in FIG. 6, the output of the error amplification circuit 4 becomes close to the DC voltage, especially when the load fluctuation is small, so that there is a problem that a noise peak appears at a specific frequency. Therefore, in order to solve this problem, input the dither signal during ΔΣ modulation,
Means have been invented to reduce the noise peaks.

As a means for reducing the noise peak in the DC-DC converter using the conventional ΔΣ modulator 6,
As shown in FIG. 7, an adder 10 is provided between the error amplifier circuit 4 and the ΔΣ modulator 6, and a dither signal generator 9 is connected to the adder 10 so that it is independent of the output signal of the error amplifier circuit 4. Add the dither signal and the output signal of the error amplification circuit 4 to the adder 1
There is a means for adding 0 and inputting the added signal to the ΔΣ modulator 6.

However, when this means is used in a DC-DC converter, as shown in FIG. 8, since the sampling frequency of the clock signal is constant, noise energy due to the clock signal is concentrated in one frequency, and the power output There was a problem that a relatively large noise peak with the same frequency as the sampling frequency occurs. Further, in particular, as the sampling frequency is higher, it is more difficult to remove noise with the LC filter, and in order to solve this problem, noise removing means such as a filter circuit must be provided.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and particularly provides a DC-DC converter for reducing noise peaks and improving power supply quality.

[0007]

In order to achieve the above object, the present invention according to claims 1 to 6 provides a clock signal in which the sampling frequency fluctuates arbitrarily in time without being affected by loads or other members. By inputting it to the ΔΣ modulation means, it is possible to greatly reduce the noise peak at a specific frequency. Further, since a frequency filter is not necessary, it is possible to reduce the size and cost of the DC-DC converter.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a DC-DC converter according to the present invention will be described below with reference to the accompanying drawings. Figure 1
Shows an embodiment of the present invention. 2 is a schematic diagram showing the relationship between frequency and signal strength according to this embodiment.

FIG. 1 is a block diagram applied to a step-down chopper, which is provided with a smoothing circuit 2, and an error amplification for amplifying a differential voltage between a voltage output to a load 3 and a reference voltage 5 on an output side of the smoothing circuit 2. Connect the error amplification circuit 4 which is a means,
It is connected to the power switch element 1 via a ΔΣ modulator 6 which is a ΔΣ modulation means for ΔΣ modulating an analog signal or a multi-bit digital signal, and a gate driver circuit 7. Further, a frequency fluctuation clock generator 8 which is frequency fluctuation clock generation means is connected to the ΔΣ modulator 6,
The frequency fluctuating clock generator 8 is configured to fluctuate the sampling frequency arbitrarily in time to output a clock signal and input the clock signal to the ΔΣ modulator 6. It should be noted that arbitrarily changing the sampling frequency with time means that the frequency changing clock generator 8 randomly changes the sampling frequency based on its own judgment, and other members such as the load 3 and the ΔΣ modulation. Bowl 6
Means not to be affected by.

The above-described structure operates as follows. The difference voltage between the voltage output to the load and the reference voltage 5 is amplified by the error amplification circuit 4, and this amplified signal is amplified by the ΔΣ modulator 6
To enter. On the other hand, the frequency fluctuating clock generator 8 temporally arbitrarily fluctuates the sampling frequency to output a clock signal, and the clock signal is input to the ΔΣ modulator 6.

Since the sampling frequency of the clock signal fluctuates arbitrarily with respect to time, noise energy due to the clock signal is appropriately dispersed without concentrating on one frequency, and as shown in FIG. It is possible to reduce the noise peak of the same frequency as a certain sampling frequency.

Next, FIG. 3 and FIG. 4 show an embodiment of a frequency fluctuating clock generator which is a main part of the present invention. The embodiment shown in FIG. 3 shows a frequency fluctuating clock generator 8 which divides a high frequency.

This frequency fluctuating clock generator is provided with a basic clock 11 having a relatively high frequency and a substantially constant cycle, and a clock division logic 12 for dividing the basic clock output by a given division ratio at its output. Connect and even
A division ratio control logic 13 is provided for the basic clock output, and the division ratio control logic output is provided for the clock division logic 1
2, the basic clock 11 is changed by the clock frequency dividing logic 12 so that the sampling frequency, which is the frequency of the frequency changing clock generator output signal, is changed arbitrarily in time based on the frequency division ratio control logic output. is there.

The above-described structure operates as follows. First, the clock dividing logic 12 divides a basic clock whose frequency is relatively constant at a relatively high frequency. Further, the sampling ratio, which is the frequency of the frequency-varying clock generator output signal, can be arbitrarily changed in time by changing the frequency division ratio of the clock frequency division logic 12 by the frequency division ratio control logic 13 arbitrarily. Therefore, it is possible to reduce the noise peak at the same frequency as the sampling frequency in the power output.

The embodiment shown in FIG. 4 shows a frequency fluctuating clock generator 8 which uses noise in the clock signal. This frequency fluctuating clock generator 8 is constructed as follows. The Zener 14 and the resistor 15 are connected in series, and the amplifier 16 is connected from the connection point of the Zener 14 and the resistor 15.
And the noise of the Zener 14 is amplified by the amplifier 16. Also, this amplifier 16 and Δ
A bandpass filter 17 is provided between the Σ-modulator 6 and the band-pass filter 17 so that noise is band-limited to a frequency range determined by a signal input to the delta-sigma modulator 8.

Note that ΔΣ by the bandpass filter 17
The frequency range determined by the signal input to the modulator 6 is
It is preferable that the frequency is equal to or higher than the frequency twice the maximum value of the input signal band of the ΔΣ modulator 6. In this embodiment, the bandpass filter 17 is interposed between the amplifier 16 and the ΔΣ modulator 6, but if the noise is limited to the frequency range determined by the signal input to the ΔΣ modulator 6, It is not necessary to provide the bandpass filter 17.

The above-described structure operates as follows. First, the noise of the Zener 14 is amplified by an amplifier. The bandpass filter 17 uses ΔΣ to amplify the amplified noise.
The frequency range is determined by the signal input to the modulator 6. This is equivalent to inputting noise limited to the required band to the ΔΣ modulator 6 as a clock signal and arbitrarily changing the sampling frequency of the clock signal with respect to time.
As described above, by using noise as the clock signal, it is possible to reduce the noise peak at the same frequency as the sampling frequency in the power supply output.

[0018]

According to the invention described in claims 1 to 6, a clock signal whose sampling frequency is not influenced by a load or other members and fluctuates arbitrarily in time is inputted to the ΔΣ modulation means. There is an effect that the noise peak at a specific frequency can be significantly reduced. Further, since the output noise peak is suppressed and the output filter can be downsized, there is an effect that it is possible to provide a practical DC-DC converter that achieves downsizing and cost reduction of the DC-DC converter.

[Brief description of drawings]

FIG. 1 is a block diagram of an example showing an example of an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a power supply output signal of the embodiment shown in FIG.

FIG. 3 is a block diagram showing an example of a main part of the present invention.

FIG. 4 is a block diagram showing an example of a main part of the present invention.

FIG. 5 is a block diagram showing a conventional method.

FIG. 6 is a schematic diagram showing a power supply output signal of the conventional example shown in FIG.

FIG. 7 is a block diagram showing a conventional method.

FIG. 8 is a schematic diagram showing a power output signal of the conventional example shown in FIG.

[Explanation of symbols]

1 Power switch element 2 smoothing circuit 3 load 4 Error amplification circuit 5 Reference voltage 6 ΔΣ modulator 7 Gate driver circuit 8 Frequency fluctuation clock generator 9 dither signal generator 10 adder 11 basic clock 12 clock division logic 13 Division ratio control logic 14 Zener 15 Resistance 16 amplifier 17 bandpass filter

Claims (6)

[Claims] 1. A smoothing circuit is provided, and a ΔΣ modulating means for ΔΣ modulating an analog signal or a multi-bit digital signal is connected to an output side of the smoothing circuit via an error amplifying means,
In a DC-DC converter for supplying a pulse signal resulting from the output signal of the ΔΣ modulation means to a power switch element, the ΔΣ modulation means does not have any influence on a sampling frequency by a load or any other member, and the ΔΣ modulation means is arbitrarily timed A frequency varying clock generating means for outputting a clock signal by varying it in a frequency range determined by a signal input to the DC signal, and inputting the clock signal to the ΔΣ modulating means. -DC
converter. 2. The DC-DC converter according to claim 1, wherein a frequency range determined by a signal input to the ΔΣ modulation means is equal to or higher than a frequency twice a maximum value of an input signal band of the ΔΣ modulation means. DC-D characterized by
C converter. 3. The DC-DC converter according to claim 1 or 2, wherein a bandpass filter is provided in the frequency fluctuating clock generation means, and a clock signal is banded in a frequency range determined by a signal input to the ΔΣ modulation means. DC-DC characterized by being configured to limit
converter. 4. The DC-DC according to claim 1, 2 or 3.
In the converter, the frequency fluctuating clock generating means is configured to divide a pulse signal having a relatively high frequency and change the dividing ratio by a dividing logic to arbitrarily change the sampling frequency in time. A DC-DC converter characterized by being provided. 5. The DC-DC according to claim 1, 2 or 3.
In the converter, the frequency fluctuating clock generating means is configured to generate noise whose band is limited to a frequency range determined by a signal input to the ΔΣ modulating means, and use this noise as the clock signal. A DC-DC converter characterized by: 6. The DC-DC converter according to claim 5, wherein a zener and a resistor are connected in series to the frequency fluctuating clock generation means, an amplifier is connected from this connection point, and the noise of the zener is connected to the amplifier. A DC-DC converter characterized by being configured to amplify.