JP2003078402A - Noise reduction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise reduction circuit capable of stably reducing crosstalk noise and surely preventing a circuit malfunction caused by the crosstalk noise. SOLUTION: This noise reduction circuit is provided with first and second transistors and a resistance means serially connected to an output side of the second transistor, while an output side of the resistance means is connected to an output side of the first transistor with an output node, and is provided with a control circuit for controlling on/off operation timing of the first and second transistors so as to allow an output voltage outputted from the output node to be changed step by step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reduction circuit for reducing mutual interference noise (hereinafter referred to as crosstalk noise) between adjacent signals.

[0002]

2. Description of the Related Art In a conventional logic circuit, when a sudden voltage change occurs, crosstalk noise is generated in an adjacent signal, which causes a malfunction. Hereinafter, a specific description will be given with reference to the drawings.

FIG. 12 shows a conventional logic circuit (pull-up).
It is a circuit diagram which shows an example.

V1 in the figure is a Pch transistor 101.
And the source voltage of the Pch transistor 111, which is V
4 is the OUT1 voltage and the OUT2 voltage when the Pch transistor 101 is off. IN1 is Pch
A control signal for the transistor 101, OUT1 is a data output on the active side, and OUT2 is an adjacent signal.

In this conventional circuit, as shown in the timing chart of FIG. 13, when the Pch transistor 101 is turned on and off by the control signal IN1, the voltage of OUT1 changes. Under this influence, crosstalk noise is generated in the adjacent OUT2.

FIG. 14 shows a conventional logic circuit (pull-down).
It is a circuit diagram which shows an example.

V4 in the figure is an Nch transistor 121.
And the source voltage of the Nch transistor 131, V
1 is the OUT1 voltage and the OUT2 voltage when the Nch transistor 121 is off. IN1 is Nch
The transistor 121 is a control signal, OUT1 is a data output on the active side, and OUT2 is an adjacent signal.

Even in this conventional circuit, as shown in FIG.
When the Nch transistor 121 is turned on / off by the control signal IN1, the voltage of OUT1 changes. Under this influence, crosstalk noise is generated in the adjacent OUT2.

As a conventional means for reducing this crosstalk noise, the output voltage during operation of the transistor is reduced by reducing the transistor size of the Pch transistor 101 or Nch transistor 121 to lower the driving capability. It is generally practiced to make the slope gentle so that abrupt voltage fluctuations do not occur.

[0010]

However, in the above-mentioned conventional noise reduction means, the slope of the output voltage during the operation of the transistor changes due to variations in manufacturing of the transistor, etc., and as a result, stable crosstalk noise is generated. There was a problem that it could not be reduced.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to be able to stably reduce crosstalk noise and to prevent circuit malfunction caused by the crosstalk noise. It is to provide a noise reduction circuit that can be reliably prevented.

[0012]

In order to achieve the above object, in a noise reduction circuit according to the invention of claim 1, first and second transistors connected in parallel to the power source side, and the second transistor And a resistance means connected in series to the output side of the transistor, the output side of the resistance means and the output side of the first transistor are connected at an output node, and a change in the output voltage output from the output node And a control circuit for controlling the on / off operation timings of the first and second transistors so that the steps become stepwise.

In the noise reducing circuit according to the second aspect of the present invention, the n transistors connected in parallel on the power supply side and the remaining transistors other than the predetermined transistor, which is one of the n transistors, are removed. n-1 resistance means connected in series to the output sides of the n-1 transistors are provided, and the output side of each resistance means and the output side of the predetermined transistor are connected at an output node, and A control circuit for controlling on / off operation timings of the n transistors is provided so that the output voltage output from the output node changes stepwise.

According to the invention of claim 3, claim 2
In the described noise reduction circuit, the n transistors are P-channel transistors and perform pull-up operation.

According to the invention of claim 4, claim 2
In the described noise reduction circuit, the n transistors are N-channel transistors and perform pull-down operation.

According to the invention of claim 5, claim 2
The noise reduction circuit according to claim 4 is characterized in that the resistance means is composed of ON resistances of the n-1 transistors.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a circuit diagram of a noise reduction circuit according to a first embodiment of the present invention.

This noise reduction circuit includes Pch transistors 11 and 12 each sources of which are connected to the high potential side V1.
A resistor element R1 connected in series to the drain side of the Pch transistor 12 is provided, one end of the resistor element R1 and the drain side of the Pch transistor 11 are connected to the output terminal OUT1, and the resistor element R is connected to the output terminal OUT1. It is connected to the low potential side V4 via.

In the vicinity of this noise reduction circuit,
An adjacent circuit having a Pch transistor 21 and an output terminal OUT2 connected to this transistor 21 is arranged.

More specifically, V1 in the figure is
Source voltage of the Pch transistor 11, the Pch transistor 12, and the Pch transistor 21, and V4 is
OUT1 voltage when the Pch transistors 11 and 12 are off, and OUT2 voltage when the Pch transistor 21 is off.
Voltage.

IN1 is a Pch transistor 11
Is a terminal for inputting the ON / OFF control signal (IN1) of
IN2 is a terminal for inputting the ON / OFF control signal (IN2) of the Pch transistor 12, and R1 is a resistance element for controlling the voltage output to the terminal OUT1 when the Pch transistor 12 is turned on. Also, OUT1
Is a terminal for outputting data (OUT1) on the active side, and OUT2 is a terminal for outputting an adjacent signal (OUT2).

Further, in this embodiment, the output terminal OUT
1 so that the change in the voltage output from 1 becomes gradual,
A control circuit for controlling the on / off operation timing of the ch transistors 11 and 12 is connected to the terminals IN1 and IN2.

FIG. 2 shows the control signals (IN1), (IN
It is a circuit diagram of a control circuit that generates 2).

As shown in the figure, this control circuit is composed of a control signal (IN1) signal path branched from a clock IN and a control signal (IN2) signal path. The control signal (IN1) signal path includes an OR gate 51 and a delay circuit 51a, and the control signal (IN2) signal path includes an AND gate 61 and a delay circuit 61a.

In this embodiment, the Pch transistor 12 is used.
By connecting the resistance element R1 in series to the terminal OUT,
The voltage value output to 1 is controlled. That is, FIG.
As shown in the timing chart of 1., when changing the voltage of the terminal OUT1 from V4 to V1, first, the Pch transistor 12 is turned on by the control signal (IN2) to output the voltage of V2 to the terminal OUT1.
Next, by the control signal (IN1), the Pch transistor 1
When 1 is turned on, the voltage of V1 is output to the terminal OUT1.

When changing the voltage of the terminal OUT1 from V1 to V4, first the control signal (IN1) is used to change Pc to Pc.
By turning off the h-transistor 11, the terminal OU
The voltage of V2 is output to T1. Next, the control signal (IN
By turning off the Pch transistor 12 by 2), the voltage V4 is output to the terminal OUT1.

Here, V2 = (R · V1 + R1 · V4)
/ (R1 + R) V4 <V2 <V1.

As described above, in this embodiment, the terminal OUT1
By changing the voltage fluctuations of V1 → V4 and V4 → V1 that occur at 2 steps in two steps, V1 → V2 → V4 and V4 → V2 → V1, respectively, abrupt voltage fluctuations are prevented, and as a result, adjacent circuit The interference noise generated at the terminal OUT2 can be reduced.

More specifically, assuming that the output voltage V, the capacitance C1 between the output terminal OUT1 and the substrate, and the capacitance C2 between the output terminal OUT1 and the adjacent terminal OUT2 are Vnoise = V * at the adjacent terminal OUT2. C2 / (C2 + C1) noise (Vnoise) occurs.

According to the present embodiment, by gradually outputting the voltage, the voltage width V (v) is changed to V / 2 (v), and the noise (Vnoise1) to the adjacent signal is Vnoise1 = (V / 2). * C2 / (C2 + C1) = Vnoise / 2, and the noise is 1/2 that before the countermeasure.

[Second Embodiment] FIG. 4 is a circuit diagram of a noise reduction circuit according to a second embodiment of the present invention. Elements common to those in FIG. 1 are designated by the same reference numerals and their description is omitted. To do.

In the noise reduction circuit of this embodiment, in the circuit configuration shown in FIG. 1 described above, a Pch transistor 13 and a resistance element connected in series with this transistor 13 are provided between the high potential side V1 and the output terminal OUT1. It is connected to R2. The Pch transistor 13 has a control signal I
ON / OFF operation is controlled by N3. Resistance element R2
Is a terminal OUT when the Pch transistor 13 is turned on.
1 is a resistance element for controlling the voltage output to 1.

Further, V4 in the figure is the OUT1 voltage when the Pch transistors 11, 12, and 13 are all off, and the OUT2 voltage when the Pch transistor 21 is off.

In this embodiment, the control circuit for controlling the on / off operation timings of the Pch transistors 11, 12, and 13 has terminals IN1, IN2, and IN2 so that the voltage output from the output terminal OUT1 changes stepwise. It is connected to IN3.

FIG. 5 shows the control signals (IN1), (IN
2) is a circuit diagram of a control circuit that generates (IN3).

As shown in the figure, this control circuit has a control signal (IN1) signal path branched from a clock IN, a control signal (IN2) signal path, and a control signal (IN
3) for signal path. Control signal (IN
The signal path for 1) includes an OR gate 51 and a delay circuit 51.
a and 51b, the control signal (IN2) signal path includes a delay circuit 55, and the control signal (IN3) signal path includes an AND gate 61 and a delay circuit 61a,
It consists of 61b.

In the present embodiment, the Pch transistor 1
The voltage value output to the terminal OUT1 is controlled by connecting the resistance elements R1 and R2 to the terminals 2 and 13, respectively. That is, when changing the voltage of the terminal OUT1 from V4 to V1, as shown in the timing chart of FIG. 6, first, the Pch transistor 13 is turned on by the control signal IN3 to output the voltage of V3 to the terminal OUT1. . Next, by the control signal (IN2), Pch
By turning on the transistor 12, the terminal OUT
The voltage of V2 is output to 1. Finally control signal (IN1)
By turning on the Pch transistor 11, the voltage V1 is output to the terminal OUT1.

Further, when changing the voltage of OUT1 from V1 to V4, first, P is set by the control signal (IN1).
By turning off the ch transistor 11, the terminal O
The voltage of V2 is output to UT1. Next, the control signal (IN
By turning off the Pch transistor 12 by 2), the voltage of V3 is output to the terminal OUT1. Finally, by turning off the Pch transistor 13 by the control signal IN3, the voltage of V4 is output to the terminal OUT1.

Here, V2 = (R · V1 + R2 · V4)
/ (R2 + R) V3 = (R * V1 + R12 * V4) / (R12 + R) R12 = (R1 * R2) / (R1 + R2) V4 <V3 <V2 <V1.

As described above, in this embodiment, the terminal OUT1
The voltage fluctuations of V1 → V4 and V4 → V1 caused by V1 → V2 → V3 → V4 and V4 → V3 → V2 → V1 respectively.
By changing the voltage in three stages, it is possible to prevent a sudden voltage change, thereby further reducing the interference noise generated at the terminal OUT2 of the adjacent circuit.

The pull-up Pch transistor for driving the terminal OUT1 is composed of two circuits in the circuit configuration shown in FIG. 1 of the first embodiment, and in the circuit configuration shown in FIG. 4 of the second embodiment. Although it is composed of three, interference noise can be further reduced by composing of three or more.

Specifically, assuming that the output voltage V, the capacitance C1 between the output terminal OUT1 and the substrate, and the capacitance C2 between the output terminal OUT1 and the adjacent terminal OUT2, Vnoise = V * is applied to the adjacent terminal OUT2. C2 / (C2 + C1) noise (Vnoise) occurs.

When the number of Pch transistors driving the terminal OUT1 is n (a positive integer), the number of resistance elements is n-1. By gradually outputting the voltage according to the present embodiment, the voltage width is changed from V (v) to V / n.
(V). Also, noise (Vnois) to an adjacent signal
e2) becomes Vnoise2 = (V / n) * C2 / (C2 + C1) = Vnoise / n, and the noise becomes 1 / n before the countermeasure.

Here, for example, when four Pch transistors are formed, in the circuit configuration shown in FIG. 4 described above, a Pch transistor and a resistance element are added in the same manner as above, and the configuration of the control circuit is shown. 7 shows.

As shown in the figure, this control circuit has a control signal (IN1) signal path branched from a clock IN, a control signal (IN2) signal path, and a control signal (IN
3) signal path and a control signal (IN4) signal path. The signal path for the control signal (IN1) is O
An R gate 51 and delay circuits 51a, 51b, 51c, a control signal (IN2) signal path is formed by an OR gate 52 and delay circuits 52a, 52b, and a control signal (IN3) signal path is formed by an AND gate 61. The signal path for the control signal (IN4) is composed of the delay circuits 61a and 61b, and the AND gate 62 and the delay circuits 62a and 6b are provided.
It consists of 2b and 62c.

Similarly, as the number of Pch transistors and resistance elements increases, the configuration of the control circuit is such that the number of control signal signal paths in which the number of delay circuits is increased is increased.

As a substitute for the resistance elements R1 and R2,
It is also possible to use the ON resistance of the Pch transistors 12 and 13, and in this case, the resistance elements R1 and R2 are omitted.

[Third Embodiment] FIG. 8 is a circuit diagram of a noise reduction circuit according to a third embodiment of the present invention.

This noise reduction circuit includes Nch transistors 71 and 72 whose sources are connected to the low potential side V4,
A resistance element R1 connected in series to the drain side of the Nch transistor 72 is provided, and one end of the resistance element R1 and the drain side of the Nch transistor 71 are connected to the output terminal OUT1. Further, the resistance element R is connected to the output terminal OUT1. It is connected to the high potential side V1 via.

In the vicinity of this noise reduction circuit,
An adjacent circuit having an Nch transistor 81 and an output terminal OUT2 connected to this transistor 81 is arranged.

More specifically, V4 in the figure is
The source voltage of the Nch transistor 71, the Nch transistor 72, and the Nch transistor 81, which is V1.
Is OUT1 when the Nch transistors 71 and 72 are off.
Voltage and OUT2 voltage. IN1 is Nch
An ON / OFF control signal for the transistor 71, IN2
Is an ON / OFF control signal for the Nch transistor 72, and R1 is O when the Nch transistor 72 is ON.
It is a resistance element for controlling the voltage output to UT1.

Further, in this embodiment, the output terminal OUT
1 so that the change in the voltage output from 1 becomes gradual,
A control circuit for controlling the on / off operation timing of the ch transistors 71 and 72 is connected to the terminals IN1 and IN2. As the control circuit, a circuit having the same configuration as the circuit shown in FIG. 2 can be used.

In this embodiment, the Nch transistor 72 is used.
By connecting the resistance element R1 to the terminal, the voltage value output to the terminal OUT1 is controlled. That is, the terminal OU
When changing the voltage of T1 from V1 to V4,
As shown in the timing chart of FIG.
The voltage of V2 is output to the terminal OUT1 by turning on the Nch transistor 72 by N2). Next, the Nch transistor 71 is turned on by the control signal (IN1) to output the voltage of V4 to the terminal OUT1.

When changing the voltage of the terminal OUT1 from V4 to V1, first, the control signal (IN1) is used to set Nc.
By turning off the h transistor 71, the terminal OU
The voltage of V2 is output to T1. Next, the control signal (IN
By turning off the Nch transistor 72 in 2), the voltage V1 is output to the terminal OUT1.

Here, V2 = (R1 · V1 + R · V4)
/ (R + R1) V4 <V2 <V1.

As described above, in this embodiment, the terminal OUT1
V1 → V4, V4 → V1 voltage fluctuation that occurs at
V2 → V4 and V4 → V2 → V1 are changed in two stages to prevent sudden voltage fluctuations.
The interference noise generated at the terminal OUT2 can be reduced.

[Fourth Embodiment] FIG. 10 is a circuit diagram of a noise reduction circuit according to a fourth embodiment of the present invention. Elements common to those in FIG. 8 are designated by the same reference numerals, and their description will be omitted. To do.

In the noise reduction circuit of this embodiment, in the circuit configuration shown in FIG. 8 described above, an Nch transistor 73 and a resistance element connected in series with this transistor 73 are provided between the low potential side V4 and the output terminal OUT1. It is connected to R2. The Nch transistor 73 has a control signal I
ON / OFF operation is controlled by N3. Resistance element R2
Is a terminal OUT when the Nch transistor 73 is turned on.
1 is a resistance element for controlling the voltage output to 1.

Further, V1 in the drawing is the OUT1 voltage when the Nch transistors 71, 72 and 73 are all off, and the OUT2 voltage when the Nch transistor 81 is off.

In this embodiment, the control circuit for controlling the on / off operation timing of the Nch transistors 71, 72, 73 has terminals IN1, IN2, IN2 so that the voltage output from the output terminal OUT1 changes stepwise. It is connected to IN3. As the control circuit, a circuit having the same configuration as the circuit shown in FIG. 5 can be used.

In the present embodiment, the Nch transistor 7
The voltage values output to the terminal OUT1 are controlled by connecting the resistance elements R1 and R2 to the terminals 2 and 73, respectively. That is, when changing the voltage of the terminal OUT1 from V1 to V4, as shown in the timing chart of FIG. 11, first, the Nch transistor 73 is turned on by the control signal IN3 to output the voltage of V2 to the terminal OUT1. . Next, by the control signal (IN2), Nc
By turning on the h transistor 72, the terminal OU
The voltage of V3 is output to T1. Finally, the control signal (IN
By turning on the Nch transistor 71 by 1), the voltage V4 is output to the terminal OUT1.

When changing the voltage of the terminal OUT1 from V4 to V1, first, the control signal (IN1) is used to set Nc.
By turning off the h transistor 71, the terminal OU
The voltage of V3 is output to T1. Next, the control signal (IN
By turning off the Nch transistor 72 by 2), the voltage of V2 is output to the terminal OUT1. Finally, the Nch transistor 73 is turned off by the control signal IN3 to output the voltage V1 to the terminal OUT1.

Here, V2 = (R2 · V1 + R · V4)
/ (R + R2) V3 = (R12 * V1 + R * V4) / (R + R12) R12 = (R1 * R2) / (R1 + R2) V4 <V3 <V2 <V1.

Thus, in this embodiment, the terminal OUT1
V1 → V4, V4 → V1 voltage fluctuation that occurs at
V2 → V3 → V4, V4 → V3 → V2 → V1 are changed in three stages to prevent sudden voltage fluctuation,
As a result, the interference noise generated at the terminal OUT2 can be further reduced.

Note that the pull-down Nch transistor for driving the terminal OUT1 is composed of two in the circuit configuration shown in FIG. 8 of the third embodiment and three in the circuit configuration shown in FIG. 10 of the fourth embodiment. Although it is configured with three pieces, by configuring with three or more pieces, it is possible to further reduce the interference noise as in the first and second embodiments.

As a substitute for the resistance elements R1 and R2,
It is also possible to use the ON resistance of the Nch transistors 72 and 73, and in this case, the resistance elements R1 and R2 are omitted.

[0068]

As described in detail above, according to the present invention, it is possible to stably reduce the crosstalk noise and reliably prevent the circuit malfunction due to the crosstalk noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a noise reduction circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a control circuit according to the first embodiment.

FIG. 3 is a timing chart showing the operation of the first embodiment.

FIG. 4 is a circuit diagram of a noise reduction circuit according to a second embodiment of the present invention.

FIG. 5 illustrates control signals (IN1) and (I) according to the second embodiment.
It is a circuit diagram of a control circuit for generating N2), (IN3).

FIG. 6 is a timing chart showing the operation of the second embodiment.

FIG. 7 is a circuit diagram of a control circuit when four Pch transistors are formed.

FIG. 8 is a circuit diagram of a noise reduction circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the third embodiment.

FIG. 10 is a circuit diagram of a noise reduction circuit according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart showing the operation of the fourth embodiment.

FIG. 12 is a circuit diagram showing an example of a conventional logic circuit (pull-up).

13 is a timing chart showing the operation of the logic circuit shown in FIG.

FIG. 14 is a circuit diagram showing an example of a conventional logic circuit (pull-down).

15 is a timing chart showing an operation of the logic circuit shown in FIG.

[Explanation of symbols]

11, 12, 13, 21 Pch transistor 71, 72, 73, 81 Nch transistor V1 High potential side V4 low potential side R1, R2 resistance element OUT1, OUT2 output terminals

Continued front page    (72) Inventor Hiroyuki Takamura             Toshiba, 580 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             LSI System Support Co., Ltd. (72) Inventor Yoshihiro Funayama             Toshiba, 580 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             LSI System Support Co., Ltd. F-term (reference) 5J039 BB19 KK10 MM09                 5J055 AX28 AX55 AX56 AX64 BX17                       CX24 DX12 DX73 DX83 EX21                       EY01 EZ25 FX12 FX17 FX35                       GX00 GX01                 5J056 AA04 BB25 DD12 DD26 DD27                       FF07 GG02 KK00

Claims (5)

[Claims] 1. A first and a second transistor connected in parallel to a power source side, and a resistance means serially connected to an output side of the second transistor, wherein an output side of the resistance means and the first side of the second transistor are provided. One transistor is connected to the output side at an output node, and the first and second transistors are turned on / off so that an output voltage output from the output node changes stepwise.
A noise reduction circuit comprising a control circuit for controlling off-operation timing. 2. The output side of each of the n transistors connected in parallel to the power supply side and the remaining n-1 transistors excluding a predetermined transistor which is one of the n transistors. N-1 resistance means connected in series are provided, the output side of each resistance means and the output side of the predetermined transistor are connected at an output node, and a change in the output voltage output from the output node is A noise reduction circuit comprising a control circuit for controlling on / off operation timings of the n transistors in a stepwise manner. 3. The noise reduction circuit according to claim 2, wherein the n transistors are P-channel type transistors and perform pull-up operation. 4. The noise reduction circuit according to claim 2, wherein the n transistors are N-channel type transistors and perform pull-down operation. 5. The resistance means comprises on-resistances of the n−1 transistors.
5. The noise reduction circuit according to claim 4.