JP2003076730A - Support system for design of semiconductor integrated circuit, method for the design and layout editor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a support system for design of semiconductor integrated circuit enabling an easy checking of fan-outs without such a detailed cell library used in an ASIC (Application Specific Integrated Circuit) and also disabling large amounts of reversions in a design flow. SOLUTION: At a step of circuit design except for wiring information, this support system for design of semiconductor integrated circuit comprises a first computing means of computing the fan-outs at every unit cell based on the circuit information including at least output driving power and input load representing contents of each unit cell and the connecting information of each unit cell, a second means of generating a virtual wiring to connect each cell unit arranged and designed and of computing the fan-outs including effects of the virtual wiring and a third computing means of computing the fan-outs including effects of wiring laid out in a step of a layout of the wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design technology and a design support tool for a semiconductor integrated circuit having an analog circuit therein, such as a DRAM (Dynamic Random Access Mem).
The present invention relates to a technique useful for designing a semiconductor memory such as a mory), an SRAM (Static Random Access Memory), and a flash ROM (Read Only Memory).

[0002]

2. Description of the Related Art A DRAM generally called a general-purpose memory,
In semiconductor memory devices such as SRAMs and flash ROMs, a sense amplifier that amplifies a read signal, a write amplifier that amplifies a write signal, a write voltage, a precharge voltage, and a plurality of levels of voltages such as an erase voltage in a flash ROM are generated. A circuit having analog elements such as a regulator circuit and an output buffer is provided with a large functional ratio.

As for the general-purpose memory provided with such an analog circuit, there are currently insufficient tools for automatic design. Logic circuits account for a large proportion of automatic design tools, for example, ASIC (Application Spec
ific IC), and in such fields, users have various functional circuits called cells or macrocells that are unitized and designed in advance for various functions and performances. A desired integrated circuit can be designed by combining them.
Various information such as timing information of the functional circuit is described in a high-level language and registered in a database called a cell library. Then, by performing logic synthesis on the designed circuit using a computer, it becomes possible to automatically perform circuit design, layout design, and wiring design at the element level while satisfying desired functions and performances. There is.

Further, at the time of the above logic synthesis, or ST
When performing A (static timing verification), the timing information of the cells registered in the cell library is used, and the calculation of an index called fan-out that checks the driving force of each cell is also performed. This is done by using the information in the library, and the driving force of each cell is checked.

[0005]

However, in an integrated circuit such as a general-purpose memory, which occupies a large proportion of an analog circuit, it is difficult to apply the above-mentioned automatic design method used in the field of ASIC. is there. This is because the degree of freedom in designing an analog circuit is significantly larger than that of a digital circuit, so that in order to construct a similar cell library, a large amount of information needs to be registered. In a library with a narrow degree of design freedom, for example, when it is used in a memory product that places importance on speeding up and chip area reduction, the analog circuit configuration of the memory product often changes significantly for each product. We cannot respond to changes.

Further, a great deal of labor is generally required to develop a cell library. Furthermore, memory products and the like have a very long product cycle, and the product development of memory products to which the same semiconductor process is applied is significantly smaller than the product development of ASIC. Therefore, even if a cell library is developed for a general-purpose memory, its frequency of use is low, and there is a problem in that the cost cannot be allocated. Therefore, conventional general-purpose memories have not been made into cell libraries.

Therefore, in the conventional memory product design, as shown in the flowchart of FIG. 6, the circuit design in step S11, the circuit layout design in step S12, and the step S
After designing the wiring layout of 13, the fanout is manually calculated to see if there is an excess or deficiency in the driving capability of each circuit (step S14). If there is a portion where this value does not satisfy the predetermined condition, Steps S11 to S1 such as cell replacement, cell arrangement change, cell change, wiring route change, etc.
The design content at each stage of 3 was manually corrected, and the driving ability between the circuits was manually adjusted. Such a fix would be
The design TAT (tu
There was a problem that rn around time) became long.

An object of the present invention is to provide AS when designing a semiconductor integrated circuit including an analog circuit such as a memory product.
Even if there is no detailed cell library used in the IC, the driving ability between the circuits can be easily checked, and the driving ability between the circuits can be adjusted without requiring a large backtrack in the design flow. An object of the present invention is to provide a semiconductor integrated circuit design support system and a semiconductor integrated circuit manufacturing method that can be performed. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, a design support system for a semiconductor integrated circuit that supports the design of a semiconductor integrated circuit including an analog circuit, wherein the integrated circuit is a constituent element of the integrated circuit at a predetermined function in the stage of circuit design excluding wiring information. Other circuits connected to the output side for each unit cell based on the circuit information including at least the output driving force and the input load indicating the contents of each unit cell unitized and the connection information of each unit cell In the stage of the layout design of the unit cells, a virtual wiring connecting the unit cells for which the layout design of the unit cells is performed with the first computing means for computing an index relating to the driving force of the unit cell with respect to The layout is designed at the stage of layout design of the wiring connecting the unit cells and the second calculation means for calculating the index relating to the driving force including the influence of the wiring. It is obtained by a third arithmetic means for performing arithmetic metrics for the driving force, including the influence of the wiring.

According to such means, the driving force between the unit cells is checked and the driving force is adjusted at each stage of the circuit design excluding the wiring information, the circuit layout design, and the wiring layout design. Can be done. Therefore, the circuit design to the wiring layout design can be performed while adjusting the driving force between the circuits and without significantly returning to the design flow, and the design period can be shortened. Moreover, since the driving force is checked over the entire circuit at each design stage, the design accuracy can be improved.

Further, the information of each unit cell necessary for performing such design support is, for example, only the output driving force and the input load, and a detailed cell library including timing information used in ASIC is Since it is not necessary, the cost of developing the unit cell library can be reduced.

Further, the first computing means, the second computing means,
Or, as a result of the calculation by the third calculating means, when the value of the index does not satisfy the predetermined condition and an error occurs, an error output means is provided to output to which side of the integrated circuit the error occurs to the user side.

Further, the above-mentioned design support system is specifically suitable for a case where a semiconductor memory such as a DRAM, an SRAM or a flash ROM is a design target.

A method for manufacturing a semiconductor integrated circuit according to the present invention is a method for manufacturing a semiconductor integrated circuit, which comprises designing an integrated circuit containing an analog circuit and forming a circuit,
Prior to the wiring layout design, the circuit information including at least the output driving force and the input load representing the contents of each unit cell that is a component of the above integrated circuit and is unitized for each predetermined function, and each unit cell Based on the connection information, an index relating to the driving force of the unit cell with respect to the other circuit connected to the output side is calculated for each unit cell, and the design correction of the integrated circuit is performed so that the index value satisfies a predetermined condition. It is something to do.

Further, in the circuit design excluding the wiring information, the layout design of each unit cell which is a constituent element of the integrated circuit and is unitized for each predetermined function, and the layout design of the wiring, the above-mentioned design is performed. While performing the calculation of the above index using the support system, if the index value at any design stage does not satisfy the predetermined condition and an error occurs, perform design correction at the design stage until the error is resolved, It is designed to move to the next design stage after there are no errors.

Further, in a layout editor capable of editing the layout and wiring layout of the unit cells constituting the semiconductor integrated circuit while displaying an image on the design screen, after the layout design of each unit cell and the layout design of the wiring, each unit is Check the output driving power of the cell for excess or deficiency, and if there is excess or deficiency, display the unit cell or wiring part in a identifiable manner on the design screen and advise how much the wiring should be changed. The display is made. After the layout design of the unit cells and before the layout design of the wiring, a virtual wiring virtually laid out under a predetermined condition is automatically created, and the output driving force is checked using this virtual wiring.

According to such a means, when the output driving force is checked and there is an error portion, the operator can easily find the error portion on the design screen, and further the design correction can be made easily by relying on the advice display. Can be done. As a result, the design TAT can be further shortened.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional configuration diagram illustrating a design support system according to an embodiment of the present invention. The design support system of this embodiment is, for example, a DRAM or SRA.
This assists the design of a semiconductor integrated circuit in which an analog circuit occupies a large proportion in function, such as a semiconductor memory such as M, ROM, and flash ROM.

In the integrated circuit designing method of this embodiment, the analog circuit is treated as a unit cell which is unitized in advance for each function, such as an amplifier, an operational amplifier, a level shift circuit, and a constant voltage circuit. Each unit cell has, for example, a characteristic value such as an amplification factor or an SN ratio and an output M.
The circuit configuration at the element level is determined by giving some circuit constants such as the element coefficient called the gate width of the OSFET.

The design support system of this embodiment is composed of, for example, an electronic computer such as a workstation, a design support program, and a database storing a simple library. It mainly functions in each of a circuit design stage in which unit cells and logic cells are combined to form an entire circuit, a layout design stage in which the layout of each unit cell is determined, and a wiring layout design stage. As its functional configuration, as shown in FIG. 1, a data input function 2 for externally inputting design data in each of the above-mentioned design stages, according to each design stage for each analog unit cell based on the input design data The calculation function 3 for calculating the fan-out, the verification function 4 for verifying the calculation result of the fan-out, the information output function 5 for outputting the error information and the advice information indicating the simple correction direction to the user based on the verification result, etc. Is equipped with. These functional configurations are
It is realized by the CPU of the electronic computer executing the design support program. Here, the fan-out is an index of a driving force of a unit cell with respect to another circuit connected to the output side of the unit cell.

The above-mentioned simple library is a simple object code capable of determining a circuit configuration at an element level by designating a predetermined characteristic value and a predetermined element coefficient for a predetermined analog unit cell. . By registering such a simple library in the database, when the design data of the circuit configuration is input to the design support system, the design data can be coded and easily input. That is, the output driving force (gate size of the output MOSFET), the input load (gate capacitance of the input MOSFET), etc. of the unit cell can be derived from the circuit constant of the unit cell in the design support system. It should be noted that the device level design data can be input when the design data is input without using the simple library.

Next, the design procedure of the semiconductor memory of the embodiment using the above design support system will be described. Figure 2
3 is a flowchart showing an example of the design procedure. In the design flow of this embodiment, first, in step S1, the above-mentioned analog-type and logic-type unit cells are combined to form an entire circuit. When the entire circuit is assembled, fanout verification is performed on this circuit in step S2.

In the fan-out verification in step S2, first, design data representing the entire circuit assembled in step S1, that is, circuit information defining a used unit cell (a net representing a circuit constant and a connection relation of its constituent elements). (List, etc.) and netlist information indicating the connection relationship between each unit cell are input to the design support system. These circuit information and netlist information are described in a design language. When the above information is input to the design support system, fanout calculation is performed in the design support system in the following manner.

FIG. 3 is a diagram for explaining an example of the fanout calculation method at the circuit design stage. That is,
When the fan-out calculation process is started, first, the unit cell 1 to be calculated is set as a constant necessary for the fan-out calculation.
The gate width Wout of the MOSFET that drives the output at 0,
The load capacitances Wc at the input nodes of all the other unit cells connected to the output side of the unit cell 10 are extracted from the circuit information and netlist information. further,
The load capacitance Wc is converted into the gate width Wgate of the MOSFET as the gate capacitance of the MOSFET. Then, the fan-out FO1 for the unit cell 10 is calculated from these values by the following equation. FO1 = W
gate / Wout

That is, in the fan-out calculation at this design stage, since there is no information about the arrangement of each unit cell and the wiring between each unit cell, the wiring load is treated as "0". Then, the above fan-out calculation is performed for all the unit cells in the circuit, and the fan-out calculation processing ends. If there are multiple output terminals in one unit cell,
The same calculation is performed for each output terminal.

After the fan-out calculation is completed, next, the calculation result of the fan-out FO1 is verified.
As the verification method, for example, the fan-out FO1 is compared with a preset minimum value min1 and maximum value max1, respectively, and if it is between the minimum value min1 and the maximum value max1, it is determined to be appropriate, and if not, it is determined to be an error. It is a thing. Then, with respect to the portion determined to be an error, the information is output to the user via the display device or the printing device of the design support system. In addition, at the time of the output, circuit correction advice information such as how small or how large the driving force at this error location is is added.

If an error location is found in the above fan-out verification, the user again returns to step S.
Returning to the circuit design of No. 1, the circuit constant is changed or the unit cell is replaced with another unit cell in the corresponding unit cell or the unit cell in the preceding stage and the subsequent stage so as to avoid the error at the pointed out point. After the design modification of the whole circuit is completed,
The fan-out verification of step S2 is performed again. And
By repeating the above-mentioned design circuit modification and fan-out verification until there are no errors, a circuit in which the fan-out satisfies the appropriate condition for all unit cells is constructed under the condition that the influence of the wiring load is excluded. .

Next, in step S3, the user
Layout design for each unit cell. The layout design uses, for example, various evaluation functions such as reduction of the area occupied by the integrated circuit, facilitation of mounting design, and facilitation of failure diagnosis.
Each condition is optimized. And
After the layout design is completed, next, in step S4, fanout verification in consideration of the layout of each unit cell is performed in the design support system.

FIG. 4 shows an explanatory view of an example of the fan-out calculation method performed in step S4. In the fan-out verification at the design stage, first, the virtual wiring 20 is determined based on the arrangement information of each unit cell, and the virtual wiring 20 is determined.
Performs fanout calculation including the effect of. Virtual wiring 2
For example, 0 is determined for two unit units connected to each other so that the wiring is along the orthogonal X direction and Y direction and the wiring length is minimized. Then, the parasitic capacitance C1 of the virtual wiring 20 is regarded as the gate capacitance of the MOSFET and converted into the gate width Wwire of the MOSFET. Then, as fan-out FO2, the following calculation is performed. FO2 = (Wgate + Wwire) / Wout

Then, the above fan-out calculation is performed for all output terminals of all unit cells. Next, as the verification of this fan-out, it is verified whether the value is within a predetermined range from the minimum value min2 to the maximum value max2. As a result, if there is a unit cell that is out of the predetermined range and has an error, the unit cell and the advice information indicating how large or how small the driving force of the unit cell is are output.

If an error location is found, the user
In order to avoid an error at the pointed out point, the process returns to the layout design in step S3 again, and the layout of the unit cell pointed out, the unit cell connected to the united cell and its peripheral circuit is corrected by relying on the error information and the advice information. To do. Then, by repeatedly performing the layout design correction and the fanout verification as described above until the error is eliminated, the layout design in which the fanouts of all the unit cells satisfy the aptitude condition is achieved in the layout design of the virtual wiring model. It

When the layout design is completed, next, step S
In 5, the user designs the wiring layout. The wiring layout is divided into two stages, for example, rough general wiring and detailed detailed wiring. After the detailed layout design of the actual wiring 30 connecting all the unit cells is completed, the fan-out verification including the influence of the actual wiring 30 is performed in the design support system in step S6.

FIG. 5 is an explanatory diagram showing an example of a fanout calculation method including the influence of the actual wiring, which is performed in step S6. The fan-out verification in step S6 is
The same calculation as in step S4 is performed using the load capacitance of the actual wiring 30. That is, the load capacitance of the input node of each unit cell and the load capacitance of the actual wiring 30 are respectively M
Considering as the gate capacitance of the OSFET, it is converted into the gate width Wgate, Wwire0 of the MOSFET, and these values and the MOSF for driving the output terminal in the unit cell 10 to be operated.
Using ET gate width Wout, fanout FO3 is calculated as in the following equation. FO3 = (Wgate + Wwire0) / Wout

Then, the above fan-out calculation is performed for all output terminals of all unit cells, and then it is verified whether the value is within a predetermined range from the minimum value min3 to the maximum value max3. As a result, if there is a unit cell that is out of the predetermined range and has an error, the unit cell and the advice information indicating how large or how small the driving force of the unit cell is are output.

If an error location is found, the user
In order to avoid an error at the pointed out portion, the process returns to the wiring layout design in step S5 again, and the layout of the wiring connected to the indicated unit cell is corrected by relying on the error information and the advice information. By repeating the layout design correction and fan-out verification as described above until the error is resolved, a design in which the fan-out satisfies the appropriate conditions including the influence of the detailed wiring for all unit cells is achieved. It

Then, in step S7, final layout verification is performed on the circuit for which detailed wiring has been designed by various tests, diagnostics, simulations, etc., which have been conventionally performed, to complete the design. Further, after that, a mask pattern is formed according to the above design contents, and a designed semiconductor memory is formed on a semiconductor substrate through a semiconductor process.

As described above, according to the design support system of this embodiment, in the design flow of the semiconductor memory incorporating the analog circuit, the design of the circuit configuration except the design of the circuit layout and the wiring layout and the layout of each unit cell are performed. At each design stage of design and layout design of detailed wiring,
Fan-out verification is performed according to each design stage, so even if an error is found in the verification,
The error can be eliminated by correcting the design stage, and the design TAT can be performed without causing a large backtrack in the design flow.
Can be shortened.

Furthermore, since fan-out verification is appropriately performed at each design stage, it is possible to proceed with the design without destroying the optimization by the evaluation function set at each design stage. Moreover, the design quality can be improved by comprehensive fan-out verification over the entire circuit.

In the fan-out verification described above, the output driving force of each unit cell and the input load information can be separated even if there is no detailed library including timing information as in the ASIC cell library, for example. If so, the detailed cell library development cost can be reduced.
Also, when dealing with analog circuits with a large degree of design freedom,
Even if it is not costly to create a detailed cell library with a small number of product developments, a simple library of unit cells can be created and used.

Next, the layout editor for designing the layout of the unit cells and the layout for the wiring, and the procedure for the circuit design using the layout editor will be described with reference to an image display example of the layout editor. The layout editor allows the operator to design the layout of circuit unit cells using a position input device such as a tablet or digitizer, and the layout of the wiring that connects each unit cell, and operates on a computer such as a workstation. Is configured as software that

When designing using the layout editor,
A design screen on which the layout of the circuit is displayed as an image is provided on the display, and the operator can move the unit cells and wirings while designing the layout design. Also, if necessary, the image on the design screen can be enlarged, and the unit cells and wiring specified in the database can be displayed in the circuit layout image so that they can be distinguished from other parts by highlighting etc. It has become.

In the layout editor of this embodiment, only the circuit configuration is determined and the first layout before the unit cell layout design is performed.
Steps, second step after unit cell layout design and before wiring layout design, third step after wiring layout design, and
It has a guide function that performs fan-out check at each of the two stages and presents advice information that shows the location of the error and the correction guideline for avoiding the error.

FIG. 7 is a flow chart showing a processing procedure of circuit design performed by using the layout editor of the embodiment. In the circuit design in which the analog circuit occupies a large proportion, the circuit design is performed using the circuit editor after the functional design (step S11). When designing a circuit, the circuit is handled, for example, for each unit cell divided into functional units, and the circuit design is performed, and the wiring design for connecting each unit cell is also performed to complete the design of the entire circuit. Then, when the circuit design is completed, a netlist D including circuit information of each unit cell and wiring information between each unit cell is displayed in the circuit editor.
1 is created and the file is output.

After the circuit is designed, a layout editor is used to perform a first stage fan-out check (step S12). In the layout editor, the operator can select a MOS according to the semiconductor process to be applied in advance.
Input gate capacitance calculation formula T1 for elements such as FETs, gate capacitance value T2 per unit area, wiring capacitance T3 per unit area, fanout calculation formula T4 in the first to third stages, and -An error determination formula T5 indicating a fan-out threshold determined to be an error in the fan-out check in the third stage is given. Also, given the above error judgment formula T5, in the layout editor,
Based on the error judgment formula T5, a conversion formula T6 for automatically obtaining the size and length of the output MOSFET, the virtual wiring length, and the actual wiring length to avoid the error is automatically obtained. Since the conversion formula T6 is the inverse calculation of the calculation by the error judgment formula T5, the error judgment formula T5
You can easily get from.

The fan-out check in the first stage is started by selecting the check execution item from the menu provided in the layout editor. In the first-stage fan-out check, the input gate capacitance calculation formula T1, the gate capacitance value T2 per unit area, the first-stage fan-out calculation formula T4, and the net transferred from the circuit editor are input from the input data. The list D1 is used to obtain the fanout value without considering the wiring load for all the output parts of all the unit cells.

When the fan-out value is obtained,
Error judgment formula T5 for the first stage fan-out check
Based on the above, the fan-out value error judgment is performed for all the output parts of all the unit cells, and the part judged as the error is picked up. Specific examples of the fanout calculation and the error determination are as shown in the description of FIG.

Further, in accordance with the above-mentioned error judgment, the output M is calculated based on the conversion equation T6 with respect to the portion judged as an error.
It is necessary to determine how many microns the size of the OS should be to avoid the error. Then, the error result information E1 including the information indicating the part determined to be an error and the advice information indicating the size of the output MOS for avoiding the error is output as a file.

FIG. 8 is a diagram for explaining a functional module for performing fan-out check in the layout editor of this embodiment. The fan-out check of the first stage is performed by a plurality of functional modules that respectively execute the processes of the following steps S21 to S26. That is, the fan-out calculation formula interpretation step S2 in which the fan-out calculation formula T4 input by the operator in advance is taken in and interpreted so that the calculation according to the calculation formula T4 can be performed.
1 and the fan-out calculation step S22 for calculating the fan-out value according to the calculation formula T4, and the error determination formula T5 input by the operator
The fan-out error judgment formula interpretation step S23 for interpreting so as to make a judgment according to the above, the fan-out error judgment step S24 for judging a fan-out value error according to the judgment formula T5, and the judgment formula T5 are converted. A fan-out error correction value calculation step S25 for obtaining a correction value for avoiding an error in a portion determined to be an error based on the obtained error conversion formula T5, and information of the portion determined to be an error and information of the correction value in a predetermined format. It is a functional module that respectively performs a fan-out error output step S26 for collectively outputting.

Then, the first operation is performed by the operator's instruction operation.
When the fan-out check of the stage is started, each of the above functional modules automatically executes each process in cooperation with each other, and if there is an error part, the error result information E1
Up to the file output of is automatically performed.
Also in the second and third stages of fan-out check, which will be described later, the fan-out calculation formula T4, the error determination formula T5, and the error conversion formula T6 are changed according to each stage, and the other processes are performed in the same manner. . Then, the error result information E2, E3 corresponding to each stage is automatically output to a file.

FIG. 9 shows an image display example of error result information of the fan-out check in the first stage. Note that, in the figure, the comment indicated by the dotted frame is an explanation of the display content and does not mean that the image is displayed. When the error result information E1 is output, the layout editor displays G
Using the window display of the UI (Graphical User Interface), the error result information E1 is displayed and output in a window X1 different from the design window X2 as a design screen used for circuit design. The display mode is a table format in which one column corresponds to one error location, and information indicating the error location and advice information indicating a guideline for correction are displayed in text for each error location. Figure 9
In the example, "CELL *" is used as the information indicating the error location.
(Identification name of unit cell). “NET * (wiring identification name)” is displayed and “Driver Size ** μ” is displayed as advice information.
m → ** μm (a guide to change the size of the output MOS from the current ** μm to more than ** μm) ”is displayed.

Further, in each column of this window X1,
A display button for highlighting the corresponding error location on the design window X2 is displayed, and the operator indicates the error location (clicking the mouse, etc.), and information indicating the error location is passed to the circuit editor. On the design drawing of the window X2 of the circuit editor, the corresponding portion (the portion P1 of the output portion where the corresponding output driving MOS is provided and the wiring Y1 to which the driving signal is output) is highlighted. These functions constitute an error part display function.

When there is a part determined to be an error in the fan-out check in the first stage, the operator relies on the displayed error information to highlight the error part in the design window of the circuit editor, The unit cell can be modified (step S1).
8). After the correction, the procedure of performing a fan-out check to see if a new error location has occurred is repeated, whereby a circuit design having no error location is performed in the fan-out check in the first stage.

When the circuit design is completed, the netlist D1 generated by the circuit editor is input to the layout editor, so that the operator uses the layout editor to design the layout of the circuit represented by the netlist D1 (step S13). ). Then, when the arrangement of all the unit cells is decided, the menu of the layout editor is selected as in the case of the first stage to perform the fan-out check of the second stage (step S14).

In the fan-out check of the second stage, first, the input gate capacitance calculation formula T1 and the gate capacitance value T per unit area, which are input in advance in the layout editor, are made by the respective function modules provided in the layout editor.
2, the wiring capacitance per unit area T3, the fanout calculation formula T4 in the second stage, the placement data D2 indicating the placement of each unit cell obtained by the placement design of the unit cell, and each unit Based on the netlist D1 including the circuit information of cells and the connection information between unit cells, the fanout value assuming that the connection between the unit cells is connected by virtual wiring is all the output parts of all the unit cells. Asked about.

Next, from the error judgment formula T5 for the fan-out check in the second step, the fan-out value error judgment is carried out for all the output parts of all the unit cells, and the part judged as an error is picked up. Specific examples of the calculation of the fan-out value and the error determination are as shown in the description of FIG.

Further, in accordance with the error determination, the layout editor determines the length of the micron for which the virtual wiring is determined based on the conversion formula T6 to avoid the error based on the conversion equation T6. The error result information E2 including the information indicating the portion determined to be an error and the advice information indicating the length of the virtual wiring for avoiding the error is output as a file.

FIG. 10 shows an example of a display image of error result information after the second stage fan-out check. When the error result information E2 is output, the layout editor displays the design window (design screen) X4 used for the layout design of the unit cells and another window X as in the case of the first stage.
3 is created and the error result information E2 is displayed and output there. The display mode is such that the advice information indicates the virtual wire correction guideline “Virtual Wire Length *** μm → *
It is the same as in the case of the first stage except that it becomes ** μm ”.
The same applies to the point where the corresponding portion is highlighted in the layout image on the design window X4 by instructing and operating the display button in the window X3. However, in this case, what is highlighted is a plurality of unit cells C1 to C3 connected by the corresponding virtual wiring and a line Y2 indicating the connection thereof. The error site display function is configured by the error site display function.

When there is a part determined to be an error in the fanout check in the second stage, the operator relies on the displayed error information to highlight the error part in the design window and Can be modified by changing the layout of (step S1)
8). After the correction, the procedure of performing a fan-out check again to see if a new error location has occurred is repeated, so that the unit-cell layout design without error is performed in the second-stage fan-out check. .

When the layout design of the unit cells is completed, the layout design of the actual wiring is then carried out on the layout editor (step S15). When the layouts of all the actual wirings are determined, the menu of the layout editor is selected to perform the fan-out check in the third stage (step S16).

In the fan-out check of the third stage, the input gate capacitance calculation formula T1 and the gate capacitance value T per unit area, which are input in advance in the layout editor, by the function modules provided in the layout editor.
2. Based on the wiring capacitance T3 per unit area, the fanout calculation formula T4 in the third stage, the netlist D1, the unit cell arrangement data D2, and the detailed wiring wiring data D3 obtained by the series of designs described above. , The fan-out value including the actual wiring is obtained for all the output parts of all the unit cells.

Next, an error judgment is made based on the error judgment formula T5 for the fan-out check in the third step, and the portion judged as an error is picked up. Specific examples of the calculation of the fan-out value and the error determination here are as shown in the description of FIG.

Further, in accordance with the above error determination, the length of the part which is determined to be an error is determined based on the conversion equation T6 by setting the number of microns of the actual wiring to avoid the error. Then, the error result information E3 including the information on the error location and the advice information indicating the length of the actual wiring for avoiding the error is output as a file.

FIG. 11 shows a display image example of error result information after the fan-out check in the third stage. When the error result information E3 is output, the layout editor displays the first
As in the case of the second stage, a window X5 different from the design window X6 as the design screen is created and the error result information E6 is displayed and output there. The display mode is
The advice information is about the length of the actual wiring, and is almost the same as that at the second stage. In addition, by operating the display button in the window X5,
The same applies to the point where the relevant portion is highlighted in the layout diagram on the design window X6. In this case, what is highlighted is the corresponding actual wiring and the plurality of unit cells C4 to C6 connected by this wiring. The function of displaying these error parts constitutes an error part display function.

When there is a part determined to be an error in the fanout check in the third stage, the operator relies on the displayed error information to highlight the error part in the design window and to check its wiring layout. Can be modified to modify the design (step S1
9). After the correction, the procedure of performing fan-out check again to see if a new error location has occurred is repeated to achieve a circuit design in which fan-out values are within the acceptable range at all locations. After that, for example, the layout verification of the design circuit is performed by a known diagnosis technique or simulation technique, and the circuit design is completed.

Table 1 shows a list of data input / output to / from the circuit editor and the layout editor in each processing of steps S11 to S19 of FIG.

[0066]

[Table 1]

In this table, the row of step S11 shows the data input / output to / from the circuit editor, and the other rows show the data input / output to the layout editor.

In the examples of FIGS. 9 to 11, as the advice information after the fan-out check, the virtual wiring length which is a guideline for the layout correction of each unit cell is presented in the second-stage fan-out check, and the third In the stage fan-out check, an example was shown in which the actual wiring length, which is a guideline for wiring layout correction, was presented. For example, in the fan-out check in the second and third stages, a guide for design correction in the previous stage You may make it display the advice information which becomes.

FIG. 12 shows an image diagram for explaining another example of the error result information obtained in the fan-out check in the third stage. For example, as shown in FIG. 12, in the fan-out check in the third stage (after the layout design of the actual wiring), the same error location is provided in addition to the correction value of the actual wiring length which is a guideline for correcting the wiring layout. In, present the correction value that will serve as a guide when correcting the driver size on the output side and the input pin capacitance on the receiving side,
It is also possible to display a message prompting the operator to avoid the fan-out error by modifying the wiring layout or the unit cell configuration.

As described above, according to the layout editor of this embodiment, before the layout design of the unit cell, after the layout design,
It is possible to perform fan-out check at each stage after wiring layout design and correct the fan-out error, so do these designs without causing a significant backtracking of the design flow. Therefore, the design period can be shortened. In addition, since the fan-out check is performed over the entire circuit at each stage, the design accuracy can be improved.

Further, when an error portion is found by the fan-out check, advice information serving as a guideline for correction is shown for each error portion. Therefore, the operator should rely on this advice information to carry out the correction process in a short time. Can be done. Furthermore, design windows X2, X4, X6
Since the error location can be displayed in the layout image in such a manner that it can be distinguished from other locations, the operator can save the trouble of finding the error location from the layout image and can easily perform the correction process.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the fan-out formula at each design stage is not limited to the formula of the embodiment, and the relationship between the output driving force of the unit cell to be calculated and the input load of another cell connected to the output side of the unit cell is shown. Various changes can be made as long as they are shown.

Although the gate width and the wiring length of the MOSFET are used as the fanout calculation parameters,
If more detailed fan-out verification is required, for example, contact holes h or MOSF for connecting wirings between layers may be used.
The fan-out calculation may be performed by including the load capacitance caused by the gate length of the ET, the load resistance of the circuit constituent elements and the wiring, and the like as parameters.

Further, as the virtual wiring used in the fan-out calculation performed in the layout design stage, the shortest wiring among the wirings along the X direction and the Y direction is illustrated, but the virtual wiring is not limited to this. For example, in the entire circuit, it is possible to first determine a rough route of wiring and make it the shortest route among the routes.

Further, in the above embodiment, the design data representing the design content is input to the design support system at each design stage. The fan-out verification routine according to the present invention may be incorporated to configure a design support system that comprehensively performs circuit design and fan-out verification.

In the above description, the case where the invention made by the present inventor is mainly applied to the design of a semiconductor memory which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and the analog circuit is used. It can be widely used for designing a semiconductor integrated circuit containing a.

[0077]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, from the circuit design to the wiring layout design can be performed while adjusting the driving force between the circuits and without making a large backtrack in the design flow. This has the effect of shortening the

Further, since the detailed cell library including the timing information used in the ASIC is not used for design support, there is an effect that the development cost of the cell library can be reduced.

Further, when an error point is found in the driving force judgment at each design stage, the advice information indicating the correction guideline is displayed and the error point can be displayed on the design screen in a distinguishable manner. The operator can easily perform the correction process.

[Brief description of drawings]

FIG. 1 is a functional configuration diagram illustrating a design support system according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a design flow of a semiconductor integrated circuit to which the design support system of the embodiment is applied.

FIG. 3 is a diagram illustrating an example of a fanout calculation method excluding wiring information, which is performed in step S2 of FIG. 2;

FIG. 4 is a diagram illustrating an example of a fanout calculation method using virtual wiring performed in step S4 of FIG.

5 is a diagram illustrating an example of a fanout calculation method for actual wiring, which is performed in step S6 of FIG.

FIG. 6 is a flowchart showing an example of a conventional general-purpose memory design flow.

FIG. 7 is a flowchart showing a processing procedure of circuit design performed using the layout editor of the embodiment.

FIG. 8 is a diagram illustrating a functional module that executes a fan-out check in the layout editor according to the embodiment.

FIG. 9 is an image diagram showing a display example of error result information obtained in the fan-out check in the first stage.

FIG. 10 is an image diagram showing a display example of error result information obtained in the fan-out check in the second stage.

FIG. 11 is an image diagram showing a display example of error result information obtained by the fan-out check in the third stage.

FIG. 12 is an image diagram illustrating another example of error result information obtained in the fan-out check in the third stage.

[Explanation of symbols]

2 data input function 3 fanout calculation function 4 fanout verification function 5 information output function 10 unit cells 11 to 13 to be operated other unit cells 20 connected to the output side 20 virtual wiring 30 actual wiring D1 netlist D2 placement data D3 Wiring data E1 to E3 Error result information S21 Fan-out calculation formula interpretation step S22 Fan-out calculation step S23 Fan-out error judgment formula interpretation step S24 Fan-out error judgment step S25 Fan-out error correction value calculation step S26 Fan-out error output step X1, X3, X5 Error output information display window X2 Circuit editor design window X4, X6 Layout editor design window

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/82 H01L 21/82 D CT (72) Inventor Tamotsu Sato Yuwa Kawabe-gun Akita Prefecture Aikawa No. 85 Incorporated company Akita Electronics Systems (72) Inventor Kazuhiro Miura 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Group (72) Hidenori Kitajima Kodaira, Tokyo 5-20-1 Kamimizuhonmachi Hitachi Ltd. Semiconductor Group (72) Inventor Kenji Nakata 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Super L.S.I.Systems Co., Ltd. Inner F term (reference) 5B046 AA08 BA03 BA04 HA04 HA09 JA03 5F064 BB12 BB28 DD02 DD03 DD04 DD09 DD24 DD32 EE03 EE08 EE43 EE57 HH06 HH10 HH12 HH15 HH17

Claims (10)

[Claims] 1. A design support system for a semiconductor integrated circuit for supporting the design of a semiconductor integrated circuit having an analog circuit built therein, which is a constituent element of the integrated circuit at a stage of circuit design excluding wiring information. Each unit cell is connected to the output side based on the circuit information including at least the output driving force and the input load showing the contents of each unit cell unitized for each function and the connection information of each unit cell. At the stage of the layout design of the unit cell, a first calculation means for calculating an index relating to the driving force of the unit cell with respect to another circuit, and a virtual wiring connecting the unit cells for which the layout is designed is generated. At the stage of the layout design of the wiring connecting the unit cells and the second computing means for computing the index relating to the driving force including the influence of the virtual wiring, the layout design And a third calculation means for calculating an index relating to the driving force, which includes the influence of the generated wiring, and a semiconductor integrated circuit design support system. 2. When the index value does not satisfy a predetermined condition as a result of the calculation by the first calculating device, the second calculating device, or the third calculating device, an error output for outputting a portion that does not satisfy the condition to the outside. The design support system for a semiconductor integrated circuit according to claim 1, further comprising means. 3. The semiconductor integrated circuit comprises a DRAM, SR
3. The semiconductor integrated circuit design support system according to claim 1, which is a semiconductor memory such as an AM or a flash ROM. 4. A method for designing a semiconductor integrated circuit, from the design of an integrated circuit containing an analog circuit to the formation of the circuit, wherein the integrated circuit is a constituent element of the integrated circuit and has a predetermined function before the wiring layout design. Based on the circuit information including at least the output driving force and the input load indicating the content of each unit cell unitized in, and the connection information of each unit cell, other unit cells connected to the output side are connected to each other. A method of designing a semiconductor integrated circuit, comprising: calculating an index relating to the driving force of the unit cell for a circuit, and designing and modifying the integrated circuit so that the index value satisfies a predetermined condition. 5. A method for designing a semiconductor integrated circuit including an analog circuit, comprising: circuit design excluding wiring information; layout design of unit cells that are constituent elements of the integrated circuit and are unitized for each predetermined function. , And at each design stage of the wiring layout design, the above-mentioned index is calculated using the design support system according to any one of claims 1 to 3, and the index value at any design stage satisfies a predetermined condition. If not, the semiconductor integrated circuit design method is characterized in that the design is modified in the design stage until the condition is satisfied, and the condition is changed to the next design stage. 6. Editing according to an input while displaying an image of a layout of each unit cell, which is a constituent element of an integrated circuit and unitized for each predetermined function, and a wiring layout between each unit cell, on a design screen. A layout editor for performing a driving force determination function for determining whether a predetermined condition is satisfied by calculating an index representing the magnitude of the driving force of the output terminal with respect to the load connected to the output terminal of the unit cell; When it is determined that the conditions are not met by the driving force determination function, the display function that distinguishes the parts that do not meet the conditions from the other parts on the design screen, and the parts that do not meet the conditions are described above in advance. A layout editor having a guide function for displaying and outputting advice information for prompting a change in wiring length so as to satisfy a predetermined condition. 7. A first calculation function for calculating a wiring length that satisfies a condition for a portion that does not satisfy the condition, wherein the advice information includes the wiring length calculated by the first calculation function. The layout editor according to claim 6. 8. The display function includes displaying and outputting advice information for changing an output driving force or an input load of a unit cell so that a portion that does not satisfy the above condition is satisfied with the predetermined condition. The layout editor according to claim 6, wherein the layout editor is a layout editor. 9. A second calculation function for calculating a value of an output driving force or an input load of a unit cell that satisfies a condition that does not satisfy the condition is provided, and the advice information is calculated by the second calculation function. 9. The layout editor according to claim 8, wherein the layout editor includes a value that is set. 10. A virtual wiring function for automatically generating a layout of virtual wiring connecting between unit cells according to a predetermined condition, wherein the drive is performed after the layout design of each unit cell and before the design of the wiring layout. The force determination function makes a determination on the index calculated including the wiring load of the virtual wiring, and the guide function displays and outputs advice information about the virtual wiring, and after the wiring layout is designed, the driving force determination is made. 10. The function according to claim 6, wherein the index is calculated including the wiring load of the designed real wiring, and the guide function displays and outputs advice information about the real wiring. Layout editor described in Crab.