JP2003070263A - Three-level inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance conversion efficiency and operation stability by controlling the resonance current of the DC bus of a three-level inverter device. SOLUTION: This device controls a resonance current going through a middle potential bus by interposing resonance control resistors 6a-6d in the middle potential bus C between the DC neutral point potential terminal and the DC link part of a multiphase inverter. This can arrange the resonance frequency of the DC link part not to accord with the switching frequency of a PWM by interposing reactors 7a and 7b for resonance control at least either between the DC positive potential terminal of the multiphase inverter and the DC positive potential bus, or between the DC negative potential terminal of the above multiphase inverter and the DC negative potential bus, thereby setting the resonance frequency properly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power conversion device for obtaining electric power of a variable frequency, and more particularly to a three-level inverter device which suppresses a resonance phenomenon in a DC bus and operates the device stably.

[0002]

2. Description of the Related Art An inverter device is applied as a power converter for driving a drive of an AC motor, and a three-level inverter device is used especially for large capacity applications. In general, an inverter device is configured by connecting a converter that converts the power of an AC power source to DC and an inverter that converts DC to AC by a DC bus.

Therefore, in an inverter device having a smoothing capacitor in each of the DC part of the converter and the DC part of the inverter, a resonance phenomenon occurs due to the inductance components of the smoothing capacitor and the DC bus of both, and the DC current and the smoothing capacitor are caused by the resonance current. There was a problem that the temperature rose.

As a method for solving this problem, Japanese Unexamined Patent Publication No.
There is a 3-level inverter (Prior Art 1) described in No. 1-18435. According to the present invention, PWM control is performed in the converter and the inverter, and each PWM switching frequency is set to 1 / n of the primary resonance frequency of the DC link unit.
Setting √2 or less prevents the resonance current from increasing.

Further, the inverter device described in Japanese Patent Laid-Open No. 11-46481 (Prior Art 2) is a parallel multiplex inverter device in which a plurality of three-level inverters are connected by a DC circuit. A damping resistor is inserted in the bus bar to suppress the resonance current.

[0006]

However, in a large-capacity inverter device, the capacitance of the smoothing capacitor becomes large, and the size of the device becomes large, so that the inductance of the DC bus also becomes large and the resonance frequency in the DC bus becomes large. Get lower.

Therefore, as in the above-mentioned prior art 1, the PW
When the M switching frequency is set to be equal to or lower than the resonance frequency 1 / √2, there is a problem that the waveform distortion of the output voltage of the inverter becomes large due to the low switching frequency and the desired performance cannot be obtained due to large vibration of the load motor. .

Further, in the DC bus between the converter and the inverter, a DC current corresponding to the power to be converted flows. Therefore, if a resistor is inserted in the positive bus and the negative bus as in the prior art 2, it is generated by the DC current. There is a problem that the loss is large and the conversion efficiency of the inverter device is reduced.

An object of the present invention is to provide a three-level inverter device which suppresses the resonance current in the DC bus without lowering the conversion efficiency and can obtain a highly efficient and stable operation.

[0010]

One feature of the present invention is to insert a resonance suppressing resistor between a DC intermediate potential terminal and a DC intermediate potential bus of a multi-phase inverter having a smoothing capacitor. Since a current corresponding to the difference between the positive bus current and the negative bus current flows through the DC intermediate potential bus, the currents other than the resonance current are small and the loss due to the insertion of the resistor is small.

Further, according to the present invention, at least one of a DC positive potential terminal and a DC positive potential bus of a multi-phase inverter having a smoothing capacitor and at least one of a DC negative potential terminal and a DC negative potential bus of the multi-phase inverter is provided. The inductance is inserted and the resonance frequency between the smoothing capacitor of the inverter unit and the DC bus is appropriately set so that the resonance frequency does not match the PWM switching frequency.

Further, in the present invention, a resonance suppressing resistor is inserted between the DC intermediate potential terminal and the DC intermediate potential bus of the single-phase inverter unit having the smoothing capacitor, and in addition to the resonance current between the multi-phase inverters, It also suppresses the resonance current between the single-phase inverter units.

Further, according to the present invention, an inductance is inserted between at least one of the DC positive potential terminal and the DC positive potential bus of the single-phase inverter unit and between the DC negative potential terminal and the DC negative potential bus of the single-phase inverter unit. However, PWM is set by appropriately setting the resonance frequency between the multi-phase inverters and the resonance frequency between the single-phase inverter units.
Do not match the switching frequency of.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 2 is a schematic diagram showing a three-level inverter device using the present invention. A three-level converter 1a converts AC power supplied from a power transformer 2 into DC power. And is supplied to the DC link unit 3.

The three-level inverters 1b to 1d convert the electric power of the DC link unit 3 into AC. The AC output terminal of the three-level inverter 1b is connected to the electric motor 4b. The three-level inverters 1c and 1d are configured to be operated in parallel, and both AC output terminal sides are connected to the common electric motor 4c.

The three-level converter 1a and the three-level inverters 1b to 1d have the same structure, and the smoothing capacitors 41a to 41d are connected between the positive potential DC terminal and the intermediate potential DC terminal and between the intermediate potential DC terminal and the negative potential DC terminal, respectively.
41d and 42a to 42d. In the DC link unit 3,
A positive potential bus P, an intermediate potential bus C, and a negative potential bus N are provided.

The positive potential bus P has a wiring inductance 51a.
~ 51c, the intermediate potential bus C, wiring inductance 52a ~ 52
The c and negative potential buses N have wiring inductances 53a to 53c, respectively. Resonance suppressing resistors 6a to 6d are respectively interposed between the DC neutral point terminals Tna to Tnd of the three-level converter 1a and the three-level inverters 1b to 1d and the intermediate potential bus C of the DC link section.

The operation of the resonance suppressing resistors 6a to 6c will be described with reference to FIG. FIG. 3 shows the three-level converter 1a of FIG.
FIG. 4 is an explanatory diagram showing a resonance path in a portion including only the three-level inverter 1b and the DC link unit 3;

There are two resonance paths X and Y in the resonance path. The resonance path X includes the smoothing capacitor 41a, the wiring inductance 51a, the smoothing capacitor 41b, the resonance suppressing resistor 6b, the wiring inductance 52a, and the resonance suppressing resistor 6a.
It is a route that goes around. The resonance path Y is the smoothing capacitor 4
1a, wiring inductance 51a, smoothing capacitor 41
b, 42b, the wiring inductance 53a, and the smoothing capacitor 42a.

Smoothing capacitors 41a, 41b, 42a,
When the capacitance of each of 42b is C, the wiring inductances 51a to 53a of the DC bus are Lb, and the resistance values of the resonance suppressing resistors 6a and 6b are Rc, respectively, the resonance angular frequency ωx of the resonance path X and the resonance path Y are shown. The resonance angular frequency ωy of can be expressed by the following equations (1) and (2), respectively.

[0021]

[Equation 1]

[Equation 2] As is clear from FIG. 3, the resonance suppression resistors 6a and 6b have an effect of suppressing the current in the resonance path X. In a normal inverter device, the resistance value suitable for the resonance suppressing resistors 6a and 6b is several Ω to several tens Ω.

FIG. 4 is a graph showing the resonance characteristic of the DC link unit 3. The solid line shows the case where the resonance suppression resistors 6a and 6b are provided, and the broken line shows the case where they are not provided. By interposing the resonance suppression resistors 6a and 6b,
Since the current on the resonance path X can be suppressed, the resonance current near the resonance angular frequency ωx can be reduced.

In the three-level inverter device, only the current component for adjusting the balance between the DC positive voltage and the DC negative voltage of the DC link section 3 flows through the intermediate potential bus C. Therefore, the increase in loss due to the insertion of the resonance suppression resistors 6a and 6b is slight.

3 and 4 show a three-level converter 1a.
Although the resonance path between the 3-level inverter 1b and the 3-level inverter 1b has been described, the other 3-level inverters 1c and 1d are described.
In consideration of the above, it is necessary to consider the resonance paths of the four three-level converters and the three-level inverters, but the effect of suppressing resonance in each is the same.

In the present embodiment, even when the PWM switching frequency of the three-level converter 1 or the three-level inverter 2 becomes a value close to ωx, it is possible to prevent the resonance current in the DC link section from increasing, so that the smoothing capacitor and There is an effect that the loss generated in the DC bus can be reduced and a highly efficient and stable operation can be obtained.

(Embodiment 2) FIG. 1 is a diagram showing a second three-level inverter device using the present invention. The difference from FIG. 2 is that the resonance suppression reactor 71a is provided between the DC positive potential terminals of the three-level converter 1a and the three-level inverters 1b to 1d and the positive potential bus P of the DC link unit, respectively.
To 71, and resonance suppressing reactors 72a to 72d are respectively interposed between the DC negative potential terminals of the three-level converter 1a and the three-level inverters 1b to 1d and the negative potential bus N of the DC link unit. It is a point.

The operation of the resonance suppressing resistors 6a to 6c and the resonance suppressing reactors 71a to 72c will be described with reference to FIG. FIG. 5 is an explanatory diagram showing a resonance path in only the three-level converter 1a, the three-level inverter 1b, and the DC link unit 3 in FIG.

There are two resonance paths X and Y in the resonance path. The resonance path X includes the smoothing capacitor 41a, the resonance suppressing reactor 71a, the wiring inductance 51a, the resonance suppressing reactor 71b, the smoothing capacitor 41b, the resonance suppressing resistor 6b, the wiring inductance 52a, and the resonance suppressing resistor 6.
It is a route that goes around a.

The resonance path Y includes a smoothing capacitor 41a, a resonance suppressing reactor 71a, a wiring inductance 51a, a resonance suppressing reactor 71b, and smoothing capacitors 41b and 42.
b, resonance suppression reactor 72b, wiring inductance 5
3a, resonance suppression reactor 72a, smoothing capacitor 42
It is a route that goes around a.

Smoothing capacitors 41a, 41b, 42a,
Let C be the capacitance of 42b, Lb be the DC bus wiring inductances 51a to 53a, Rc be the resistance values of the resonance suppression resistors 6a and 6b, and Lc be the resonance suppression reactors 71a to 72b. The resonance angular frequency ωx of the path X and the resonance angular frequency ωy of the resonance path Y can be expressed by the following expressions (3) and (4), respectively.

[0031]

[Equation 3]

[Equation 4] FIG. 6 is a graph showing the resonance characteristic of the DC link unit 3.
The solid line shows the case where the resonance suppression resistors 6a and 6b and the resonance suppression reactors 71a to 72b are installed, and the broken line shows the case where they are not installed.

By interposing the resonance suppressing resistors 6a and 6b, the current in the resonance path X can be suppressed, so that the resonance current in the vicinity of the resonance angular frequency ωx can be reduced.
Further, the resonance angular frequency ωy of the resonance path Y can be reduced by interposing the resonance suppression reactors 71a to 72b. Since the resonance angular frequency ωy can be arbitrarily set by the resonance suppression reactors 7a and 7b, by setting it so as not to match the PWM switching frequency of the three-level converter 1 or the three-level inverter 2,
Make sure that the resonance current in the DC link does not increase.

In the three-level inverter device, only the current component for adjusting the balance between the DC positive voltage and the DC negative voltage of the DC link section 3 flows through the intermediate potential bus C. Therefore, the increase in loss due to the insertion of the resonance suppression resistors 6a and 6b is slight.

5 and 6 show a three-level converter 1a.
Although the resonance path between the 3-level inverter 1b and the 3-level inverter 1b has been described, the other 3-level inverters 1c and 1d are described.
In consideration of the above, it is necessary to consider the resonance paths of the four three-level converters and the three-level inverters, but the effect of suppressing resonance in each is the same.

In the above-described embodiment, the resonance frequency ωy of the resonance path X of the DC link portion is suppressed and the resonance frequency ωy of the resonance path Y is arbitrarily set to obtain the resonance frequency ωy.
Is prevented from matching the PWM switching frequency of the three-level converter 1 or the three-level inverter 2 and the resonance current in the DC link section can be prevented from increasing, so that the loss generated in the smoothing capacitor and the DC bus can be reduced, There is an effect that stable operation can be obtained with efficiency.

(Third Embodiment) FIG. 7 is a diagram showing a third three-level inverter device using the present invention. In FIG. 7, reference numeral 1a is a three-level converter, which converts the AC power supplied from the power transformer 2 into DC power. Supply to the DC link unit 3. The three-level inverters 1b and 1c for converting direct current into alternating current have the direct current link unit 3 respectively.
DC power of the above is converted into AC power and supplied to the electric motors 4b and 4c.

The DC link unit 3 is provided with a positive potential bus P, an intermediate potential bus C, and a negative potential bus N, and a positive potential bus P
Has wiring inductances 51a to 51c, intermediate potential bus bar C has wiring inductances 52a to 52c, and negative potential bus bar N has wiring inductances 53a to 53c.

The three-level converter 1a and the three-level inverters 1b and 1c have the same structure, and each has three single-phase inverter units 11a to 13a and 11b.
.About.13b, 11c to 13c. The single-phase inverter units 11a to 13c have the same structure as each other, and have positive side smoothing capacitors 41a to 43c and negative side smoothing capacitors 44a to 46c, respectively. Further, in the single-phase inverter units 11a to 13c, resonance suppression resistors 61a to 63c are respectively interposed between the DC neutral point terminal and the interconnection point of the two smoothing capacitors.

The operation of the resonance suppressing resistors 61a to 63c is similar to that of the resonance suppressing resistors 6a to 6d in the first embodiment of the present invention, and is performed between the 3-level converter 1a, the 3-level inverter 1b and the 3-level inverter 1c. Suppress resonance current.

Further, the resonance suppressing resistors 61a to 63a are the single-phase inverter unit 11a in the three-level converter 1a.
The resonance current between 13a to 13a is also suppressed. Similarly, the resonance suppression resistors 61b to 63b also suppress the resonance current between the single-phase inverter units 11b to 13b in the three-level inverter 1b, and the resonance suppression resistors 61c to 63c each include the single-phase inverter unit 11c in the three-level inverter 1b. The resonance current between 13c is also suppressed.

In FIG. 7, the resonance suppressing resistor is mounted in each single-phase inverter unit, but the effect is not changed even if the resonance suppressing resistor is mounted in the connecting portion outside the unit.

Similar to the second embodiment, the same effect can be obtained by interposing the resonance suppression reactor at the DC positive potential terminal or the DC negative potential terminal of each single-phase inverter unit.

In this embodiment, in a plurality of multi-phase inverters composed of a single-phase inverter unit having a smoothing capacitor, the resonance current of the DC link portion between the multi-phase inverters is suppressed, and the single-phase inverters in the multi-phase inverters are suppressed. Since the resonance current between the phase inverter units can also be suppressed, the loss generated in the smoothing capacitor and the DC bus can be reduced, and highly efficient and stable operation can be obtained.

[0044]

As described above, according to the present invention, the loss generated in the smoothing capacitor and the DC bus can be reduced, the temperature rise can be prevented, and highly efficient and stable operation can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a second embodiment of the present invention.

FIG. 2 is a configuration diagram of the first embodiment of the present invention.

FIG. 3 is a diagram showing an equivalent circuit showing a resonance path in the first embodiment.

FIG. 4 is a diagram showing resonance characteristics.

FIG. 5 is an equivalent circuit showing a resonance path in the second embodiment.

FIG. 6 is a diagram showing resonance characteristics.

FIG. 7 is a diagram showing a configuration diagram of a third embodiment.

[Explanation of symbols]

1a ... 3-level converter, 1b-1d ... 3-level inverter, 3 ... DC link part, 41a-46d ... Smoothing capacitor, 51a-53c ... Wiring inductance, 6a-
6d, 61a to 63c ... Resonance suppressing resistors, 71a to 72
d ... Resonance suppressing reactor.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5H006 AA01 AA06 BB05 BB06 CA01                       CA07 CA12 CA13 CB01 CC02                       CC05 CC08                 5H007 AA01 AA08 AA17 BB06 BB11                       CB05 CC01 CC04 CC05 CC06                       CC23 FA01 FA03 FA12 FA13

Claims (4)

[Claims] 1. A direct current link unit comprising a positive potential bus, a negative potential bus and an intermediate potential bus, a positive potential DC input terminal and a negative potential DC input respectively connected to the positive potential bus, the negative potential bus and the intermediate potential bus. Terminals, an intermediate potential DC input terminal, an AC output terminal, and a plurality of multi-phase inverters having smoothing capacitors between the positive potential DC input terminal and the intermediate potential DC terminal and between the intermediate potential DC input terminal and the negative potential DC terminal, respectively. A three-level inverter device comprising: a multi-phase inverter, wherein a resistor is interposed between the intermediate-potential DC terminal of the multiphase inverter and the intermediate-potential bus bar of the DC link unit. 2. A direct current link unit comprising a positive potential bus, a negative potential bus and an intermediate potential bus, and a positive potential DC input terminal and a negative potential DC input respectively connected to the positive potential bus, the negative potential bus and the intermediate potential bus. Terminals, an intermediate potential DC input terminal, an AC output terminal, and a plurality of multi-phase inverters having smoothing capacitors between the positive potential DC input terminal and the intermediate potential DC terminal and between the intermediate potential DC input terminal and the negative potential DC terminal, respectively. In a three-level inverter device including: a three-level inverter device, wherein an inductance is provided between a DC input terminal of the multi-phase inverter and a bus bar of the DC link unit. 3. A direct current link unit comprising a positive potential bus, a negative potential bus and an intermediate potential bus, and a positive potential DC input terminal and a negative potential DC input respectively connected to the positive potential bus, the negative potential bus and the intermediate potential bus. Terminals, an intermediate potential DC input terminal, an AC output terminal, and a plurality of single-phase inverters having smoothing capacitors between the positive potential DC input terminal and the intermediate potential DC terminal and between the intermediate potential DC input terminal and the negative potential DC terminal, respectively. A three-level inverter device including a unit, wherein a resistor is provided between the intermediate-potential DC terminal of the single-phase inverter unit and the intermediate-potential bus bar of the DC link section. 4. A direct current link unit comprising a positive potential bus, a negative potential bus and an intermediate potential bus, a positive potential DC input terminal and a negative potential DC input respectively connected to the positive potential bus, the negative potential bus and the intermediate potential bus. Terminals, an intermediate potential DC input terminal, an AC output terminal, and a plurality of single-phase inverters having smoothing capacitors between the positive potential DC input terminal and the intermediate potential DC terminal and between the intermediate potential DC input terminal and the negative potential DC terminal, respectively. A three-level inverter device including a unit, wherein an inductance is provided between a DC terminal of the single-phase inverter unit and a bus bar of the DC link unit.