JP2003069656A - Terminal device, base station device, repeater and communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform efficient radio transmission by reducing an influence on error of configuration data and adaptively changing the operation precision. SOLUTION: Signal processing circuits 23a-1 to 23a-4 are constituted of residue number arithmetic circuits corresponding to respective moduli of a modulus set 3, 5, 7 and 11} and realize the processing for digital radio communication. Conversion circuits 23b-1 to 23b-4 convert outputs of residue digit arithmetic circuits of modulus sets 3, 5 and 7}, 3, 5 and 11}, and 3, 7, 11}, and 5, 7 and 11} to a binary system. The conversion results are compared with a non- redundant dynamic range by comparison circuits 23c-1 to 23c-4. The results smaller than the non-redundant dynamic range are selectively outputted by a decoder 23d and a multiplexer 23e. When all the modulus sets are larger than the non-redundant dynamic range, the decoder 23d outputs a retransmission request signal to a base station.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal device, a base station device, a relay device and a communication method based on software defined radio technology.

[0002]

2. Description of the Related Art Recently, software defined radio is being developed. Software defined radio is a concept of a system in which basic radio functions (bandwidth, filtering, modulation / demodulation, coding, etc.) can be changed by software. As features of software defined radio, reconfigurability (ability to change configuration / spec) and downloadability (ability to rewrite program) can be mentioned. A radio defined by software defined radio technology is called a software defined radio.

More specifically, in software radio communication technology, a microprocessor and a DSP (Digital Signal) are used.
Processor) chip or FPGA (Field Programmabl)
e Gate Array) to configure a programmable modulator / demodulator for digital wireless communication, and download software for configuring the modulator / demodulator of the desired communication method to the modulator / demodulator by wire or wirelessly, and use the same specifications. It can be flexibly realized by hardware.

If, for example, different wireless communication systems such as PHS (Personal Handyphone System), mobile phone, and local area network (LAN) can be realized by one wireless communication device by downloading software, users are the same. If you have a wireless terminal device, you can get the service all over the world by downloading the program of the communication system of the area. For terminal device manufacturers, mass production is possible by using common hardware, and manufacturing costs can be reduced.

Further, since the function of the wireless communication device can be easily updated, it is easy for the communication carrier to add a new service, upgrade the function, change the system, correct a software mistake, and the like. Furthermore, by downloading the software via radio, you can flexibly set the bit rate, modulation / demodulation method, error correction coding / decoding method, etc. according to the propagation environment, and provide the optimum transmission quality for the propagation environment and subscribers. Allows the number to be improved.

FIG. 1 shows an example of a conventional software defined radio device. The signal of the center frequency fc received from the antenna 1a passes through the antenna switch 1b and is input to the low noise amplifier 1j. The signal output from the low noise amplifier is mixed with the oscillation frequency f11 of the first local oscillator 1c in the reception mixer 1k and converted into a signal of the intermediate frequency fi.

The signal converted to the intermediate frequency fi is quadrature-detected by the quadrature detector 11 with the intermediate frequency f12 of the second local oscillator 1d and converted into analog baseband signals I and Q. Analog baseband signal I, Q
Are converted into digital baseband signals ID and Q-D in the A / D converter 1m. The digital baseband signals ID and Q-D are supplied to the demultiplexer 1p.

The demultiplexer 1p selects a software transmission packet or an information data transmission packet. A / when downloading software
The output data ID and Q-D of the D converter are demodulated by the software modulation signal demodulation unit 1o. Baseband digital modulator 1i in which the demodulated program is programmable
Alternatively, it is downloaded to the programmable baseband digital demodulation unit 1n. After downloading, the demultiplexer 1p displays the output data ID and Q of the A / D converter.
-D is supplied to the programmable baseband digital demodulation unit 1n, and the desired demodulation processing determined by the program is performed.

The programmable baseband digital modulation unit 1i and the programmable baseband digital demodulation unit 1n are, as an example, a program from the software modulation signal demodulation unit 1o.
Ogonal frequency division multiplexing) function and W-CDM
This is to switch the modulation and demodulation functions of the A (Wideband-CDMA: wideband code division multiple access) system. This modulation / demodulation system is an example of a multi-mode radio,
This invention is based on GSM (Global System for Mobile Commun
ication: European digital car / mobile phone system) may be realized by a program. Furthermore, the present invention is applicable not only to mobile communication but also to different systems in wireless LAN, different systems in ITS (Intelligent Transport System).

When transmitting the software to be downloaded to the partner station, the software stored in the software memory 1q is modulated by the software modulator 1r, and the digital IQ signals I-D and Q-D passed through the multiplexer 1s. It is input to the D / A converter 1h. D
The / A converter 1h converts the digital IQ signal into an analog signal. When transmitting the information bits, the modulated data bits are modulated by the programmable baseband digital modulator 1i in a desired modulation scheme. Modulator 1i
The output of is passed through the multiplexer 1s and is input to the D / A converter 1h as digital baseband signals I-D and Q-D. The software memory 1q and the software modulator 1r may be included in not only the base station but also the terminal station.

In the quadrature modulator 1g, the analog signal is quadrature-modulated by the oscillation frequency f12 of the second local oscillator (1d) and converted into a signal having an intermediate frequency fi (= f12). The signal modulated to the intermediate frequency fi is transmitted to the transmission mixer 1
At f, the signal is converted into a signal of frequency fc (= f12 + f11) by the frequency f11 of the first local oscillator 1c.

The OFDM modulated signal converted to the frequency fc is amplified to a predetermined transmission power in the power amplifier 1e. The amplified signal is supplied to the antenna 1a via the antenna switch 1b and transmitted. MMAC
(Mu1timedia mobi1e accesscommunication system) and W
In mobile radio communication using a wide band spectrum such as CDMA (Wideband code division mu1tip1e access), the sampling frequency of the A / D converter 1m and the D / A converter 1h is several tens of MSPS (Mega samples per se).
cond).

FIG. 2 shows a configuration example of a packet of a link for wirelessly downloading software for a software defined radio system, and a configuration example of a packet of a link for transmitting information data. This link is the downlink from the base station to the terminal station. The packets are packets 2a-1, 2a-2, ..., 2a- that transmit software.
information packets 2b-1, 2b for transmitting k and information data
-2, ..., 2b-n.

The software packet has a preamble 2
c and software 2d. The software 2d uses the CRC (Cyc1i) added for error detection.
The data 2e for c redundancy check) and the configuration data 2f for reconfiguring a program or FPGA to be input to the microprocessor (or DSP). The information packet includes a preamble 2g and information symbols 2h-1, 2h-2, ...
It is composed of 2h-m.

A preamble that is a known signal is detected for the received data, and packet timing synchronization, frequency synchronization, and transmission line equalization are performed based on the detection. For the received software, CRC is used for error detection.
When an error is detected, the packet is discarded and a resend is requested. Only when no error is detected, the program is demodulated and the ACK signal (acknowledge signal) is transmitted to prompt the transmission of the next packet. When all the programs are demodulated, the demodulated programs are downloaded to the baseband digital signal modulator 1i and the demodulator 1n, and the desired modulation / demodulation method is set. After receiving the information packet and performing packet timing synchronization, frequency synchronization, and transmission path equalization on the preamble 2g, the information packet is set for the information symbols 2h-1, 2h-2, ..., 2h-m. The information data is demodulated by the demodulation method.

FIG. 3 shows an example of the structure of a link (uplink) packet transmitted from a terminal station to a base station by a modulation unit in which software is downloaded in a software defined radio system. Packet 3a-
, 3a-n are composed of a preamble 3b, which is a known signal, and information data 3c. The information data 3c includes information symbols 3d-1, 3d-2, ...
-It is composed of 3d-m. On the receiving side, packet timing synchronization, frequency synchronization, and transmission line equalization are performed based on the detection of the preamble, and then the information symbols are demodulated.

FIG. 4 shows an example of packet retransmission processing of the software defined radio system. In the software defined radio system, the modulation and demodulation of the information data that should be originally transmitted is performed by the modulation and demodulation unit where the software is downloaded. There is a possibility that a failure occurs in the modulation / demodulation unit due to the software error generated by the wireless transmission path.
Therefore, the error detection by the CRC is performed on the wireless transmission packet of the software, and the retransmitting process is repeatedly performed until the error is not detected. However, CRC
Even if the error is not detected by, the bit error is not zero, and the bit error rate is extremely low, but the bit error may exist.

For example, the first software packet 1 (4a) is transmitted from the software transmission station. Error detection by CRC is performed on the received packet, and when an error is detected, the retransmission request signal (4b) is transmitted to the transmitting station until no error is detected. Figure 4
This is an example in which an error is not detected in software packet 1 (4e) transmitted after requesting retransmission twice, so the same packet (4a, 4c, 4e) is retransmitted three times. ACK after no error is detected
The signal (4f) is transmitted to the software transmission side.

After repeating these operations, the final software packet k (4k) is received, and the demodulation of all software is completed. The decrypted software is downloaded to the programmable modulation / demodulation unit, and desired modulation / demodulation processing becomes possible. Final software packet k (4
Information packet (4m, 4n, ..., 4o) is transmitted after transmitting ACK signal (4l) for k).

Next, the processing contents of the programmable baseband digital demodulation unit 1n shown in FIG. 1 will be described.
Generally, the processing of the demodulation unit is more complicated than that of the modulation unit,
Only the demodulation unit will be described. As an example, MMAC, which is a mobile radio communication system using a wide band spectrum
The configuration of the WCDMA demodulator will be described.

FIG. 5 shows a configuration example of the OFDM demodulation unit for MMAC. Input digital baseband signal I
-D and Q-D are the packet timing synchronization unit 5a.
After the packet timing synchronization is obtained at, the carrier frequency synchronizer 5b synchronizes the carrier frequency, and the memory 5c
After writing the data in FFT (fast Fouriertr
Ansform) 5d performs conversion into the frequency domain. If the number of subcarriers is NFFT, in FFT5d,
Fast Fourier transform of the NFFT points is performed and demodulated into parallel reception data of the NFFT points. After that, the equalizer 5e performs transmission path equalization, and the error correction code decoder 5f
The error bits are corrected by and output as demodulated bits.

FIG. 6 shows a configuration example of a spread spectrum demodulation unit for WCDMA. The input digital baseband signals I-D and Q-D are first subjected to packet timing synchronization by the packet timing synchronization unit 6a and then synchronized with the carrier frequency by the carrier frequency synchronization unit 6b. After writing the data in the memory 6c, the despreading / equalization unit 6d performs despreading and transmission line equalization using a predetermined spreading code. The output of the despreading / equalization unit 6d is supplied to the error correction code decoder 6e, the error bit is corrected by the decoder 6e, and the demodulated bit is output.

In the demodulation section as shown in FIGS. 5 and 6, the sampling data input at the rate of several tens MSPS is processed in real time by FFT, despreading, equalizer, etc. There is a need to do. In a software defined radio system, these processes are realized by programmable hardware. It is also conceivable to use an ultrahigh-speed general-purpose microprocessor that operates at a clock of several hundred MHz as a programmable device. However, since the power consumption depends on the clock frequency, it is difficult to design a practical portable information terminal device that operates on a battery.

FPGA as a programmable device
By using, it is possible to realize signal processing hardware for demodulation with relatively low power consumption and high speed. 100
Since large-scale FPGAs with over 10,000 gates are also on the market, OFDM for MMAC with over 1.4 million gates
The functions of the LSI can be fully realized by using several FPGAs. However, in order to program the FPGA to a desired function, the configuration data for programming the function of the reconfigurable logic circuit inside the FPGA, the wiring between the logic circuits, and the like are required. In order to program the above-mentioned MLSI OFDM LSI, configuration data of 8 Mbits is required.

An adder, a multiplier, and an arbitrary 2-input arithmetic circuit designed by using the FPGA block will be described below. In order to simplify the description, the contents of an LUT (Look Up Table) and a programmable logic circuit dedicated to carry generation, C, unless otherwise specified, will be described below.
CL setting data for setting L (Carry Logic) will be referred to as configuration data. The CL can realize one of several logical circuits defined in advance by the corresponding configuration data.

FIG. 7 shows a configuration example of a 9-bit adder designed by LUT and CL of FPGA. It is a ripple carry type adder in which a carry signal propagates from the lower bit. Bits a8-a0 and b8-b0 of the input data bus expressed in 2's complement are firstly LUTs 9a-1, 9a-2, 9 of the first stage.
a-3, 9a-4, 9a-5, 9a-6, 9a-7, 9
a-8, 9a-9, 9a-10. LUT9
a-1 generates a control signal indicating that an overflow has occurred. The other LUTs calculate the sum of the data of two bits having the same weight and the carry signal from the lower bit.

CL (9b-1, 9b-2, 9b-3, 9
b-4, 9b-5, 9b-6) generate a carry signal in each corresponding bit of the input data bus and propagate the carry signal from the lower bit to the upper bit. LUT (9c-1, 9c-2, 9c-3, 9c-4, 9 in the final stage
In c-5, 9c-6, 9c-7, 9c-8), the code processing corresponding to the two's complement representation for the sum output and the saturation processing at the time of overflow are performed. Other than this example, various adder algorithms have been proposed.

FIG. 8 shows an example of the configuration of a 3.2-bit multiplier designed by using the FPGA LUT and CL. Input data a2, a1, a0 and b1, which are represented by the two's complement,
b0 is the corresponding LUT (10a-1, 10a).
-2, 10a-3), LUT (10a-5, 10a-
6) and CL (10b-1, 10b-2, 10b-
It is converted to an absolute value by 3). LUT (10a-
The sign of the product is determined by 4). Each bit a'2, a'1, a0 'and b'1, b'0 of the absolute value is LUT (10c
-1, 10c-2, ..., 10c-6),
LUT (10c-1, 10c-2, ..., 10c-
According to 6), the partial product is calculated. Partial product is LUT
(10d-1, 10d-2, 10d-3), CL (10
e-1, 10e-2), LUT (10f-1, 10f-
2, ..., 10f-5) and CL (10g-1, 1)
0g-2,10g-3,10g-4) are added by the addition tree constructed from the bit _{P 4, P 3, P 2} , P 1, the product made of is calculated.

An arbitrary 2-input arithmetic circuit is designed by the LUT. Table 1 shows 2 inputs with a data word length of 12 bits 1
The example of the truth table of an output arithmetic circuit is shown.

[0030]

[Table 1]

FIG. 9 shows an example of the configuration of an arithmetic circuit designed by the LUT based on this truth table. Since the total number of bits of input data is 24 bits, it can be realized by preparing 12 logic circuits with 24 inputs and 1 output. Output bits c11 (MSB), c10, ..., c0 (LSB)
Is calculated by the logic circuit (11 ₁₁ , 11 ₁₀ , ..., 11 ₀ ). Each logic circuit has eight LUTs (11a-1, 11a-2, 11a) for inputting 24-bit data.
-3, 11a-4, 11a-5, 11a-6, 11a-
7, 11a-8).

Configuration data is written in each LUT of each logic circuit so as to satisfy the truth table (Table 1). The configuration shown in FIG. 9 is an example in which the number of LUTs is the maximum because the LUTs are directly connected in a tree shape and designed. Depending on the contents of the truth table, it is possible to reduce the number of LUTs by simplifying the logical expression.

The timing synchronizing parts (5a, 6a) and the carrier frequency synchronizing parts (5b, 6) shown in FIGS.
In b), FFT (5d), and despreading / equalization unit (6d), correlation calculation is mainly performed, and division is performed in the process of OFDM transmission path equalization (5e). That is, FPG
To configure the processing circuit on A, a multiplier, an adder,
And a divider is required. Input data is input at a sampling rate of tens of MHz, and it is necessary to perform calculations in real time. Assuming that the operation time of the operation circuit composed of LUT or CL of FPGA is several tens of nanoseconds, it is difficult to share the hardware in a time-division manner, and each operation unit needs its own operation circuit. Becomes Therefore,
An enormous number of LUTs and CLs are required to configure the entire baseband modulation / demodulation processing.

For example, only the FFT for MMAC is FPG.
In order to realize it on A, it is necessary to have as many CLs as there are 2300 or more LUTs. Large amounts of configuration data are required to program them. Further, since the OFDM modulation / demodulation LSI for MMAC has a scale of 1.4 million gates or more, assuming that it is composed of an FPGA, configuration data of 8 Mbits or more is required.

As shown in FIG. 4, in the conventional wireless download method of software, error detection by CRC is performed on the received software, and after the error free (no error) is confirmed, the programmable device is transferred to the programmable device. Download is done. When an error is detected, a resend request is made until error free. In a bad propagation environment, this method requires retransmitting a huge amount of configuration data many times until it reaches error-free, and a huge amount of time is required to complete the download.

If the download time of the configuration data increases, the transmission efficiency of the information data that should be originally transmitted as shown in the packet configuration diagram of FIG. 2 deteriorates. Further, in the adaptive transmission method in which the optimum function is wirelessly downloaded and realized according to the ever-changing propagation path environment, it is necessary to quickly transmit the configuration data for realizing the function. In the transmission method involving retransmission, the propagation environment changes drastically until the wireless download is completed, and the optimum function for the propagation environment after completion of the download cannot be realized on the FPGA. Therefore, in order to utilize the features of the software defined wireless communication system, it is essential to establish a highly efficient wireless transmission / download method of software including FPGA configuration data.

First, regarding the FPGA, consideration will be given to the FPGA constituting the baseband processing unit described above in the conventional example. FIG. 10A shows an internal configuration of an example of FPGA. In the following, the term "software" or "program" also includes configuration data that defines the function of the FPGA.

Configuration data is externally supplied to the FPGA chip 7a, an example of which is shown in FIG. 10B, and is written in a configuration memory (not shown). As will be described later in detail, the configuration memory is distributed in each block that constitutes the FPGA 7a. The function of each part of the FPGA is programmed by this configuration data.

The programmable logic circuit block CLB (Configurable Logic Block) 7b can be configured into a small-scale logic circuit desired by the user by the corresponding configuration data. For illustration purposes, FIG.
In A, an FPGA composed of 3 × 3 CLBs is shown, but actually, there is also a relatively large-scale FPGA in which several tens × several tens of CLBs are integrated. IOB
The (Input / Output Blocks) 7c is an interface circuit for signals outside the chip and inside the chip. The IOB 7c is also a kind of current amplifier. The IOB 7c is set to a predetermined logic amplitude voltage by the corresponding configuration data, and has a function of converting an external logic voltage into an internal logic voltage.

RC (Routing Channel) 7d is a data bus connecting each block. Programmable switches CB (Connection Block) 7e and SB (Switchi)
ng Block) 7f are arranged in a matrix. CB
Between CLB and CLB, between SB and SB and CLB
And IOB. The SB makes connections between CB and CB and between CB and IOB. Note that in FIG. 10, the hardware configuration for inputting and distributing the configuration data to the configuration memory is not shown.

FIG. 11 shows an internal structure of an example of the CLB 7b. CLB7b is a 4-input 1-output LUT (Look-Up T
able) 8a, 8b and LUT 8c with 3 inputs and 1 output, C which is a programmable logic circuit dedicated to carry generation
L (Carry Logic) 8d, 8e, 9 multiplexers 8
f, 8g, 8h, 8i, 8j, 8k, 8l, 8m, 8n
And two registers 8o and 8p. CLB is SRAM, and the input corresponds to the address. 16-bit and 8-bit configuration data can be downloaded to the 4-input and 3-input CLBs, respectively, to configure an arbitrary logic circuit. The CLB 7b further includes a configuration memory 8q that stores control signals for each multiplexer.

Table 2 shows an example of a truth table of a 4-input LUT. The CL can realize one of several predefined logic circuits according to the corresponding configuration data. Also, the control signals for each multiplexer are
Set by configuration data. By applying various configuration data to CLB, a desired logic circuit including a register can be realized.

[0043]

[Table 2]

FIG. 12 shows an example of the structure of the CB 7e.
In FIG. 12A, the buses 12a arranged one above the other
Is a bus connected to SB7f. The intersecting left-side bus 12b and right-side bus 12c are IOB 7c or C.
This is a bus connected to the LB 7b. Switch 12d
It is connected to the bit line of each bus. As shown in FIG. 12A, in the switch 12d, the source and drain of the transistor 12e are connected between each bit line. The signal for controlling the gate voltage of the transistor 12e is written in the cell 12f of the configuration memory. Depending on the cell signal, the transistor 12e is turned on.
Turn off control. In FIG. 12, description of data signals and control signals to be written in the configuration memory is omitted.

FIG. 13 shows an example of the configuration of SB7f.
As shown in FIG. 13B, buses 13a, 13b, 13
c and 13d are arranged vertically and horizontally. The switch 13e is arranged diagonally at the intersection of the bit lines of each bus, and the input is connected to the bit lines in four directions. The source and drain of the transistor 13f are connected between the bit lines from the four directions of the switch. A configuration memory cell 13g is connected to the gate of the transistor, and ON / OFF control of the bit lines in four directions is performed by signals written in the cell. Descriptions of input signals and control signals to the configuration memory are omitted.

As an example is shown in FIG. 13B, the switch 13e is also controlled to turn on / off the bit lines in four directions in the same manner as the switch 12d. Further, with respect to the IOB, the voltage level of the input / output signal, the maximum value of the output current, the insertion / non-insertion of the register, etc. are set by the data of the cell of the internal configuration memory.

As described above, by writing the data realizing the desired circuit in the configuration memory distributed in each block, CB, SB, CL
The B and IOB programs are executed, and a logic circuit having desired specifications can be realized on the FPGA.

When a logic circuit is realized by the above FPGA blocks, how each of the FPGA blocks is connected will be considered. FIG. 14 shows an example FPGA layout when a certain logic circuit is realized on the FPGA. In the following, a unit of a logic circuit configured by using a block of FPGA to realize a certain function will be appropriately referred to as a functional module. FIG. 14 is composed of two small functional modules 100a (functional module A), a functional module 100b (functional module B), and a wiring area 100c between the modules.

[0049]

In software radio communication systems, wireless transmission of FPGA configuration data is essential. In wireless transmission, bit errors occur with a very small probability even if error correction processing or retransmission processing is performed on the transmitted configuration data.

Generally, an arithmetic circuit for signal processing of radio communication is mainly composed of a normal binary arithmetic circuit of a weighting system of two. In this arithmetic circuit, each bit is weighted. When a bit error occurs in the configuration data corresponding to the LUT or CB or SB to which a bit having a large weight is input / output, a circuit failure occurs, and a normal processing result cannot be obtained. For example, MSB in FIG.
When a bit error occurs in the configuration data of the side UT 9a-2, it causes a serious error in the operation result.

Another problem is that when a normal binary arithmetic circuit of the weighting number system of 2 is constructed by an LUT of FPGA, the module area of the arithmetic circuit is the output bit number of the operand and product or sum. Dependent. WCDMA and O
If the FDM communication system is adopted, it is necessary to improve the calculation accuracy, that is, to increase the bit word length of the calculator in order to improve the transmission quality. As the bit word length increases, the circuit area of the module increases. If the circuit area of the module increases, in the case of a relatively large-scale signal processing circuit such as a digital filter that requires a large number of multipliers and adders, the wiring distance between modules becomes long and the wiring becomes complicated. The number of CBs and SBs inserted between the wirings increases, the electrical resistance of the wirings increases, the time constant that is the product of the resistance and the wiring capacitance increases, and the transmission delay time of the digital signal increases. This increases the calculation time and deteriorates the operating clock frequency.

As an example, FIG. 15 shows a product-sum operation of z = c _0.
an arithmetic circuit for performing a x + c ₁ y shows a layout diagram of a case of realizing on FPGA. The CLB, CB, and SB blocks are not shown. CB and SB are inserted at the intersections of two different wires to control the signal flow direction. Reference numerals 15a and 15b are modules of a constant coefficient multiplier for multiplying c ₀ and c ₁ , respectively. Reference numeral 15c is a module of an adder, which includes constant coefficient multipliers 15a and 15b in the preceding stage.
Add the products of.

The higher the wireless transmission bit rate or the transmission symbol rate of information, the higher the demand for the high speed arithmetic circuit in the modulator or demodulator.
When A is used, it is difficult to realize a signal processing circuit that operates at a desired clock due to performance degradation caused by wiring between arithmetic unit modules.

Next, the problem of adaptive setting of the calculation accuracy of the signal processing circuit in the software radio communication system will be described. In general, hardware for wireless communication is designed based on calculation accuracy that satisfies a certain required specification. In such a case, the communication quality is limited depending on the state of the propagation path. By using the software wireless communication technology, it is possible to adaptively set the optimum calculation accuracy corresponding to the state of the propagation path. When the condition of the propagation path becomes bad, for example,
In the case of a propagation path with a low S / N or multipath, if the accuracy of the arithmetic circuit is increased, it may be possible to prevent the deterioration of communication quality.

Improvement of calculation accuracy, that is, expansion of dynamic range requires enlargement of operation circuit in order to increase bit word length. In order to increase the dynamic range in a normal binary number arithmetic circuit of a binary number system, in order to increase the bit word length, it is necessary to add a circuit corresponding to the increased bit word length in consideration of carry propagation. is there. FIR with a complicated structure having many multipliers and adders
In the case of a signal processing circuit such as a filter, the shape of the layout already realized on the FPGA becomes complicated, and the spatial margin on the layout for arranging the circuit for the new increase of the dynamic range is not guaranteed. . Therefore,
It is not easy to add an increased circuit to many multipliers and adders already realized. Further, it is not easy to expand the data bus.

In the software radio communication system, it is ideal to use the radio download of only the configuration data of the circuit corresponding to the increase in the calculation accuracy.
However, for the above reason, it is necessary to wirelessly download the enormous amount of configuration data of all the processing circuits whose calculation accuracy has been increased, resulting in poor transmission efficiency.

FIG. 16 shows an example of a normal binary arithmetic circuit. The operand of the arithmetic circuit shown in FIG. 15 was 8 bits. Consider increasing the number of operands of this arithmetic circuit by one bit in order to improve the arithmetic precision. 16a, 16
Reference numerals b and 16c are arithmetic modules already realized. It is necessary to add hardware 16d, 16e, 16f corresponding to the increase to the arithmetic modules 16a, 16b, 16c. In that case, there must be a spatial allowance for adding the increased amount of hardware.
Further, although wiring is added later, it is necessary to arrange the wiring so as not to contact the wiring already realized. Therefore, it may not always be optimum, and as shown by reference numeral 16g in FIG. 16, it may be necessary to realize a long-distance wiring that bypasses the module.

Therefore, an object of the present invention is to improve the reliability of the circuit so that the signal processing operation does not become defective due to the failure of the signal processing circuit caused by the bit error of the program data transmitted by radio, and the arithmetic module. It reduces the deterioration of the circuit performance due to the increase of the wiring length between the wirings and the complicated wiring.

Another object of the present invention is to be able to adaptively set the calculation accuracy of the signal processing circuit, and to transmit only the configuration data of the circuit corresponding to the difference for the setting. This is intended to improve the transmission efficiency of configuration data.

[0060]

In order to solve the above-mentioned problems, the invention of claim 1 is such that a part or all of hardware is composed of a programmable logic circuit, and the desired data is generated by program data for the logic circuit. In the terminal device adapted to realize the wireless communication system of No. 1, the received program data constitutes a remainder number calculation means having a redundant dynamic range, and a circuit failure occurs when the calculation result exceeds the non-redundant dynamic range. Is a terminal device that selects the combination of the surplus digits when it does not exceed and outputs it as the correct calculation result. According to the invention of claim 11, it is considered that a circuit failure has occurred when the operation result exceeds the non-redundant dynamic range, and a combination of surplus digits is selected when the operation result does not exceed the dynamic range.
It is a base station device that outputs a correct calculation result. According to the twenty-first aspect of the invention, when the operation result exceeds the non-redundant dynamic range, it is considered that a circuit failure has occurred, and when the operation result does not exceed the surplus digit combination, the combination is selected and the correct operation result is output. It is a relay device.

According to a second aspect of the present invention, a part or all of the hardware is composed of a programmable logic circuit, and the terminal device adapted to realize a desired wireless communication system by program data for the logic circuit is received. The generated program data is configured for each remainder digit, and a combination of a remainder number calculation means having a redundant dynamic range and a different remainder digit of the remainder number calculation means is generated, and the calculation result of the generated combination is calculated as 2 A plurality of converting means for converting into a base number, a determining means for determining whether or not the outputs of the plurality of converting means exceed the non-redundant dynamic range, and a non-redundant dynamic range in response to the determination result of the determining means. If you do not exceed the combination of remainder digits,
The terminal device is provided with a selection unit that selectively outputs a correct calculation result. A twelfth aspect of the present invention is a base station apparatus, which selects a combination of remainder digits when a calculation result does not exceed a non-redundant dynamic range and outputs the combination as a correct calculation result. A twenty-second aspect of the present invention is a relay device that selects a combination of remainder digits when a calculation result does not exceed a non-redundant dynamic range and outputs the selected combination as a correct calculation result. A thirty-first aspect of the present invention is a communication method comprising: a selection step of selectively outputting a combination of remainder digits when a non-redundant dynamic range is not exceeded as a correct calculation result.

When the configuration data for the FPGA, which is a program of the software defined radio, is wirelessly transmitted, an incorrect calculation result is output due to a circuit failure caused by a bit error caused by noise or the like. In the present invention, focusing on the fact that the product-sum operation can be executed independently for each remainder digit in the remainder number operation, the dynamic range is made redundant, and the combination of the outputs of several remainder digits is changed to a normal binary number. It is possible to check whether the converted result is equal to or more than the non-redundant dynamic range, and output only the result smaller than the non-redundant dynamic range as a correct operation result.

According to a seventh aspect of the present invention, a part or all of the hardware is composed of a programmable logic circuit, and the terminal device is adapted to realize a desired wireless communication system by program data for the logic circuit. The program data is provided with a residue number calculating means composed of an arithmetic circuit configured for each residue digit, and the error detecting code is decoded for each program data with respect to each arithmetic circuit of the residue number calculating means. It is a terminal device that does not configure an arithmetic circuit in which a bit error is detected in program data and requests retransmission of only the program data of the relevant arithmetic circuit. The invention of claim 17 is a base station apparatus which does not form an arithmetic circuit in which a bit error is detected in program data by an error detection code and requests the retransmission of only the program data of the relevant arithmetic circuit.
The invention of claim 27 is a relay apparatus which does not form an arithmetic circuit in which a bit error is detected in the program data by the error detection code and requests the retransmission of only the program data of the relevant arithmetic circuit. According to a thirty-sixth aspect of the present invention, there is provided a communication method for requesting retransmission of only program data of a corresponding arithmetic circuit without forming an arithmetic circuit in which a bit error is detected in the program data by the error detection code.

In the present invention, by utilizing the property that the redundant digits of the redundant residue number system are independent, the CRC is set for each configuration data of the arithmetic circuit of the corresponding residue number arithmetic means of each modulus.
Is added to check the failure of the remainder number calculation means for each calculation circuit corresponding to the modulus, and to retransmit the configuration data of the remainder number calculation circuit for each modulus. Thereby, the transmission efficiency of the configuration data can be improved.

According to an eighth aspect of the invention, in a terminal device in which a part or all of hardware is composed of a programmable logic circuit, and a desired wireless communication system is realized by program data for the logic circuit, The program data is provided with a remainder number calculation means composed of a calculation circuit configured for each remainder digit, and newly added to improve the calculation accuracy of the remainder number calculation means when the state of the propagation path deteriorates. The terminal device receives the program data of the residue number calculation means having the accuracy corresponding to the increase in the calculation accuracy. An eighteenth aspect of the present invention is a base station apparatus for receiving program data of a remainder number calculation means having accuracy equivalent to an increase in newly added calculation accuracy. A twenty-eighth aspect of the present invention is a relay apparatus for receiving program data of a remainder number calculating means having accuracy equivalent to an increase in newly added operation accuracy. According to a thirty-seventh aspect of the present invention, in order to improve the calculation accuracy of the remainder number calculation means when the state of the propagation path deteriorates, there is provided a remainder number calculation means having accuracy corresponding to an increase in the calculation accuracy newly added. This is a communication method for receiving program data.

In the present invention, in order to adaptively set the dynamic range of the signal processing circuit based on the remainder number calculating means, only the program data of the arithmetic circuit of the remainder digit corresponding to the increase of the dynamic range is wirelessly transmitted. The program data can be efficiently downloaded wirelessly.

[0067]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. To facilitate understanding of the present invention, a remainder number calculation method will be described. In a normal binary arithmetic circuit of 2 weighted number system, since a carry signal is transmitted and received between the digits, the arithmetic circuit cannot be divided for each digit. In the present invention, a remainder number arithmetic circuit different from the ordinary binary number arithmetic circuit is used.

The principle of remainder calculation will be described. A system in which the integer x is represented by a set of remainders for N disjoint integers m ₁ , m ₂ , ..., _{M N} is called a residue number system. The residue number operation is an operation method in which a normal addition or multiplication is applied to an input operand and then a residue obtained by division by a certain method is output. Hereinafter, an operation for obtaining a remainder of a certain integer x by the modulus m is expressed as x mod m. Further, the input and output of the remainder number calculation by the same method will be referred to as the remainder digit. In the residue number system,
Addition and subtraction can be performed independently for each residue. An example of addition is shown in FIG. 17A. Set of mods {m ₁ , m ₂ , m ₃ }
Is, for example, {3, 5, 7}. Expression 8 is {2, 3, 1} when expressed by a residue number, and Expression 9 is {0, 4,
2}. The result of addition (8 + 9) is
{2mod 3,7mod 5,3mod 7} = {2,2,3}.

FIG. 17B shows an example of multiplication (9 × 10). Similar to the addition example, if the modulo set is {3,5,7}, this multiplication is {0,4,2} × {1,0,3} =
{0mod3,0mod5,7mod6} = {0,0,6}. From FIG. 17, in the calculation of the remainder number, there is no transmission / reception of a signal such as a carry between each residue digit. Therefore, the circuit for each residue digit can be realized independently. However, the modulo of each residue digit must be relatively prime. The range of integers that can be represented by a set of modulo is called the dynamic range.

FIG. 18 is a diagram comparing the scales of the modules of the residue number adder and the normal binary number adder. FIG. 18A
Shows the structure of the residue number adder, and FIG. 18B shows the structure of a normal binary number adder. The maximum dynamic range of the remainder calculation is represented by the product of the moduli used. In this example (3 ×
5 × 7 = 105). The word length of a normal binary arithmetic unit having the same dynamic range is 7 bits. Reference numerals 18a, 18b and 18c indicate modules of respective digits of the residue number adder. Reference numeral 18d indicates a module of a conventional binary adder. However, in the figure, CLB. SB. CB is omitted.

A computing unit 18 for computing a residue number of each residue digit
The word lengths of a, 18b, and 18c are shorter than the word length of the entire dynamic range. Therefore, the layout area occupied by the remainder number calculator of each remainder digit on the FPGA can be smaller than that of a normal binary number calculator. When implementing a digital filter or the like composed of a large number of arithmetic units, the length of wiring between arithmetic units can be shortened, and the complexity of wiring can be reduced.
Considering realization with FPGA, it is possible to reduce the number of SBs and CBs that configure the wiring, reduce the wiring resistance and the wiring capacitance, reduce the signal delay time between arithmetic units, and increase the operating clock frequency. it can.

FIG. 19 realizes z = c ₀ x + c ₁ y,
FIG. 20 shows a layout of a remainder number arithmetic circuit designed with a dynamic range of 105, and FIG. 20 shows a layout of a normal binary number arithmetic circuit. In FIG. 19, reference numeral 19a
And 19b show a constant coefficient multiplier when the modulus is 3,
Reference numerals 19d and 19e indicate constant coefficient multipliers when the modulus is 5, and reference numerals 19g and 19h indicate that the modulus is 7.
The constant coefficient multiplier in the case of is shown. Reference numerals 19c and 19
f and 19i represent adders in the case where the modulo is 3, 5, and 7, respectively. In FIG. 20, reference numerals 19j and 19k
Indicates a constant coefficient multiplier having a binary arithmetic circuit configuration,
Indicates an adder for adding the outputs of both arithmetic circuits 19j and 19k.

Due to the independence of the remainder digits, there is no exchange of signals, such as exchange of carry, between arithmetic circuits having different moduli. As the number of arithmetic units increases and the arithmetic algorithm becomes more complicated and the connections between arithmetic units become more complicated, the signal processing circuit using the remainder arithmetic circuit becomes more advantageous. Compared with the signal processing circuit using the normal binary arithmetic circuit shown in FIG. 20, performance deterioration due to the complexity of the wiring between the arithmetic circuits and the wiring length can be alleviated.

Considering a signal processing circuit for wireless communication,
Conversion of digital data and analog signals is required.
A commercially available general A / D converter converts an analog signal into normal binary data. Therefore, it is necessary to convert the ordinary binary number representation to the remainder number system. This is performed by a combinational logic circuit composed of FPGA CLB or a conversion circuit composed of ROM. Similarly, a general D / A converter on the market also converts ordinary binary data into an analog signal. Therefore, it is necessary to convert the numerical representation of the residue number system into the ordinary binary numerical representation. In that case, the exchange of data between the remainder digits occurs, and the independence of the remainder digits breaks down. However, the calculation load is very small as compared with the calculation load in the main filter, for example. The conversion from the residue number system to the ordinary binary number system is performed based on the conversion to the mixed radix system or the Chinese Remainder Theorem.

FIG. 21 shows an example of the configuration of a signal processing system based on remainder calculation for inputting and outputting an analog signal. The analog signal is once converted into a normal binary number by the A / D converter 20a. A / D converter 20a
Output each modulo m ₁ of, m _2, ···, converters 20b-1 and 20b-2 correspond respectively to the m _N,. ． ． , 20b-1N, a normal binary number is converted into a residue number corresponding to each residue digit of each modulus. Next, the signal processing circuits 20c-1, 20c-2 ,. ． ． ，
The remainder calculation is performed by 20c-N. The signal processing circuits 20c-1, 20c-2 ,. ． ． , 20
The c-N is composed of a residue number computing unit that executes a signal processing algorithm that performs a product-sum calculation such as an FIR filter. The signal processing circuits 20c-1, 20c-2 ,. ． ． , 2
The result of 0c-N is input to the converter 20d, and the converter 20d
After the remainder is converted to normal binary data by d, it is converted to an analog output signal by the D / A converter 20e.

The conversion from the ordinary binary number system to the remainder number system is
It can be implemented relatively easily using table lookup and modulo addition. On the other hand, the inverse conversion from the residue number system to the binary number system is complicated. Hereinafter, two types of algorithms for converting a numerical value in the residue number system into a normal binary number will be described. A system that expresses numerical values using a plurality of bases is called a mixed radix system. A normal decimal number expression is a number expression using only the radix 10, and a binary number expression is a number expression using only the radix 2.

From the residue number system based on the mixed radix system to the usual 2
Numerical value x of the residue number system using the conversion algorithm to the base number system
FIG. 22 shows an example in which ₁ , x ₂ and x ₃ are converted into a normal binary number y. The modulo m ₁ = 3, m ₂ = 4, m ₃ = 5, and the residual numbers corresponding to each modulo are x ₁ = 1 and x ₂ respectively.
= 3, x ₃ = 3. This remainder number is converted into a normal binary value y.

First, let x ₁ which is the minimum remainder of the modulus be a ₁
And Next, a ₁ is subtracted from each residue number. Divide the result by m ₁ = 3. This is equivalent to multiplying the inverse element of m ₁ = 3 in the residue number calculation of m ₂ = 4 and m ₃ = 5. The inverses are 3 and 2 for m ₂ and m ₃ , respectively. The result 2 of the remainder digit of m ₂ = 4 is set to a ₂ . next,
Subtract a ₂ from the value of the remainder digit of m ₃ and divide by m ₂ = 4. That is, it is multiplied by 4, which is the inverse element of 4 in m ₃ = 5.
In this way, a ₁ = 1, a ₂ = 2, a ₃ = 3 are obtained. Different numbers in mixed radix system Radix 1, m ₁ , m
It is expressed by ₁ m ₂ , and y = a ₁ + a ₂ m ₁ + a ₃ m ₁ m ₂
Is defined by Substituting, (y = 1 + 2 × 3 + 3 × 3
× 4 = 43) is required.

An explanation will be given of a conversion algorithm from the residue number system to the ordinary binary number system by the Chinese remainder theorem. The definition formula of this theorem is shown in Formula (1).

[0080]

[Equation 1]

In the equation (1), M and m _i ^
Is defined by the following equations (2) and (3). Note that ^ is added above the letter m, but in this specification, m and ^ are shown separately for convenience of notation.

[0082]

[Equation 2]

[0083]

[Equation 3]

However, m _i ^ ^-1 shown in equation (4) is modulo m _i
The inverse element of m _i ^ in is shown.

[0085]

[Equation 4]

For example, the number of moduli N = 3, the modulus is m ₁ = 3,
It is assumed that m ₂ = 4 and m ₃ = 5, and the residual numbers corresponding to the respective moduli are x ₁ = 1, x ₂ = 2, and x ₃ = 3. The expression is converted into an ordinary binary number with this remainder digit. First, from the equation (2), M = 60, and from the equation (3), m ₁ ^ = 20, m ₂ ^ 1
5, m ₃ ^ = 12. Furthermore, from the equation (4), m ₁
^ ^-1 [m ₁ ] = 2, m ₂ ^ ^-1 [m ₂ ] = 3, m ₃ ^ ^-1 [m
₃ ] = 3. Substituting these values into equation (1),
The usual binary representation value y = 58 is obtained.

In both of the above conversion algorithms, between the remainder digits
Since there is a signal transfer in the
It will not stand. For example, in the mixed radix system example of FIG.
Law m ₂ And m₃ M from the remainder digit of₁ Is the remainder of₁ Pull
I am Also, in the Chinese Remainder Theorem,
Here, the sum of the calculation results of each residue digit is calculated. Surplus
In order to utilize the features of mathematical operations, signal processing at each residue digit is
The calculation amount of the logic algorithm is a binary number from a residue number system.
Must be much larger than the amount of computation for system conversion
I have to.

Up to this point, a general residue number system has been described. Next, the redundant residue number system will be described. Generally, the signal processing circuit is designed by setting the data word length of the arithmetic unit to a minimum in order to adapt to the minimum dynamic range required for processing (hereinafter, referred to as non-redundant dynamic range). Is performed. Such a signal processing circuit designed using a residue number arithmetic unit will be referred to as a signal processing circuit based on non-redundant residue number arithmetic. On the other hand, in the redundant remainder number calculation, a redundant remainder digit is added to the signal processing circuit to design a circuit so that a dynamic range more than necessary for signal processing (this is called a redundant dynamic range) can be obtained.

In a software defined radio system using FPGA, FPG is used to improve reliability.
When the configuration data of A is transmitted wirelessly, the configuration data is encoded by an error correction code and transmitted, and the receiving side decodes it to correct the bit error generated on the transmission path. Alternatively, a CRC code or parity data is added and transmitted, and the receiving side checks the CRC code or parity data and if an error occurs, a retransmission request signal is transmitted to the transmitting side and the same information is retransmitted. do that for me. Even if these processes are performed to improve reliability, the bit error rate is extremely low, but erroneous bits still exist. A circuit failure caused by the error bit causes a malfunction in the operation of the wireless communication system.

In a signal processing circuit for calculating a redundant remainder number configured by wirelessly transmitted configuration data, it is assumed that an error bit in the configuration data causes a failure in an arithmetic circuit of a certain remainder digit. In this case, there is a high probability that the calculation result obtained by converting all the values of the remainder digits into the normal binary number system will exceed the non-redundant dynamic range. Therefore, the failure of the signal processing circuit is detected by checking whether or not the calculation result obtained from all the remainder digits exceeds the non-redundant dynamic range.

Further, after such a failure detection, in order to find out which method of the remainder arithmetic circuit has a failure, a plurality of combinations of a plurality of methods that obtain a dynamic range exceeding the non-redundant dynamic range are created. . A result in which the calculation result of the combination is within the non-redundant dynamic range is output as a normal calculation result. On the other hand, although a failure occurs in a combination that outputs a result exceeding the non-redundant dynamic range, a surplus digit in which the arithmetic circuit has a failure can be searched for by comparing with a result of another combination. A signal processing system devised so that a normal calculation result can be output even in the presence of a circuit failure is called a fault tolerant system.

A specific example will be described. In modulo arithmetic, the dynamic range is equal to the modulus product. Here, for simplicity of explanation, it is assumed that the signal processing circuit only performs multiplication. As shown in FIG. 23, the entire set of moduli is {3, 5, 7, 11}. It is assumed that the remainder digit multiplication circuit corresponding to the four moduli is realized by writing the configuration data downloaded via radio into a block on the FPGA. Choosing 3 and 5 as the moduli, the non-redundant dynamic range is 3 × 5 = 15. This means that the general operation result is smaller than 15. On the other hand, examples of combinations of methods for obtaining the redundant dynamic range are {3, 5, 7}, {3, 5, 1
1}, {3, 7, 11}, {5, 7, 11}. FIG. 23A shows an example of 4 × 3 multiplication when no failure occurs. FIG. 23B shows an example in the case where a failure occurs in the processing circuit for the remainder digit of which the modulus is 11, and 8 is calculated instead of the normal result 1. In FIG. 23C, reference numerals 22a, 22
Reference numerals b, 22c, and 22d denote multipliers corresponding to the moduli 3, 5, 7, and 11, respectively.

Next, a value obtained by converting the calculation result of each set for which the redundant dynamic range is obtained into a normal binary number system is compared with 15 which is the non-redundant dynamic range. {3, 5,
7}, {3, 5, 11}, {3, 7, 11}, {5
If the residual numbers of the combination of 7, 11} are converted into ordinary numerical values, the results are 12, 162, 96, 327, respectively. As a result, only 12, which is the result of the arithmetic circuit using the remainder digit of {3, 5, 7}, is within the non-redundant dynamic range. Therefore, 12 is regarded as a normal operation result and output. Other combinations {3, 5,
11}, {3, 7, 11}, {5, 7, 11} exceed the non-redundant dynamic range, and since all include modulo 11, the remainder multiplication circuit corresponding to modulo 11 It can be estimated that there is a failure in the.

In order to expand the redundant dynamic range, the more mods, that is, the more the number of modulos, the greater the number of modal combinations and the probability of obtaining a correct result within the non-redundant dynamic range. Higher and more reliable.

FIG. 24 shows an example of the configuration of a signal processing circuit based on the redundant residue number arithmetic circuit based on the above-mentioned principle. These hardwares are realized on FPGA. Each of the signal processing circuits 23a-1, 23a-2, and 23a-4 is composed of a remainder arithmetic circuit corresponding to each modulus of the modulo set {3, 5, 7, 11}, and is used for modulation and digital radio communication. Realize the demodulation algorithm. Conversion circuits 23b-1 and 23b
Outputs from the signal processing circuits 23a-1, 23a-2, 23a-3, and 23a-4 at the previous stage are supplied to -2, 23b-3, and 23b-4. Conversion circuits 23b-1, 23b-
2, 23b-3, 23b-4 have a set of mods {3, 5,
7}, {3, 5, 11}, {3, 7, 11}, {5
The output of the arithmetic circuit of the remainder digit corresponding to 7, 11} is supplied, and the output of the arithmetic circuit is converted into a normal binary number system. Conversion circuits 23b-1, 23b-2, 23b-3,
The output of 23b-4 is the comparison circuits 23c-1, 23c-2,
In each of 23c-3 and 23c-4, it is compared with the value 15 of the non-redundant dynamic range.

Comparing circuits 23c-1, 23c-2, 23c
Each of the comparison results of -3 and 23c-4 is the decoder 23.
Selection information that is supplied to d and is selected in the decoder 23d that selects a combination of moduli that outputs a result smaller than the non-redundant dynamic range. The selection information is input to the multiplexer 23e. The multiplexer 23e includes conversion circuits 23b-1, 23b-2, 23b-3, 2
The output of 3b-4 is supplied, and the normal result converted into a normal binary number is selectively output. If all modulo pairs are above the non-redundant dynamic range, the decoder 2
3d outputs a retransmission request signal to the base station.

In consideration of the wireless download function of the software defined wireless communication system in FIG. 24, the configuration data of the signal processing circuits 23a-1, 23a-2, 23a-3, 23a-4 are wirelessly transmitted. On the other hand, conversion circuits (20b-1, 20b-2, ..., 20b-) for converting an ordinary binary number into a residue number system.
N), and a conversion circuit 23b for detecting a failure and selecting a result.
-1,23b-2,23b-3,23b-4, the comparison circuits 23c-1,23c-2,23c-3,23c-4, the decoder 23d, and the configuration data of the multiplexer 23c have bit error. Existence is not allowed. These configuration data are supplied not from the wireless but from the configuration database inside the portable wireless communication terminal.

FIG. 25 shows the configuration of a software defined radio system based on this design concept. Reference numeral 24a is an antenna for receiving a modulated wave that transmits configuration data. Reference numeral 24b is a radio for receiving the configuration data.
The antenna 24a and the wireless device 24b are mainly shown in FIG.
The configuration data of the signal processing circuit of is received and demodulated. It also makes a request to send necessary configuration data.

Reference numeral 24c is a configuration database, and as described with reference to FIG. 23, it stores the configuration data of the conversion circuit and the comparison circuit for detecting a failure. The demodulated configuration data and the configuration data at the output of the database are supplied to the configuration data combination and generator 24d to generate the overall configuration data. The generated configuration data is supplied to the software radio 24e to reconfigure the radio that performs a desired communication method. Reference numeral 24f is an antenna for the software defined radio. After the reconfiguration, the modulation / demodulation process for the user information data is performed on the software defined radio.

FIG. 26 shows a configuration example of the software defined radio unit.
Shown in. The signal of the center frequency fc received from the antenna passes through the antenna switch 25b and passes through the low noise amplifier 2
5j, and the reception mixer 25k mixes the oscillation frequency fl1 of the first local oscillator 25c and converts it into the intermediate frequency fi. The quadrature detector 25l quadrature-detects the intermediate frequency at the frequency of the second local oscillator 25d with fl2 = fi and converts it into analog baseband signals I and Q. The analog IQ signal is converted by the A / D converter 25m into a digital baseband signal ≡-D. Converted to Q-D.

The externally demodulated configuration data is downloaded to the programmable baseband digital modulator 25v or the programmable baseband digital demodulator 25n. After downloading the configuration data, A / D converter 2
The output data ≡-D and Q-D of 5 m are supplied to the programmable baseband digital demodulation unit 25n, and the desired demodulation processing determined by the program is performed.

When transmitting the information bits, the modulated data bits are modulated by the programmable baseband digital modulator 25v in a desired modulation method. Modulator 2
The output of 5v is a digital baseband signal ≡-D. Q-
It is input to the D / A converter 25h as D. The D / A converter 25h converts the digital IQ signal into an analog signal. In the quadrature modulator 25g, the second local oscillator 2
Quadrature modulation is performed with an oscillation frequency fl2 of 5d, and the intermediate frequency fl2 = fi is converted. First in the transmission mixer 25f
At the frequency fl1 of the local oscillator 25c, fc = fl2 +
The frequency is converted to fl1. Power amplifier 25e
Amplifies the digitally modulated signal to a predetermined transmission power.
The amplified signal finally passes through the antenna switch 25b and is sent to the external antenna.

The redundancy of the redundant dynamic range is defined as (redundant dynamic range / non-redundant dynamic range). In a propagation environment in which a bit error is likely to occur in the configuration data, increasing redundancy can improve reliability. In addition, in a propagation environment in which an error is unlikely to occur, it is desirable that the redundancy is low in terms of configuration data transmission efficiency, circuit usage efficiency, and power consumption. Therefore, the redundancy may be adaptively set based on the ratio (S / N) of signal power and noise power, which is the quality of the propagation path for wirelessly transmitting the configuration data.

FIG. 27 shows a configuration diagram for realizing this. Only differences from FIG. 25 will be described. After the S / N of the configuration data propagation path is measured by the S / N measuring device 26g, the redundancy is determined by the redundancy determining unit 26h from the value. The redundancy information is input to the configuration data download radio device 26b, and requests the base station to transmit the configuration data of the arithmetic circuit corresponding to the desired redundancy. Further, the redundancy information is also input to the configuration database 26c, and the configuration data for performing the failure detection adapted to the redundancy is read out.

An example of the S / N measuring section 26g will be described. However, the RF unit and the IF unit are omitted, and only the signal processing method of the baseband unit will be described. FIG. 28 shows S
It is a block diagram which shows the structural example of the / N measurement part 26g. S
The / N measuring unit includes an area discriminating unit 51, an S / N measuring circuit 52,
It is composed of an S / N measuring circuit 53, an S / N measuring circuit 54, an S / N measuring circuit 55 and an average calculating section 56. Here, a case where the subcarrier modulation method is QPSK will be described. There are four signal points of QPSK, and there are four effective areas on the complex plane. In each of these four areas,
The S / N measuring circuit 52, the S / N measuring circuit 53, the S / N measuring circuit 54 and the S / N measuring circuit 55 correspond to each other.

The region discriminating unit 51 discriminates a threshold value for each of the real and imaginary parts of the complex number data, that is, discriminates to which of the above-mentioned four regions the data valid signal corresponding to the discrimination. Is output.

The data from the area judging section 51 is inputted only to the S / N measuring circuit in which the data valid signal becomes active. The activated S / N measurement circuit calculates and outputs the S / N measurement value corresponding to each area based on the input data. The average calculator 56 averages the S / N measurement values of the supplied regions and outputs the averaged values.

FIG. 29 is a block diagram showing the structure of the area determination unit 51. The input signal is supplied to threshold value comparison circuits 61 and 62. Threshold comparison circuits 61 and 6
2 calculates which region the input data belongs to, expresses the calculation result by 2 bits, and outputs a signal corresponding to this expression. Specifically, comparison is performed with respect to a threshold value, that is, 0. If the input is 0 or more, 1 is output, and if not, 0 is output.

The decoder 63 outputs a data valid signal indicating which area of data corresponds to, based on the signals supplied from the threshold comparison circuit 61 and the threshold comparison circuit 62.

FIG. 30 is a block diagram showing the structure of the S / N measuring circuit 52. Input data is written in the memory 71. The accumulator 72 calculates and outputs the sum X1 of these data based on the sequentially input data. The memory 71 and the accumulator 72 operate only when the data valid signal becomes active. That is, only when the data valid signal becomes active,
The output data of the area discrimination unit 51 is input to the memory 71 and the accumulator 72. The counter 73 counts the number of data in one frame based on the input data valid signal.

The output X1 of the accumulator 72 is input to the complex number divider 74. The complex number divider 74 divides the output X1 of the accumulator 72 by the number Y1 of data output from the counter 73 to obtain an average value X2 (= X1 / Y1
) Is calculated and output to the absolute value square calculator 75 and the difference absolute value square calculator 76.

The absolute value square calculator 75 calculates the absolute value squared X3 (= | X2 | ² ) of the average value X2 from the average value X2 output from the complex number divider 74, that is, the average power (signal power). Calculate and output the average value of). 2 of absolute difference
The multiplication calculator 76 calculates and outputs the square of the absolute value of the difference between the average value X2 output from the complex number divider 74 and the data Y2 read from the memory 71, X4 (= | X2-Y2 | ² ). To do. The accumulator 77 calculates and outputs the sum X5 of these data based on the data output from the absolute value square calculator 76.

The divider 78 divides the output X5 from the accumulator 77 by the total number Y1 of data in one frame to obtain a variance value, that is, the average noise power Y in the frame.
Calculate and output 3 (= X5 / Y1). The divider 79 is
The average power X3 is divided by the average noise power Y3 to calculate and output the S / N measurement value (X3 / Y3).

In the above description, the S / N measuring circuit 52 has been described as an example, but the S / N measuring circuit 53, the S / N measuring circuit 54 and the S / N measuring circuit 55 also have the same configuration, The same process as the above process is performed.

In one embodiment of the present invention, if the value obtained from any combination of the remainder digits does not fall within the range of the non-redundant dynamic range, the correct processing result cannot be output and the decoder 23d in FIG. A resend request signal is output. In this case, a request to resend the configuration data of the remainder number calculation circuit is newly made for each remainder digit, the circuit is reconfigured for each remainder digit on the area of the existing remainder calculation circuit, and the output of the reconfigured circuit is output. The dynamic range is included in the judgment. In this case, two types of retransmission methods are possible.

The first method is a method of requesting once to retransmit the configuration data of the remainder number arithmetic circuit of the remainder digit corresponding to all the moduli. The flow of this method is shown in the flowchart of FIG. In FIG. 31, when a retransmission request signal is generated from the decoder 23d in step S1, all modulus = m ₁ , m ₂ , ..., _{M N} are dealt with from the terminal device to the base station in step S2. Retransmission of the configuration data of the remainder arithmetic circuit is required.

In the second method, the modulus value is sequentially increased until the operation result becomes smaller than the non-redundant dynamic range, starting from the retransmission request of the configuration data of the circuit whose modulus is the smallest m ₁ . The resend request is repeated for each configuration data of the digit remainder number calculation circuit. FPG the retransmitted configuration data
It is realized on A and the calculation result and the non-redundant dynamic range are compared. If the calculation result is smaller than the non-redundant dynamic range, the retransmission processing ends. If it is equal to or more than the non-redundant dynamic range, it is requested to retransmit the configuration data of the modulo remainder arithmetic circuit having a larger modulus.

The flow of the second method is shown in the flowchart of FIG. In step S11, the variable i (1 to N)
Is set to an initial value of 1. In step S12, it is determined whether or not the retransmission request signal is output from the decoder 23d. If not output, the process ends.

When it is determined that the retransmission request signal has been output, in step S13, it is requested to retransmit the configuration data of the remainder number arithmetic circuit of the modulus m _i (initially m ₁ ). In the next step S14, error bits are corrected by decoding the error correction code for the received configuration data, and the corrected configuration data is inspected by CRC for the presence or absence of an error.

In step S15, it is determined whether or not the CRC inspection is successful, that is, whether or not there is an error. If it is determined that there is an error, the process proceeds to step S
The procedure returns to the process 13 of retransmitting the configuration data. If it is determined that there is no error, replace Residue Arithmetic circuit corresponding to m _i on the FPGA the new circuit to operate.

Then, in step S17, it is determined whether or not the retransmission request signal is output from the decoder 23d. If the retransmission request signal is not output, the process ends. If it is output, in step S18,
(I = N?) Is determined. If i has not reached N, i is incremented in step S19 and the process returns to the process (retransmission request) in step S13. N is i
In step S20, (i
= 1), and similarly, the process returns to step S13 (retransmission request). In this way, even if the retransmission of the configuration data of the arithmetic circuits corresponding to all the moduli of m _{1 to} m _N is completed, if the arithmetic result is not smaller than the non-redundant dynamic range, that is, the decoder 23d retransmits the data. If the request signal is output, start over from m ₁ .

The above-described two methods detect a failure by checking whether or not the calculation result falls within the non-redundant dynamic range. The signal processing circuit based on the redundant remainder calculation corresponding to all modulo
Even if it is realized on A and a fault is not detected, a CRC for detecting a bit error is inserted for each configuration data of the residue number arithmetic circuit of each modulus, and the CRC is inspected, and a bit error is obviously detected. If you know what is happening,
It can be inferred that a failure has occurred in the circuit before implementation on the FPGA. At that time, the retransmission of the configuration data of the corresponding remainder arithmetic circuit is requested.

FIG. 33 shows the frame format of such configuration data. 27b-1
Is configuration data of an arithmetic circuit of a certain modulus m ₁ . The CRC 27a-1 is a CRC added to the configuration data. Below, the configuration data (27
b-2, ..., 27b-N) has the same CRC (2
7a-2, ..., 27a-N) are added. This C
The bit sequence including RC is encoded by an error correction code. The encoding is done collectively for all configuration data, or CRC
An error correction code is encoded for each configuration data of the arithmetic circuit of i and modulo = mi. By decoding this error correction code, a correctable error is corrected by the correction capability of the code, an uncorrectable error cannot be corrected, and an error flag indicates that there is an error.

After the error bit is corrected by decoding the error correction code as described above, a check using CRC1
If a bit error occurs in the configuration data of the remainder arithmetic circuit of m ₁ , it means that a failure has occurred in that circuit. CR after correction of error bits
An error detected by C has a low probability but is possible. In this case, it is not necessary to implement the remainder arithmetic circuit on the FPGA, as in the case where the uncorrectable error is determined by the error correction code. Only the retransmission of the configuration data of the remainder arithmetic circuit corresponding to the modulus in which the error is detected by the CRC is requested.

A flowchart of this processing is shown in FIG. In step S31, the variable i (= 1 to N) is set to the initial value 1. In step S32, the configuration data is received and error correction is performed using the error correction code. If the error can be corrected, step S3
At 3, the inspection is done by CRC1. In step S34, it is determined whether the inspection has passed. If no error can be detected by CRC1, it is determined that the inspection has passed, and in step S35, the modulus = m.
A remainder number arithmetic circuit of ₁ is realized on the FPGA.

Then, in step S36, (i =
N? ) Is determined. If i has not reached N,
In step S37, i is incremented and the process of step S33 (error check using CRCi)
Return to. In the case of i = 1, i = 2, and the same process is performed on CRC2. The process is repeated until i = N, and if N reaches i, the process ends.

In step S34, if the configuration data fails the CRC check, in step S38, a request is made to retransmit only the configuration data of the remainder arithmetic circuit for m ₁ . Then, in step S39, the retransmitted modulus =
The configuration data of the remainder arithmetic circuit of m ₁ is received, and the error bit is corrected by decoding the error correction code. Then, the process proceeds to step S33 (CRCi
Return to (inspection using). Although omitted in FIG. 34, if the error cannot be corrected by the error correction code, retransmission of the configuration data is requested.

Furthermore, by utilizing the independence of the remainder digit in the remainder number calculation, the dynamic range of the signal processing circuit of the software defined radio can be easily reset by wireless. The terminal station requests the base station to transmit only the configuration data of the remainder arithmetic circuit corresponding to the modulus corresponding to only the increase of the dynamic range.
In this case, the constraint on the layout arrangement position of the increased signal processing circuit does not depend on the layout arrangement position of the already realized signal processing circuit more than the normal binary arithmetic circuit because of the independence of the remainder digit. A conversion circuit for converting a normal binary number representation to a residue number representation, a test for an operation result, and a result selection circuit are programmable by setting a modulo value, a number, or the like, or The configuration data of a circuit having a desired function is read from a local database and supplied to the FPGA to realize it.

FIG. 35 shows an example of a layout configuration diagram realized on the FPGA. Reference numeral 31d is an FPGA chip. Reference numerals 31a-1, 31a-2, 31a-
Reference numerals 31b- and 31a-4 are conversion circuits for converting an already realized normal binary number into a residue number system.
1, 31b-2, 31b-3, 31b-4 are signal processing units by the already implemented remainder number calculation circuit. Reference numeral 31c is a circuit that converts four types of remainder numbers into normal binary numbers and selects the correct result, and is assumed to be already realized.

To change the dynamic range in order to improve the calculation accuracy, for example, to increase it by 13 times,
The arithmetic circuit 31b-5 whose modulus is 13 may be added. Along with this, a conversion circuit 31a-5 for converting an ordinary binary number into a remainder number whose modulus is 13 is added, and a remainder number system considering the new modulus 13 is converted into an ordinary binary number system. Conversion circuit 31c for selecting the correct calculation result
Need to be changed.

Conversion circuit 31a-5 and conversion circuit 31c
Is the terminal configuration database 2
Read out from 4-c (Fig. 25) or 26-c (Fig. 27) and realize on FPGA, or if these are designed as a programmable circuit, the value of the modulus and the number of moduli It can be applied to the newly added arithmetic circuit simply by changing the setting signals such as.

The present invention is not limited to the above-described embodiment of the present invention and the like, and various modifications and applications can be made without departing from the scope of the present invention. For example, as the programmable logic circuit, a microprocessor (or DSP) may be used instead of the FPGA. Further, as the error detection code, a code such as simple parity other than CRC may be used. Further, the present invention is
The present invention can be applied to not only the terminal device but also a base station device in a wireless communication system, a broadcast relay device attached to a satellite or a flying object, as in the case of the terminal device.

[0133]

As described above, according to the present invention, the FP
It is possible to eliminate the influence of a circuit failure due to a bit error generated in the GA configuration data due to noise on the wireless transmission path. Further, according to the present invention, even if the circuit failure is serious and the correct result cannot be output, the circuit configuration can be efficiently reconfigured by retransmitting the configuration data of the remainder arithmetic circuit for each modulus. It will be possible. Further, if the redundancy of the redundant residue number calculation circuit is high, the hardware of the FPGA may be wasted. However, the present invention is based on the S / N of the transmission line.
By adaptively setting the redundancy, an arithmetic circuit having the optimum redundancy can be efficiently realized on the FPGA. Further, according to the present invention, the dynamic range can be easily increased by newly adding the remainder arithmetic circuit of the signal processing circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a software defined radio device according to a conventional technique.

FIG. 2 is a configuration example of a packet of a link for wirelessly downloading software for a software defined radio system,
3 is a schematic diagram showing a configuration example of a packet of a link for transmitting information data.

FIG. 3 is a schematic diagram showing a configuration example of a packet of a link (uplink) transmitted from a terminal station to a base station by a modulator in which software is downloaded.

FIG. 4 is a schematic diagram showing an example of packet retransmission processing of a software defined radio system.

FIG. 5 is a block diagram showing a configuration example of an OFDM demodulation unit for MMAC.

FIG. 6 is a block diagram showing a configuration example of a spread spectrum demodulation unit for WCDMA.

FIG. 7 is a block diagram showing a configuration example of a 9-bit adder designed by LUT and CL of FPGA.

FIG. 8: 3 designed using LUT and CL of FPGA
FIG. 3 is a schematic diagram illustrating a configuration example of a × 2-bit multiplier.

FIG. 9 is a block diagram showing a configuration example of an arithmetic circuit designed by an LUT based on a truth table.

FIG. 10 is a schematic diagram showing an internal configuration of an example of FPGA.

FIG. 11 is a block diagram showing an internal configuration of an example of CLB.

FIG. 12 is a schematic diagram showing an example of the structure of CB.

FIG. 13 is a schematic diagram showing the configuration of an example of SB.

FIG. 14 is a schematic diagram showing an example of an FPGA layout when a certain logic circuit is realized on the FPGA.

FIG. 15 is a block diagram showing an outline of a layout of an arithmetic circuit by a normal binary arithmetic operation.

FIG. 16 is a block diagram showing an outline of a layout in the case where the calculation accuracy is expanded in a calculation circuit using a normal binary number calculation.

FIG. 17 is a schematic diagram used to explain a remainder number calculation.

FIG. 18 is a block diagram for comparing layout scales of circuits for realizing the same dynamic range.

FIG. 19 is a block diagram showing a layout of a configuration including a remainder number calculation circuit.

FIG. 20 is a block diagram showing a layout of a configuration of a normal binary number arithmetic circuit.

FIG. 21 is a block diagram showing a configuration example of a signal processing system using a remainder number calculation circuit.

FIG. 22 is a schematic diagram showing an example of conversion of numerical values from a residue number system to a normal binary number system.

FIG. 23 is a schematic diagram showing an example of redundant remainder number calculation and a layout of a calculation circuit.

FIG. 24 is a block diagram showing a configuration of an example of a signal processing circuit based on redundant remainder number calculation.

FIG. 25 is a block diagram showing a configuration of an example of a software defined radio system based on redundant remainder calculation.

FIG. 26 is a block diagram showing a configuration of an example of a software defined radio.

FIG. 27 is a block diagram showing a configuration of an example of a software defined radio that adaptively changes redundancy.

FIG. 28 is a block diagram showing a configuration of an example of an S / N measuring section.

FIG. 29 is a block diagram for explaining an S / N measuring unit.

FIG. 30 is a block diagram for explaining an S / N measuring unit.

FIG. 31 is a flowchart illustrating a batch retransmission process of configuration data.

[Fig. 32] Fig. 32 is a flowchart for describing divisional retransmission processing of configuration data.

FIG. 33 is a schematic diagram showing an example of a frame format of configuration data.

FIG. 34 is a flowchart illustrating a retransmission process when a CRC is added to each residue digit.

FIG. 35 is a schematic diagram showing a layout configuration example on an FPGA chip.

[Explanation of symbols]

23a-1, 23a-2, 23a-4 ... A signal processing circuit composed of a remainder arithmetic circuit corresponding to each method of the set of methods {3, 5, 7, 11}, 23b-1, 23b- Two
23b-3, 23b-4 ... A conversion circuit for converting a combination of different outputs of the arithmetic circuit of the remainder digit into a binary number, 23
c-1, 23c-2, 23c-3, 23c-4 ... A comparison circuit that compares the output of the conversion circuit with the value of the non-redundant dynamic range, 23d ... Outputs a result smaller than the non-redundant dynamic range A decoder for generating selection information for selecting a combination of moduli, 23e ... A multiplexer for selecting the output of the conversion circuit according to the selection information, 2
4b ... Radio for receiving configuration data, 24c ... Configuration database, 24e ... Software radio, 26g.
..S / N measuring device, 26h ... Redundancy determining unit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Harada             4-2-1 Kanaikitamachi, Koganei City, Tokyo Independent             Communications Research Institute (72) Inventor Masayuki Fujise             4-2-1 Kanaikitamachi, Koganei City, Tokyo Independent             Communications Research Institute F-term (reference) 5K004 AA08 JE03 JF00 JG01 JH00                 5K014 AA01 BA06 FA03 FA11 HA01                 5K022 DD01 EE01 GG01                 5K067 AA01 AA23 BB21 DD45 DD46                       EE02 EE10 GG01 GG11

Claims (38)

[Claims] 1. A terminal device, wherein a part or all of the hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired wireless communication system, by the received program data. , If the calculation result exceeds the non-redundant dynamic range, it is considered that a circuit failure has occurred, and if the calculation result exceeds the non-redundant dynamic range, the combination of surplus digits is selected and correct. A terminal device configured to output as a calculation result. 2. A terminal device, wherein a part or all of the hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired wireless communication system, by the received program data. , A combination of the remainder number calculating means configured for each remainder digit and having a redundant dynamic range, and the different remainder digits of the above-mentioned remainder number calculating means is generated, and the calculation result of the generated combination is converted into a binary number. A plurality of converting means, a determining means for determining whether or not the outputs of the plurality of converting means exceed a non-redundant dynamic range; and, in response to the determination result of the determining means, exceeding the non-redundant dynamic range. A terminal device comprising: selecting means for selectively outputting a combination of remainder digits in the case of no output as a correct calculation result. 3. The method according to claim 1 or 2, wherein the operation results of all combinations of the remainder digits are converted.
A terminal device requesting resending of program data of the remainder calculating means corresponding to all of the above-mentioned remainder digits if any value of the decimal number exceeds the non-redundant dynamic range. 4. The method according to claim 1 or 2, wherein the operation results of all combinations of the remainder digits are converted.
If any value of the decimal number exceeds the non-redundant dynamic range, the retransmission of the program data is requested for each residue digit corresponding to each modulus from the smallest modulus, and when the operation result does not exceed the non-redundant dynamic range, A terminal device that cancels a request to resend program data, assuming that a correct result can be output. 5. The method according to claim 1 or 2, when the state of the propagation path for transmitting the program data is poor, the redundancy of the dynamic range of the residue number computing means is increased, and the state of the propagation path is good. Is a terminal device for reducing the redundancy of the dynamic range of the remainder number calculating means. 6. The redundancy according to claim 5, wherein the redundancy of the dynamic range is increased when the S / N which is the ratio of the signal power to the noise power of the propagation path is low, while the S / N is increased.
A terminal device that adaptively decides to reduce redundancy when the value is high. 7. A terminal device, wherein a part or all of the hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired wireless communication system, by the received program data. , A remainder number calculating means composed of an arithmetic circuit configured for each remainder digit is provided, and an error detection code is decoded for each program data for each arithmetic circuit of the remainder number calculating means, and the error detection code is converted into program data. A terminal device that requests retransmission of only program data of a corresponding arithmetic circuit without configuring an arithmetic circuit in which a bit error is detected. 8. A terminal device, wherein a part or all of the hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired wireless communication system, by the received program data. , A remainder number calculating means including an arithmetic circuit configured for each remainder digit is provided, and in order to improve the calculation accuracy of the above-mentioned remainder number calculating means when the state of the propagation path becomes poor, A terminal device for receiving program data of a residue number calculation means having accuracy equivalent to an increment. 9. The terminal according to claim 1, 2, 7, or 8, wherein the program data of a portion requiring reliability is stored in a local database, and the program data of a portion whose function is frequently changed is wirelessly transmitted. apparatus. 10. The terminal device according to claim 1, 2, 7 or 8, wherein the logic circuit is an FPGA and the program data is configuration data. 11. A program data received in a base station device, wherein a part or all of hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired wireless communication system. By this, a remainder number calculation means with a redundant dynamic range is configured.If the calculation result exceeds the non-redundant dynamic range, it is considered that a circuit failure has occurred, and the combination of the remainder digits when it does not exceed is selected, A base station device that outputs a correct calculation result. 12. A program data received in a base station device, wherein a part or all of hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired wireless communication system. By the above, a combination of a remainder number calculating means which is configured for each remainder digit and has a redundant dynamic range and a different remainder digit of the above-mentioned remainder number calculating means is generated, and the calculation result of the generated combination is converted into a binary number. A plurality of converting means, a determining means for determining whether or not the outputs of the plurality of converting means exceed the non-redundant dynamic range, and the non-redundant dynamic range in response to the determination result of the determining means. A base station provided with a selection unit that selectively outputs a combination of remainder digits when the number does not exceed as a correct calculation result. Location. 13. The method according to claim 11 or 12, wherein the operation results of all combinations of the remainder digits are converted.
A base station apparatus that requests retransmission of program data of the remainder calculating means corresponding to all of the above-mentioned remainder digits if any value of the base number exceeds the non-redundant dynamic range. 14. The method according to claim 11 or 12, wherein the operation results of all combinations of the remainder digits are converted.
If any value of the decimal number exceeds the non-redundant dynamic range, the retransmission of the program data is requested for each residue digit corresponding to each modulus from the smallest modulus, and when the operation result does not exceed the non-redundant dynamic range, A base station device that cancels a request to resend program data, considering that a correct result can be output. 15. The method according to claim 11 or 12, when the state of the propagation path for transmitting the program data is poor, the redundancy of the dynamic range of the residue number calculating means is increased, and the state of the propagation path is good. Is a base station apparatus for reducing the redundancy of the dynamic range of the remainder number calculating means. 16. The redundancy according to claim 15, wherein the redundancy of the dynamic range is increased when the S / N ratio of the signal power and the noise power of the propagation path is low, while the S / N ratio is increased.
A base station device that adaptively decides to reduce redundancy when the value is high. 17. Program data received in a base station device, wherein a part or all of hardware is composed of programmable logic circuits, and program data for the logic circuits realizes a desired wireless communication system. According to the present invention, there is provided a remainder number calculation means composed of a calculation circuit configured for each remainder digit, and the error detection code is decoded for each program data for each calculation circuit of the above remainder number calculation means. A base station device that requests retransmission of only program data of a corresponding arithmetic circuit without configuring an arithmetic circuit in which a bit error is detected. 18. A program data received in a base station apparatus, wherein a part or all of hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired wireless communication system. According to the above, there is provided a remainder number calculating means composed of an arithmetic circuit configured for each remainder digit, and when the state of the propagation path deteriorates, a new addition precision is added to improve the calculation accuracy of the remainder number calculating means. A base station device for receiving program data of a residue number calculating means having accuracy equivalent to the increment of 19. The base according to claim 11, 12, 17 or 18, in which the program data of a portion for which reliability is required is stored in a local database, and the program data of a portion whose function is frequently changed is wirelessly transmitted. Station equipment. 20. The base station device according to claim 11, 12, 17 or 18, wherein the logic circuit is an FPGA and the program data is configuration data. 21. In a relay device in which a part or all of hardware is composed of a programmable logic circuit, and a program data for the logic circuit realizes a desired broadcasting system, If the calculation result exceeds the non-redundant dynamic range, it is considered that a circuit failure has occurred, and if the calculation result exceeds the non-redundant dynamic range, the combination of surplus digits is selected and correct calculation is performed. A relay device that outputs as a result. 22. In a relay device, wherein a part or all of hardware is composed of a programmable logic circuit, and a program data for the logic circuit realizes a desired broadcasting method, A plurality of units that are configured for each remainder digit and that generate a combination of the remainder number calculation means having a redundant dynamic range and different remainder digits of the above-mentioned remainder number calculation means and convert the calculation result of the generated combination into a binary number. Conversion means, a determination means for determining whether or not the outputs of the plurality of conversion means exceed a non-redundant dynamic range, and a non-redundant dynamic range not exceeded in response to the determination result of the determination means. A relay device comprising: a selection unit that selectively outputs the combination of the remainder digits in this case as a correct calculation result. 23. The calculation result according to claim 21 or 22, wherein the calculation results of all combinations of the remainder digits are converted.
A relay device requesting retransmission of the program data of the residue number calculating means corresponding to all of the residue digits if any value of the decimal numbers exceeds the non-redundant dynamic range. 24. The calculation result according to claim 21 or 22, wherein the calculation results of all combinations of the remainder digits are converted.
If any value of the decimal number exceeds the non-redundant dynamic range, the retransmission of the program data is requested for each residue digit corresponding to each modulus from the smallest modulus, and when the operation result does not exceed the non-redundant dynamic range, A relay device that cancels a request to resend program data, assuming that a correct result can be output. 25. In claim 21 or 22, when the state of the propagation path for transmitting the program data is poor, the redundancy of the dynamic range of the remainder calculation means is increased, while the state of the propagation path is good. Is a relay device for reducing the redundancy of the dynamic range of the remainder number calculating means. 26. In claim 25, the redundancy of the dynamic range is increased when the S / N which is the ratio of the signal power to the noise power of the propagation path is low, while the S / N is increased.
A relay device that adaptively decides to reduce redundancy when the value is high. 27. In a relay device, wherein a part or all of hardware is composed of a programmable logic circuit, and the program data for the logic circuit realizes a desired broadcasting system. A remainder number calculating means including an arithmetic circuit configured for each remainder digit is provided, and an error detection code is decoded for each program data for each arithmetic circuit of the remainder number calculating means, and the error detection code is used to bit the program data. A relay device that does not configure an arithmetic circuit in which an error has been detected and requests retransmission of only the program data of the relevant arithmetic circuit. 28. In a relay device in which a part or all of hardware is composed of a programmable logic circuit and a desired broadcasting system is realized by program data for the logic circuit, A remainder number calculating means including an arithmetic circuit configured for each remainder digit is provided, and when the state of the propagation path deteriorates, the calculation accuracy of the above-mentioned remainder number calculating means is increased to increase newly added calculation accuracy. A relay device for receiving program data of a residue number calculating means having accuracy equivalent to minutes. 29. The relay according to claim 21, 22, 27, or 28, wherein program data of a portion requiring reliability is stored in a local database, and program data of a portion whose function is frequently changed is wirelessly transmitted. apparatus. 30. The relay device according to claim 21, 22, 27 or 28, wherein the logic circuit is an FPGA and the program data is configuration data. 31. A communication method, wherein a part or all of hardware is composed of a programmable logic circuit, and a desired wireless communication system or a desired broadcasting system is realized by program data for the logic circuit. The receiving step of receiving the data, the step of configuring the remainder number calculating means which is configured for each remainder digit by the received program data and has a redundant dynamic range, and the different remainder digits of the remainder number calculating means. A conversion step of generating a combination and converting the operation result of the generated combination into a binary number; a determination step of determining whether or not the converted operation result exceeds a non-redundant dynamic range; Correct the result of the combination of the remainder digits when the range is not exceeded. Communication method comprising the selection step of outputting the 択的. 32. The calculation result according to claim 31, wherein the calculation results of all combinations of the remainder digits are converted.
A communication method for requesting resending of program data of the remainder calculating means corresponding to all the above-mentioned remainder digits if any value of the decimal number exceeds the non-redundant dynamic range. 33. The calculation result according to claim 31, wherein the calculation results of all combinations of the remainder digits are converted.
If any value of the decimal number exceeds the non-redundant dynamic range, the retransmission of the program data is requested for each residue digit corresponding to each modulus from the smallest modulus, and when the operation result does not exceed the non-redundant dynamic range, A communication method that cancels a request to resend program data, assuming that a correct result can be output. 34. In claim 31, when the state of the propagation path for transmitting the program data is poor, the redundancy of the dynamic range of the remainder computing means is increased, while when the state of the propagation path is good, A communication method for reducing the redundancy of the dynamic range of the remainder calculation means. 35. The redundancy of the dynamic range is increased according to claim 34, when the ratio of the signal power and the noise power of the propagation path is low, and the redundancy of the dynamic range is increased.
A communication method that decides adaptively so as to reduce redundancy when the value is high. 36. A communication method, wherein a part or all of hardware is composed of a programmable logic circuit, and a desired wireless communication system or a desired broadcasting system is realized by program data for the logic circuit. The program data for each arithmetic circuit of the remainder number calculating means includes a receiving step of receiving data, and a step of forming a remainder number calculating means composed of an arithmetic circuit configured for each remainder digit by the received program data. A communication method in which an error detection code is decoded for each time, and a retransmission of only the program data of the corresponding operation circuit is requested without configuring an operation circuit in which a bit error is detected in the program data by the error detection code. 37. A communication method, wherein a part or all of hardware is composed of a programmable logic circuit, and a desired wireless communication system or a desired broadcasting system is realized by program data for the logic circuit. It comprises a receiving step of receiving data, and a step of constructing a remainder number calculating means composed of an arithmetic circuit configured for each remainder digit by the received program data, and when the state of the propagation path deteriorates, A communication method for receiving program data of a remainder number calculation means having an accuracy corresponding to an increase in calculation precision newly added to increase the calculation accuracy of the remainder calculation means. 38. The communication method according to claim 31, 36 or 37, wherein the program data of a portion requiring reliability is stored in a local database, and the program data of a portion whose function is frequently changed is wirelessly transmitted.