JP2003069411A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit that outputs a signal with a multi-value level that decreases jitter in an output signal and quickens a signal transfer cycle. SOLUTION: In the output circuit of a simultaneous bidirectional interface at which a tri-state level potential appears at its output terminal, a series connection comprising two switch transistors M1, M2 is connected between an output node N1 of a buffer circuit BUF2 and a prescribed level (ground), and a series connection of switch transistors M3, M4 is connected between an output node N2 and a prescribed level (power supply potential) respectively, an internal signal inverse of IN is given to control terminals of the switch transistors M2, M4 and a potential Vpad of an output terminal PO is given to control terminals of the other switch transistors M1, M3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing delay variation of an output signal in a signal output circuit in a semiconductor integrated circuit and further in an output circuit capable of multilevel output of three or more values, and more particularly to simultaneous bidirectional input / output. The present invention relates to a technique useful when applied to a circuit.

[0002]

2. Description of the Related Art In a simultaneous bidirectional interface capable of transmitting and receiving signals at the same time, for example, when outputting a signal changing from a low level to a high level, an external device connected to the input / output terminal is connected. The potential appearing at the input / output terminal varies depending on the output state. For example, when the output of the external device is high level, the potential of the input / output terminal changes from middle level to high level, but when the output of the external device is low level, the potential of the input / output terminal is changed from low level to middle level. Change to a level.

[0003]

As described above, in the simultaneous bidirectional interface, the voltage of the input / output terminal varies depending on the output state of the external connection device. When the output state of is at a high level, various parasitic capacitances connected to the output terminal are charged to some extent,
When the output state of the externally connected device is low level, the parasitic capacitance is in a discharged state.

However, in the conventional simultaneous bidirectional interface, the same output operation is performed only on the basis of the internal signal regardless of the output state of the external connection device. Therefore, the output signal rises depending on the output state of the external connection device. The time and fall time have changed, and as a result,
There is a problem that delay variation (jitter) of the output signal increases.

For example, as shown in FIG. 7, when the output state of the externally connected device is high level, the output circuit (output M
OS QP1, QN1) drive to output potential Vout
Is changed from the middle level to the high level, the load capacitance C0 parasitic on the output terminal is also charged from the externally connected device via the transmission line, so that the rise time of the output signal becomes short.

On the other hand, as shown in FIG. 8, when the output state of the externally connected device is driven to the low level and the output circuit is driven to change the output potential Vout from the low level to the middle level, the load capacitance CO is charged. This is performed only by the circuit, and since the current also flows through the transmission line L1 to the external connection device side, the rise time of the output signal becomes long.

Such a phenomenon occurs not only in the simultaneous bidirectional interface but also in a circuit which outputs a multilevel signal based on an internal signal of a plurality of bits. That is, for the output operation based on any one bit of the m-bit internal signal, the other (m
Since there are 2 ^(m-1) output states based on -1) bits, the delay of the output signal is different for each state.

An object of the present invention is to reduce variations in the transmission delay time of an output signal in an output circuit which outputs a multi-level signal, and to reduce the number of signal transfer cycles in a semiconductor integrated circuit equipped with such an output circuit. It is to speed up. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in a semiconductor integrated circuit having an output circuit that outputs potentials of M levels (M is an integer of 3 or more), delay correction means for correcting the operation delay of the output circuit according to the signal level of the output terminal. It is equipped with. Specifically, in an output circuit in which a buffer circuit is provided before the output transistor, two switch transistors are connected in series between the output node of the buffer circuit and a predetermined potential (for example, power supply potential), and This is realized by inputting an internal signal to the control terminal (for example, the gate terminal of MOSFET) of the switch transistor and the potential of the output terminal to the control terminal of the other switch transistor.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of an output circuit of a simultaneous bidirectional interface suitable for applying the present invention. The output circuit 100 is an output circuit of a simultaneous bidirectional interface, and an input circuit (not shown) is also connected to the input / output pad PO which is an output terminal thereof. In FIG. 1, QP1 is a push-side P-channel output MOSFET that constitutes a push-pull output stage.
(Hereinafter referred to as MOS), QN1 is an N-channel output MOS on the pull side of the same output stage, BUF1 to BUF5 are buffer circuits for transmitting the internal signal IN to the output MOSs QP1 and QN1, and 20 is the potential of the input / output pad PO. It is a level feedback circuit as delay correction means for feeding back Vpad to correct the transmission delay of the buffer circuits BUF1 to BUF4.

In the simultaneous bidirectional output circuit 100,
Even if the level of the internal signal IN is constant, the signal level appearing at the input / output pad PO varies depending on the output state of the connection partner. That is, the internal signal I of the output circuit 100
When N is at low level and the push-side output MOS QP1 is turned on, the pad potential Vpad appearing at the input / output pad PO is at high level when the other output circuit also has the push-side output PMOS turned on. become.
On the other hand, if the pull-side output NMOS is turned on in the destination output circuit when the output MOS QP1 is turned on, the output MOS QP1, the transmission line, and the pull-side output MOS of the destination output circuit A current flows through the path, and the pad potential Vpad becomes the middle level. Similarly, when the internal signal IN of the output circuit 100 is at high level, the pad potential Vpad becomes low level or middle level depending on the output state of the partner output circuit.

Therefore, even when the internal potential IN is changed from the high level to the low level and the same rise output is generated in which the pad potential Vpad rises, when the pad potential Vpad changes from the low level to the middle level (hereinafter, referred to as “L”). → M "pattern) and a case where the middle level is changed to a high level (hereinafter referred to as" M → H "pattern). On the contrary, when the internal signal IN transits from the low level to the high level, the pad potential Vpad changes from the middle level to the low level (hereinafter, “M →
There is a case where the pattern changes from a high level to a middle level (hereinafter referred to as an “H → M” pattern).

The level feedback circuit 20 includes switch MOSs M1 and M2 for changing the signal delay of the buffer circuits BUF1 and BUF2 for transmitting the internal signal IN to the push-side output MOS QP1 and pull-side output MOS.
Buffer circuit BUF for transmitting internal signal IN to QN1
3, switch MOSM for changing the signal delay of BUF4
3 and M4.

The switch MOSs M1 and M2 are P-channel type and N-channel type MOSFETs, the drain terminals of which are commonly coupled to each other, and the switch MOSs on the P-channel side.
The source terminal of M1 is connected to the output node N1 of the buffer circuit BUF2, the source terminal of the switch MOS M2 on the N-channel side is connected to the second power supply potential VSS2, and the gate terminal of the switch MOS M1 on the P-channel side is input / output pad. The gate terminal of the switch MOS M2 on the N-channel side is connected to PO at the output node N3 of the buffer 5.

The switch MOSs M1 and M2 are both turned on when the pad potential Vpad makes a transition in the "L → M" pattern, so that the charges are extracted from the node N1. That is, in the initial stage before the transition of the pad potential Vpad, the potential of the input / output pad PO is at the low level, the switch MOS M1 is in the on state, and the potential of the node N3 is at the low level, so the switch MOS M2 is in the off state. is there. Next, when the internal signal IN transitions and the potential of the node N3 changes to high level, the output of the buffer circuit BUF2 is pulled down to low level, and at the same time, the switch MOS M2 is turned on and the node from the switch MOS M1, M2 side is also changed. Pull down the potential of N1.

FIG. 2 shows potential waveform diagrams of the node N1 in two rise output patterns. With the above operation, when the pad potential Vpad transits in the “L → M” pattern, as shown in the waveform W1 of FIG.
The potential of is rapidly changed to low level.

On the other hand, when the pad potential Vpad makes a transition in the “M → H” pattern, the switch MOS M1 is not turned on from the initial stage to the transition, and the node N1.
Since the potential of the node changes only by driving the buffer circuit BUF2, the potential of the node N1 transitions to the low level relatively gently as shown by the waveform W2 in FIG.

As a result, the timing at which the next-stage buffer circuit BUF1 connected to the node N1 is driven is "L".
The “M → H” pattern is delayed by the delay time T1 than the “→ M” pattern. The length of this delay T1 is switch M
Since it can be adjusted to an appropriate length by adjusting the driving force (for example, the gate width) of the OS M1 and M2, for example, it should be adjusted to a value that eliminates the delay variation of the output signal based on the output state of the other side. Is possible.

Further, the pad potential Vpad drops "M
In the case of the "→ L" pattern or the "H → M" pattern, one of the switch MOSs M1 and M2 is kept in the off state, and the switch MOSs M1 and M2 have no effect.

FIG. 3 is a diagram showing two patterns of output waveforms at the time of rise output in the output circuit 100 of the first embodiment. Both waveforms show the case where the internal signal IN is switched at the same timing.

As described in the item of the problem, in the output circuit 100 of FIG. 1, when the level feedback circuit 20 is not provided, for example, in the case of the rise output, the “L → M” pattern is more preferable than the “M → H” pattern. , It is necessary to charge the output load capacitance from the output circuit 100 more.
The output waveform W3 of the “L → M” pattern has a longer rise time of the signal than the output waveform W4 of the “H” pattern.

On the other hand, due to the delay action of the switch MOSs M1 and M2 of the level feedback circuit 20, the transmission time until the internal signal IN is transmitted to the P channel output MOS QP1 is "M" rather than "L → M" pattern.
The → H ”pattern is delayed by the delay time T1. On the other hand, the signal for turning off the N-channel output MOS QN1 propagates at the same timing in the “L → M” pattern and the “M → H” pattern.

Therefore, in the case of the "L → M" pattern,
While the N-channel output MOS QN1 is turned off and the P-channel output MOS QP1 is turned on at the same time, in the case of the “M → H” pattern, the delay time T1 is set after the N-channel output MOS QN1 is turned off. After that, the P-channel output MOS QP1 turns on. When the delay time T1 is sufficiently large, the input / output pad PO in the “M → H” pattern is driven only by the current supplied from the external device through the transmission line, and the potential of the input / output pad PO is at a high level. P channel output MOS QP
1 turns on. Therefore, the waveform of the “M → H” pattern becomes gradual and becomes equivalent to the “L → M” waveform. As a result, the delay times are the same in both transition states.

That is, in the waveform W4, the timing S at which the intermediate voltage Vref2 between the middle level and the high level is reached
1 becomes the same as the timing S2 when the intermediate voltage Vref1 of the low level and the middle level in the waveform W3 becomes the same, and the delay variation (jitter) of the output signal is reduced between the “M → H” pattern and the “L → M” pattern. It Further, since the rising and falling slopes of the output signal do not vary, there is an effect that the reflection noise of the output signal can be reduced.

In the level feedback circuit 20, the switch MOS M3 associated with the pull-side output MOS QN1
Regarding M4, the above-mentioned switch MOS M1, M2
With the configuration in which the potential is symmetrical with respect to positive and negative, the same operation can be performed.

According to the output circuit 100 of the first embodiment, the output delay can be corrected with a relatively small structure.
It is possible to reduce the jitter of the output signal and the reflection noise without increasing the chip occupying area and the power consumption so much.

FIG. 4 is a circuit diagram showing a second embodiment of the input / output circuit of the simultaneous bidirectional interface. In the output circuit of the second embodiment, a plurality of signal paths of the internal signal IN connected to the gate terminals of the output MOSs QP1 and QN1 are provided with different signal delays, and the potential of the output terminal and the level of the internal signal IN are set. By appropriately switching the signal path for transmitting the internal signal IN, the rise time of the output signal is made uniform to reduce the jitter of the output signal, as in the first embodiment.

In FIG. 4, reference numeral 200 denotes an output circuit, 220
Is an input circuit, QP1 and QN1 are P-channel output MOS and N-channel output MOS constituting a push-pull type output stage, BUF1, BUF3, BUF5 are buffer circuits, 31-34, 36-39 are delay devices, and SEL1, SE.
L2 is a selector circuit, 40 and 41 are NAND circuits and OR circuits that generate a selection signal with a predetermined logic, SA1 and SA2.
Is a sense amplifier as a detection amplifier of the feedback means for detecting the pad potential appearing at the input / output pad PO, and SEL3 is an input selector circuit for taking in an input signal internally, BU
F10 is an input buffer circuit that internally transmits an input signal.

The sense amplifiers SA1 and SA2 detect the pad potential Vpad for correcting the signal delay of the output circuit and the pad potential Vpad for internally inputting the output signal from the output circuit of the other side. Are configured to do at the same time. One sense amplifier SA1 compares the reference voltage Vref1 between the middle level and the low level with the pad potential and outputs the comparison result. That is,
A high level is output when the pad potential is a high level, and a low level is output when the pad potential is a middle level or a low level.

The other sense amplifier SA2 is configured to compare a reference voltage Vref2 between the high level and the middle level with the pad potential and output the comparison result similarly. Then, these sense amplifiers SA1 and SA2
It is possible to detect whether the pad potential is at a high level, a middle level, or a low level based on both detection results.

The selector SEL3 for input signal has a sense amplifier S when the internal signal IN for output is low level.
The signal on the A2 side is selected and input to the inside when the internal signal IN is at a high level. As a result, the input signal from the connection partner side obtained by subtracting the output signal of the output circuit 200 from the pad potential can be fetched.

In the output circuit 200, the path for transmitting the internal signal IN to the gate terminal of the push-side output MOS QP1 is branched into two signal paths PAS1 and PAS2 on the way. These two signal paths PAS1, PAS
2 are provided with different numbers of delay stages, and are configured to have different signal transmission delays. Then, by the selector circuit SEL1, either signal path P
AS1 and PAS2 are configured to be selected.
The selector circuit SEL1 is controlled by a signal of NAND of the potential of the node N5, which is the inverted output of the internal signal IN, and the potential of the output node N6 of the sense amplifier SA1.

Specifically, the potential of the node N6 is high level (pad potential is middle level or high level), and the potential of the node N5 is high level (internal signal IN is low level).
The signal path PAS1 side is selected when, and the signal path PAS2 side is selected otherwise. Also, NAND
The operation delay of the circuit 40 and the selector circuit SEL1 is made smaller than the transmission delay of the signal buses PAS1 and PAS2.
As a result, the selector circuit SEL1 is switched at a timing earlier than the timing at which the internal signal IN passes through the selector circuit SEL1. Therefore, when the internal signal IN transits from the high level to the low level or vice versa, the path through which the rising or falling signal of the internal signal IN passes is the path before the transition of the voltage and the pad potential after the transition of the internal signal IN. It will be decided based on the voltage.

Under the above conditions, four transition patterns of the pad potential Vpad, the "M → H" pattern, and the "L → M" pattern.
When the logics of the nodes N6 and N7 and the NAND circuit 40 are verified with respect to the pattern, the “M → L” pattern, and the “H → M” pattern, the signal path PAS1 is selected in the “M → H” pattern. It can be seen that the signal path PAS2 is selected in the remaining three patterns.

Similarly, pull-side output MOS QN1
For the signal paths PAS3 and PAS4 according to the above, “M → L” among the four transition patterns of the pad potential Vpad.
The signal path PAS3 is selected in the case of the pattern, and the signal path PAS4 is selected in the remaining three patterns, that is, the “M → H” pattern, the “L → M” pattern, and the “H → M” pattern. .

According to the above configuration, when there is a transition pattern (“M → H” and “M → L” pattern) in which the rise time and the fall time of the output signal are shortened when there is no level feedback action. , Output MO by switching signal path
Since the transmission delay of the internal signal IN transmitted to one of S QP1 and QN1 is increased, the delay variation of the output signal is reduced as in the case of the first embodiment.

Further, in the input / output circuit of the second embodiment,
Since the delay amount can be set independently for each signal path, there is also an effect that the correction amount of the transmission delay according to the pad potential can be set within a large variable range without affecting other circuits.

Further, according to the input / output circuit of the second embodiment, the sense amplifiers SA1 and SA2 have both a level detection for feedback control of the output circuit 200 and a level detection for signal input. Therefore, the area occupied by the circuit and the power consumption can be reduced accordingly.

FIG. 5 is a circuit diagram showing a third embodiment of the input / output circuit of the simultaneous bidirectional interface. The input / output circuit of the third embodiment has a pad potential Vpad and an internal signal I.
By increasing / decreasing the driving power of the output MOS according to the level of N, the rise time and the fall time of the output signal are made constant irrespective of the pad potential Vpad to reduce the jitter of the output signal and the output reflected wave. And is intended.

In FIG. 5, output MOS QP1, QN
1. The buffer circuits BUF1 to BUF5 are the same as those shown in FIG. 1, and the input circuit 220 is the same as that shown in FIG. In FIG. 5, QP2 is a P channel output MO for temporarily increasing the output driving force on the push side.
S and QN2 are N-channel output MOS for temporarily increasing the output driving force on the pull side, and 50 is a pad potential Vpa.
output MOS QP2 according to the level of d and the internal signal IN
Circuit for determining the operation of the
Operation pulse PU for limiting the drive time of P2 to a predetermined length
A logic circuit for generating LS1, 55 is a pad potential Vpad
And a NAND circuit 56-58 for determining the operation of the output MOS QN2 according to the level of the internal signal IN.
Operation pulse P for limiting the driving time of QN2 to a predetermined length
It is a logic circuit that generates ULS2.

According to the circuit configuration described above, the node N
When the potential of the node N5 transits from the low level to the high level while the potential of 6 is at the low level, the NAND circuit 53 outputs the low-level operation pulse PULS1 for a predetermined period.
Is output. That is, of the four transition patterns of the pad potential Vpad, the output MOS QP2 is driven for a predetermined time when the pattern is the "L → M" pattern and is not driven when the pattern is the other three patterns.

By adjusting the operation delay of the NAND circuit 53 and the transmission delay of the buffer circuits BUF1 and BUF2 to be the same, the operation timing of the output MOS QP1 and the output MOS based on the operation pulse PULS1.
The operation timing of QP2 is made to match.

FIG. 6 is a diagram showing output waveforms of two patterns at the rise output in the output circuit 300 of the third embodiment. Both waveforms W7 and W8 are internal signals IN
Shows the case of switching at the same timing. As described in the item of the problem, at the time of the rise output, the amount of charge to the output load capacity becomes larger in the case of the “L → M” pattern than in the case of the “M → H” pattern. When the driving force of the MOS is equal, the waveform W
As shown by the broken line of 7, the rise time is longer in the “L → M” pattern.

However, in the case of the "L → M" pattern, the auxiliary output MOS QP2 is simultaneously turned on and the charging of the output load capacitance is accelerated, so that the rise time of the signal can be shortened. Further, this rise time can be made equal to the rise time of the “M → H” pattern by adjusting the driving force (for example, the gate width) of the output MOS QP2 and the pulse width of the operation pulse PULS1.

When the output MOS QP2 is turned on, the output MOS QP2 is turned off in a predetermined period indicated by the pulse width of the operation PULS1, so that the output impedance of the output MOS QP2 does not become inconsistent thereafter.

The logic circuits 55 to 58 for generating the pull-side output MOS QN2 and its operation pulse PULS2 perform the same operation when the pad potential Vpad transits in the "H → M" pattern.

As described above, according to the input / output circuit of this embodiment, the output state of the connection partner, that is, the pad potential V
Since the rise time and the fall time of the output signal can be made uniform regardless of the pad, it is possible to reduce variations in the delay time of the output signal. In addition, since the rising and falling slopes of the output signal do not vary, it is possible to reduce the reflection noise of the output signal.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the embodiment, the output circuit that generates a three-value level output potential has been described, but the present invention is also applicable to a multi-value level output circuit having four or more levels. That is, when the output circuit of the second embodiment is applied to an N-value level (N is an integer of 4 or more) output circuit, the rise output transition pattern is (N-1).
Therefore, by providing (N-1) signal paths having a transmission delay suitable for each pattern and selecting a signal path for transmitting an internal signal according to each transition pattern, the delay variation of each transition pattern Can be reduced.

When the output circuit of the third embodiment is applied to an N-value level output circuit, a plurality of output MOSs suitable for each output transition pattern are provided on the push side and the pull side, respectively. -1) By selecting an output MOS to be auxiliary driven for a predetermined time according to each transition pattern,
Signal transitions and rising and falling slopes can be aligned with each transition pattern.

In the above description, the output circuit of the simultaneous bidirectional input / output interface, which is the field of application which is the background of the invention made mainly by the present inventor, has been described. However, the present invention is not limited thereto, and for example, ,
It can be widely used for an output circuit that outputs a signal of three or more values in one direction, an output circuit that exchanges signals with other blocks in the same semiconductor chip, and the like.

[0051]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, in an output circuit that outputs a signal at three or more voltage levels, the signal delay can be made constant and the delay variation of the output signal can be reduced regardless of the transition of the output potential. There is an effect. There is also an effect that the signal waveform becomes constant and the reflection noise of the output signal can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an output circuit of a simultaneous bidirectional interface suitable for applying the present invention.

FIG. 2 is a waveform diagram showing the potential of a node N1 in FIG. 1 at the time of rise output.

FIG. 3 is a diagram showing an output waveform of the output circuit of FIG. 1 at the time of rise output.

FIG. 4 is a second output circuit of the simultaneous bidirectional interface.
It is a circuit diagram which shows an Example.

FIG. 5 is a third output circuit of the simultaneous bidirectional interface.
It is a circuit diagram which shows an Example.

6 is a diagram showing an output waveform of the output circuit of FIG. 5 at the time of rise output.

FIG. 7 is a conceptual diagram illustrating the operation of the simultaneous bidirectional input / output circuit, which is when the output potential transits from the middle level to the high level.

FIG. 8 is a conceptual diagram illustrating the operation of the simultaneous bidirectional input / output circuit, which is when the output potential transits from a low level to a middle level.

[Explanation of symbols]

20 level feedback circuit 31-34, 36-39 Delay device 100 output circuit 200,300 output circuit 220 input circuit BUF1 to BUF5 buffer circuit M1 to M4 switch MOS PAS1 to PAS4 signal paths PO input / output pad SA1, SA2 sense amplifier SEL1, SEL2 selector circuit QP1, QP1 output MOS QP2, QN2 auxiliary output MOS

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Claims (5)

[Claims] 1. A semiconductor integrated circuit having an output circuit for outputting potentials of M levels (M is an integer of 3 or more), wherein an operation delay of the output circuit is corrected according to a signal level of the output terminal. A semiconductor integrated circuit comprising delay correction means. 2. The output circuit includes an output transistor that receives an internal signal at a control terminal and injects or extracts electric charge from the output terminal, and a buffer circuit that transmits the internal signal to the control terminal of the output transistor. 2. The semiconductor integrated circuit according to claim 1, wherein the delay correction means is configured to inject or extract electric charge into or from an output node of the buffer circuit based on the potential of the output terminal and the level of the internal signal. circuit. 3. The delay compensating means has two switch transistors connected in series between an output node of the buffer circuit and a predetermined potential, and the output terminal is provided as a control terminal of one of the switch transistors. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is connected and the internal signal is input to the control terminal of the other switch transistor. 4. The output circuit has a plurality of output transistors that drive the output terminal in the same positive or negative direction, and a detection amplifier that detects the signal level of the output terminal by comparing it with a reference voltage. 2. The semiconductor integrated circuit according to claim 1, wherein the delay correction means is configured to change a target or a number of the plurality of output transistors to be operated based on a detection result of the detection amplifier. circuit. 5. The output circuit includes a plurality of signal paths for transmitting an internal signal to the output stage with different delays, a selection means for selecting one of the plurality of signal paths, and a signal at an output terminal. A detection amplifier that detects the level by comparing it with a reference voltage is provided, and the delay correction means is configured to change a signal path through which an internal signal is transmitted based on a detection result of the detection amplifier. The semiconductor integrated circuit according to claim 1, wherein: