JP2003069018A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a sustaining voltage is enhanced without changing the cell size of a fundamental structure, whose turn-off time is shortened and which can be operated at high speed. SOLUTION: A plurality of first grooves 9 arranged in parallel to each other are formed on the surface (one main face) of an n-type drain region 2 formed on an n<+> substrate region 1. First insulating films 5 and first MOS electrodes 4 composed of p<+> polysilicon are formed inside the first grooves 9 so as to be insulated from the drain region 2. Respective p-type gate regions 8 are formed so as to come into contact with respective ends in the longitudinal direction of the first grooves 9. Second grooves 12 which make the first adjacent grooves 9 communicate with each other make the first grooves 9 alternately communicate with each other in positions displaced to the direction of any end from the center in the longitudinal direction of the first grooves 9. Source regions 3 as heavily doped n<+> regions are formed in parts coming into contact with the second grooves 12 in near parts from the gate regions 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for a vertical power device having a plurality of unit cells arranged in parallel.

[0002]

2. Description of the Related Art As a background art of the present invention, Japanese Patent Application Laid-Open No. 8-46192 filed by the present applicant is cited. 5 and 6 are structural views of the semiconductor device cited from the above publication. It should be noted that reference numerals and names of parts and the like in the drawings are appropriately changed for description. FIG. 5 is a surface view for explaining the basic structure, and FIG. 6 is a sectional view.

Reference numeral 51 in the above-mentioned drawing indicates an n + type substrate region,
52 is an n-type drain region, 53 is an n + type source region, 54 is a MOS type electrode, and 55 is an insulating film. MOS
The mold electrode 54 is made of high-concentration p + type polysilicon. 6
A drain electrode 1 is in ohmic contact with the substrate region 51. Reference numeral 63 denotes a source electrode which makes ohmic contact with the source region 53 and further with the MOS electrode 54. That is, the MOS electrode 54 is fixed at the source potential. Therefore, the MOS electrode 54 and the insulating film 55
Are collectively referred to as a fixed potential insulated electrode 56.

The cross-sectional structure of the fixed potential insulated electrode 56 is
For example, the side walls are formed in substantially vertical grooves like a letter "U", and these grooves are arranged in parallel and formed in a stripe shape. The "dashed line" in FIG. 6 indicates the presence of the fixed potential insulated electrode 56 in the depth direction of the paper surface, as can be seen from the relationship with FIG. Further, the drain region 52 sandwiched between the fixed potential insulating electrodes 56 is called a channel region 57.

In addition, the source region 53 is in contact with the insulating film 55.
A p-type gate region 58 is present apart from. In FIG. 6, reference numeral 68 denotes an electrode which makes ohmic contact with the gate region 58 and is called a gate electrode. Further, two source regions 53 are formed in the unit cell region surrounded by the two gate regions 58 and the two fixed potential insulating electrodes 56. These two source regions 53 are symmetrically arranged so as to have a predetermined distance from the portions that are equidistant from the two gate regions 58. Reference numeral 60 is an interlayer insulating film.

In this device, for example, the source electrode 63 is set to the ground potential (0 V), and the drain electrode 61 is used by applying an appropriate positive potential via an inductive load such as a motor. A mechanism in which a positive potential is applied to the gate electrode 68 to change the element from the conductive state to the cutoff state will be described.

In the conductive state, a gate potential higher than the source potential is applied, and the pn junction composed of the p-type gate region 58, the peripheral n-type drain region 52 and the channel region 57 is forward biased. This forward bias causes the gate region 58 to drain region 52 and channel region 57.
The holes are injected into the drain region 52 and the channel region 57 to increase the conductivity, and the electron current which is a component of the drain current flows from the source region 53 to the substrate region 51 with low resistance.

When the potential of the gate electrode 68 is set to ground (0 V) or a negative potential in order to turn off from this conductive state, excess holes in the drain region 52 and the channel region 57 flow into the gate region 58, The hole concentration gradually decreases from the vicinity of the gate region 58. Then, in the drain region 52, excess holes that are located relatively far from the gate region 58 also move to the channel region 57 having a low potential, and the holes in the drain region 52 are depleted.

Then, the resistance of the drain region 52 gradually increases, but when an inductive load such as a motor is connected to the drain electrode 61, the inductive load itself has the property of holding a current value. Therefore, as the resistance of the drain region 52 increases, the potential of the drain electrode 61 also increases.

Then, when a depletion region spreads in the drain region 52 and carriers travel in a high electric field applied to the drain region 52, a new pair of carriers is generated. Of the carriers generated in this drain region 52,
The electrons make up the electron flow as they are. On the other hand, the holes move to the channel region 57 in the opposite direction to the electron flow path, pass through the interface of the fixed potential insulating electrode 56, and are discharged to the gate region 58. At this time, if the amount of holes generated in the drain region 52, which increases with the increase of the drain potential, becomes equal to the amount of holes discharged to the gate region 58, a sustain operation occurs at the drain potential. .

However, in the above conventional element structure,
The breakdown due to the sustain operation that is known in a normal bipolar transistor does not occur. This is because there is no P-type region between the source region 53 through which the electron flow flows and the substrate region 51 in the above-described conventional element structure. Therefore, even if the electron flow is concentrated on one source region 53,
Since the resistance increases due to the temperature increase in that portion, the electron flow becomes difficult to flow, the electron flow flows from another source region 53 having a relatively low temperature and low resistance, and eventually the electron flow is an arbitrary source region 53. This is because the so-called negative feedback is applied, which means that you do not concentrate on the.

That is, in a semiconductor chip having a plurality of conventional element structures formed, during a sustain operation, an electron current flows in the entire region where the conventional element structure is formed. When this conventional element structure is used in an inductive load circuit for driving a motor or the like, this property is due to an increase in drain voltage generated by an induced electromotive force at the time of turn-off, such as a guard ring formed in the same semiconductor chip. This is an advantage that the burden on the pressure resistant structure can be avoided.

Further, by appropriately setting the unit cell size of the conventional structure, the sustain voltage is changed from the predetermined voltage applied to the drain electrode 61 when the conventional element is in the cutoff state to the breakdown voltage of the guard ring or the like. It can be designed to any voltage up to the breakdown voltage of the structure. For example, in the conventional device structure, when the unit cell size is reduced, the density of the source regions 53 per unit area is increased, so that the density of electron flow flowing in each source region 53 is decreased and the drain region 52 is also reduced. Of these, the distance from the gate region 58 to the most distant portion is short, so that the hole extraction speed is high. That is, when the unit cell size is reduced, the generation of pairs of carriers is suppressed and the generated holes are expelled, so that the sustain voltage becomes higher.

[0014]

However, if the unit cell size is made too small in order to increase the sustain voltage in the conventional device structure, the proportion of holes injected from the gate region 58 into the source region 53 in the conductive state. Becomes higher, the conductivity of the drain region 52 is not improved, and the current gain is reduced. As described above, the conventional structure has a problem in that the sustain voltage cannot be increased while maintaining other characteristics.

As described above, in the conventional element, when the drain electrode 61 is connected to an inductive load such as a motor, the inductive load itself has a property of holding a current value, and therefore the drain The potential of the drain electrode 61 rises as the resistance of the region 52 rises. The electron flow flowing from the source region 53 to the substrate region 51, whose current value is maintained by this inductive load, always tries to flow in a path having a small resistance, so that a transient state in which holes are discharged from the vicinity of the gate region 58. In the above, in the drain region 52, a portion farthest from the two gate regions 58 where holes remain until the end, that is, a portion equidistant from the two gate regions 58 flows.

From this, in the conductive state, the two gate regions 58 and the two fixed potential insulated electrodes 56 surrounded by the two gate regions 58 are formed.
The electron flow was flowing from one source region to the substrate region 51 through different routes, but in the transient state at the time of turn-off, the current routes are concentrated to the portions equidistant from the two gate regions 58. Therefore, the current density at this time is higher than that during steady conduction. In other words, in the conventional device, the density of the electron flow flowing through the drain region 52 to which a high electric field is applied is high, so that a new pair of carriers is easily generated.

Further, the holes generated by the pair generation of carriers are opposite to the path of the electron flow in the channel region 5 on the surface.
7 and is discharged to the gate region 58 through the interface of the fixed potential insulating electrode 56. At this time, in the conventional structure, holes are generated in the part of the drain region 52 that is farthest from the two gate regions 58, and therefore the resistance of the extraction path when extracting holes from this part is large.

From the above, in the conventional element,
Since the current density is increased due to the concentration of the electron flow path immediately before turning off, carriers are likely to be generated, and the resistance of the hole extraction path is large. There was a problem of being delayed.

In view of the above problems, it is an object of the present invention to provide a semiconductor device in which the sustain voltage is improved without changing the cell size of the basic structure.

Another object of the present invention is to provide a semiconductor device which can reduce turn-off time and operate at high speed.

[0021]

The invention according to claim 1 is
In order to achieve the above object, a plurality of first grooves arranged in parallel to each other are provided on one main surface of a semiconductor substrate of a first conductivity type which is a drain region, and the main grooves sandwiched by the first grooves are provided. On the surface
It has a source region of the first conductivity type, and inside the first groove,
Is insulated from the drain region by an insulating film, and
It has a fixed potential insulating electrode kept at the same potential as the source region, and the fixed potential insulating electrode is a conductive material having a work function so as to form a depletion region in the drain region adjacent to the drain region through the insulating film. And a channel region which is a part of the drain region in contact with the source region and is sandwiched by the fixed potential insulating electrodes, and the channel region has the depletion formed around the fixed potential insulating electrode. A region forms a potential barrier that blocks the movement of majority carriers, minority carriers are introduced into the interface of the insulating film surrounding the fixed potential insulating electrode to form an inversion layer, and the drain from the fixed potential insulating electrode is formed. In order to shield the electric field to the region and reduce or eliminate the potential barrier formed in the channel region to open the channel, A plurality of second-conductivity-type gate regions, which are in contact with the main surface, the insulating film, and the drain region and are not in contact with the source region, are arranged at regular intervals, and are opposed to each other on the main surface. The main region surrounded by the two gate regions adjacent to each other and the two first trenches located at unequal distances from the two opposing gate regions 1
A plurality of the source regions, and in the main region between the source region and the gate region remote from the source region, the first trenches adjacent to the source region and adjacent to each other are communicated with each other. In addition, the gist is to have a second groove that is in contact with the main surface.

According to a second aspect of the present invention, in order to achieve the above object, in the semiconductor device according to the first aspect, in each of the two adjacent main regions sandwiched by the two gate regions, the two adjacent main regions are provided. The gist is that the gate region closest to the source region in the main region is the separate gate region.

In order to achieve the above object, the invention according to claim 3 is the semiconductor device according to claim 1 or 2, wherein the fixed potential insulating electrode is provided inside the second groove. And

Next, the operation of the structure according to the first aspect of the invention will be described. For example, when the source region is grounded and an appropriate positive potential is applied to the drain region through an inductive load to use, in order to turn off the conductive state,
When the gate region is grounded or at a negative potential, excess minority carriers in the drain region and the channel region flow into the gate region, and the minority carrier concentration gradually decreases from the vicinity of the gate region. Further, in the drain region, excess minority carriers located relatively far from the gate region also move to the channel region on the main surface having a low potential, and the minority carriers in the drain region are depleted.

At this time, the main region surrounded by the two gate regions and the two fixed potential insulated electrodes is divided by the second groove, and the main region on the side having the source region in the divided main regions is divided. The minority carriers that have moved to the region move to the gate region closer to the source region, and the minority carriers that have moved to the main region on the side where the source region does not exist move to the gate region further away from the source region. That is, the minority carriers that have moved to the main region on the side without the source region do not affect the turn-off operation of the majority carriers flowing from the source region.

From this, the minority carriers that have moved to the main region on the side where the source region is located are extracted from the vicinity of the gate region, and the minority carriers immediately below the source region are finally extracted, so that the source region is drained to the drain region. The path of the majority carriers flowing is maintained just below the source region, as in the conductive state. That is, in this configuration, the majority carrier density in the drain region does not change even in the transient state at the time of turn-off.

Then, as the minority carriers in the drain region are exhausted, the drain potential rises, and when a high electric field is applied to the drain region, the minority carriers generated in the drain region are opposite to the majority carrier path. , Move to the main region, pass through the first fixed potential insulated electrode interface, and are discharged to the gate region. In this configuration, the position where the minority carriers are generated is close to the gate region because it is immediately below the source region, so the generated minority carriers are not accumulated and are quickly discharged in a short time.

From the above, the amount of minority carriers generated in the drain region is reduced, and the amount of minority carriers discharged to the gate region is increased. Therefore, the sustain voltage at which the amounts are equal is increased. To be

Next, the operation of the structure according to the second aspect of the present invention will be described. When the potential of the gate region is increased in the conductive state, the pn junction composed of the gate region, the drain region and the channel region is forward biased, and minority carriers are directly injected into the drain region and the channel region. To be done. Then, the majority carriers flow from the source region to the drain region with low resistance. As the majority carriers flowing from the source region spread radially according to the thickness of the drain region as they move in the drain region, the path of the majority carriers flows from the drain region with the source region as an apex. It has a conical shape with one surface facing the main surface as a bottom surface.

At this time, since the source regions are sparsely arranged in two staggered rows due to the above configuration,
The majority carrier paths in the drain region do not substantially overlap. That is, the density of the majority carriers in the drain region is almost the same as that in the case where they are arranged adjacent to each other, and since the density of the source region can be reduced, the minority carriers injected from the gate region are reduced. Is less likely to jump into the source region.

Further, even in the transient state at the time of turn-off, since the source regions are sparsely arranged, the paths of the majority carriers in the drain region do not substantially overlap with each other, and the current density of the majority carriers does not increase. For,
The minority carrier pair generation associated with the increase of the drain electric field is further reduced.

Next, the operation of the structure according to the third aspect of the invention will be described. With such a configuration, the second groove is simultaneously manufactured in the same step as the first groove, so that the conventional manufacturing apparatus can be used to easily manufacture the second groove in the same manufacturing step. The semiconductor device of the invention can be manufactured.

[0033]

As described above, according to the invention of claim 1, the amount of the minority carriers generated in the drain region is reduced, and the amount of the minority carriers discharged to the gate region is reduced. Therefore, the sustain voltage at turn-off can be easily increased without changing the cell size of the device. Further, there is an effect that the turn-off speed can be improved.

According to the invention described in claim 2, in addition to the effect of the invention described in claim 1, in each of the two main regions adjacent to each other sandwiched between the two gate regions, each of the main regions is adjacent. Since the gate region closest to the source region in the region is the separate gate region, it is possible to improve the current gain and facilitate the driving of the semiconductor device in the steady conduction state. effective. Further, in the transient state at the time of turn-off, the generation of minority carrier pairs can be further suppressed, so that the sustain voltage can be further increased.

Further, according to the invention of claim 3, in addition to the effect of the invention of claim 1 or claim 2, the fixed potential insulated electrode is provided inside the second groove. There is an effect that the semiconductor device of the present invention can be easily realized without changing the conventional manufacturing process.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. 1 to 4 are drawings showing an embodiment of a semiconductor device according to the present invention. 1 is a perspective view for explaining the basic structure of the element, FIG. 2 is a plan view showing the same portion as the surface of FIG. 1, and FIG. 3 is a sectional view of the same side surface of FIG. Further, FIG. 4 is a cross-sectional view taken along a line segment AA in the plan view of FIG. Further, in FIGS. 1 and 2, for the sake of explanation, a state in which the metal film which is an electrode on the surface and the surface protective film are removed is drawn. Although not particularly limited, in the present embodiment, the semiconductor is silicon, the first conductivity type is n-type, and the second conductivity type is p-type.
Described as a type.

First, the device structure will be described. First, in FIGS. 1 to 4, n formed on the n + type substrate region 1 is formed.
A plurality of first trenches 9 arranged in parallel to each other are formed on the surface (one main surface) of the drain region 2 of the mold. A first insulating film 5 is formed inside the first groove 9 and is insulated from the drain region 2. The first trench 9 is filled with the first MOS electrode 4 made of high-concentration p + type polysilicon. P-type gate regions 8 are provided so as to contact the respective ends of the first trenches 9 in the longitudinal direction. Second groove 12 that connects adjacent first grooves 9 to each other
Connect the first grooves 9 to each other at a position displaced from the center of the first grooves 9 in the longitudinal direction toward either end. That is, the area sandwiched between the adjacent first grooves 9 is the second groove 1
It is unevenly divided by two. A source region 3 that is a high-concentration n + type region is provided in a portion of the region sandwiched by the adjacent first trenches 9 that is in contact with the second trench 12 in the shorter region.

The drain electrode 11 is in ohmic contact with the other main surface of the n + type substrate region 1. The source electrode 13 is in ohmic contact with the source region 3 and further with the MOS electrode 4. That is, the first MOS electrode 4 is fixed to the source potential. Therefore, this first
The MOS type electrode 4 and the first insulating film 5 are collectively referred to as a first fixed potential insulating electrode 6.

The sectional structure of the first fixed potential insulated electrode 6 is formed in a first groove 9 whose side wall is substantially vertical like a letter "U" as shown in FIG. Further, in the drawing, the source region 3 is drawn so as to be in contact with the first insulating film 5, but if the source region 3 is arranged so as to be sandwiched by the first fixed potential insulating electrode 6, it does not contact. May be.

Further, in FIG. 2, the drain region 2 sandwiched between the first fixed potential insulating electrodes 6 is called a channel region 7. Further, as shown in FIGS. 1 and 3, a p-type gate region 8 exists in a position in contact with the first insulating film 5 and away from the source region 3. In FIG. 3, reference numeral 18 denotes an electrode which makes ohmic contact with the gate region 8 and is called a gate electrode. Incidentally, 10 is an interlayer insulating film.

A feature of the present invention is that only one source region 3 is formed in a unit cell region surrounded by two gate regions 8 and two first fixed potential insulating electrodes 6, and two source regions 3 are formed. It is arranged at an unequal distance from the gate region 8.
In addition, of the two gate regions 8 that sandwich the source region 3,
A second fixed potential insulating electrode 16 is arranged so as to face the gate region 3 farther from the source region 3 and be adjacent to the source region 3 and in contact with the first fixed potential insulating electrode 6. There is.

The second fixed potential insulating electrode 16 is composed of the second insulating film 15 and the second MOS type electrode 14. In the present embodiment, the second insulating film 15 is the first insulating film 15.
Of the insulating film 5 and the second MOS type electrode 14 of the first MOS
The case of the same material as the mold electrode 4 is shown.

In the present embodiment, a structure in which the manufacturing method can be easily realized is illustrated as an example, but the portion of the second fixed potential insulating electrode 16 is, for example, the second groove 12.
Only the second insulating film 15 or the second MOS type electrode 14 may be partially formed. In the present embodiment, as an example, the width of the second fixed potential insulating electrode 16 is the same as the width of the first fixed potential insulating electrode 6, but the second fixed potential insulating electrode 16 has the same width.
The width of the fixed potential insulating electrode 16 may be larger or smaller than the width of the first fixed potential insulating electrode 6. Although the second insulating film 15 is drawn so as to be in contact with the source region 3, it is arranged so that the source region 3 is sandwiched between the first fixed potential insulating electrode 6 and the second fixed potential insulating electrode 16. You don't have to be in contact with them if they are done.

Further, in the present embodiment, for example,
In the structure in which the source regions 3 in the two adjacent unit cell regions sandwiched between the two gate regions 8 are staggered so that the closest gate regions 8 become different gate regions 8. explain. Regarding the arrangement of the source regions 3 of the adjacent unit cell regions sandwiched between the two gate regions 8, a plurality of source regions 3 may be arranged alternately, and one source region 3 may face the other. It doesn't matter if they are lined up.

Next, the operation of the semiconductor device of this embodiment will be described. In this element, for example, the source electrode 13 is grounded (0
V) and the drain electrode 11 is used by applying an appropriate positive potential through an inductive load such as a motor.

First, when the gate electrode 18 is grounded, the device is in the cutoff state. To explain using FIG. 4,
A depletion layer associated with the built-in potential of the first MOS-type electrode 4 is formed around the first fixed potential insulating electrode 6, but the two first fixed potential insulating electrodes 6 facing each other in the channel region 7 are formed. If the distance between them (hereinafter referred to as the channel thickness H) is sufficiently small, a sufficient potential barrier for conduction electrons is formed in the channel region 7 by this depletion region. For example, if the thickness of the first insulating film 5 is 1
The channel region 7 has an impurity concentration of about 1 × 10
^If the channel thickness H is set to about ¹⁴ cm ⁻³ and the channel thickness H is set to 2 μm or less, a potential barrier sufficient to prevent the conduction electrons of the source region 3 from moving through the channel region 7 to the drain region 2 side can be formed. If the distance is narrower (the channel thickness H is thinner), the barrier performance is improved.

Next, in the conductive state, the potential of the gate electrode 18, that is, the potential of the p-type gate region 8 is set to +0.
When a positive potential of 5 V is applied, holes flow into the interface of the first insulating film 5 from the p-type gate region 8 contrary to the above to form an inversion layer and form a potential barrier. The lines of electric force from the MOS electrode 4 to the channel region 7 are shielded, and the potential barrier for conduction electrons in the channel region 7 is lowered. That is, the drain region 2 and the source region 3 are brought into conduction.

When the potential of the gate electrode 18 is further increased, the pn formed of the p-type gate region 8 and the peripheral n-type region is formed.
The junction is forward biased and holes are directly injected into the drain region 2 as well as the channel region 7. Then, the conductivity is increased in these n-type regions, which have been made to have a low impurity concentration and a high resistance in order to maintain the device breakdown voltage, and the electron current which is a component of the drain current flows from the source region 3 to the substrate region 1. It comes to flow with low resistance. The electron flow flowing from the source region 3 spreads radially according to the thickness of the drain region 2 as it approaches the substrate region 1. Therefore, the electron flow path has the source region 3 as the apex and the substrate region 1 as the bottom surface. It becomes a conical shape.

In this embodiment, only one source region 3 is formed in the unit cell region surrounded by the two gate regions 8 and the two first fixed potential insulating electrodes 6, and they are adjacent to each other. Since the source regions 3 in the unit cell region are alternately arranged so that the gate region 8 closest to the source region 3 is a different gate region 8.
The paths of the electron currents in the drain region 2 in the conductive state are arranged so as not to substantially overlap with each other.

From this fact, the density of the electron flow in the drain region 2 is almost the same as the conventional one, although the density on the main surface of the source region 3 is half that in the prior art. , The on-resistance becomes the same as the conventional one. further,
In the present embodiment, the density of the source region 3 is reduced and the ratio of holes injected from the gate region 8 jumping into the source region 3 is reduced as compared with the prior art, so that a certain drain current value is driven. The gate current value necessary for this is reduced, so-called current gain is improved, and the semiconductor device according to the present invention can be easily driven.

Next, in order to turn off this element, the gate electrode 18 is set to ground (0 V) or a negative potential, and excess holes in the drain region 2 and the channel region 7 flow into the gate region 8. , The hole concentration gradually decreases from the vicinity of the gate region 8. In addition, the excess holes in the part of the drain region 2 which is distant from the gate region 8 also move to the channel region 7 on the surface where the potential is low, and the holes in the drain region 2 are depleted.

At this time, in the present embodiment, the unit cell region surrounded by the two gate regions 8 and the first fixed potential insulating electrode 6 is divided by the second fixed potential insulating electrode 16. Of the divided unit cell regions, the holes that have moved to the surface on the side where the source region 8 is present move from the source region 3 to the closer gate region 8 and the holes that move to the surface on the side where the source region 3 is absent. It moves to the other gate region 8.

That is, the holes that have moved to the surface where the source region 3 is not present do not affect the turn-off operation of the electron flow flowing from the source region 3. From this, the source region 3
Regarding the holes that have moved to the surface on the side where there is, the holes that were directly under the source region 3 are discharged from the vicinity of the gate region 8, and the holes that were immediately below the source region 3 are discharged finally. The path is maintained right below the source region 3 as in the conductive state. That is, as in the steady conduction state, the electron flow paths in the drain region 2 do not substantially overlap with each other, so that the electron flow density in the drain region 2 is not high even in the transient state.

Further, the potential of the drain electrode 11 rises,
When the depletion layer spreads in the drain region 2, carriers travel in a high electric field in the drain region 2, so that a new pair of carriers is generated. Of the carriers generated in the drain region 2, the electrons directly constitute the electron flow. On the other hand, the holes move to the channel region 7 on the surface in the direction opposite to the path of the electron flow, and are discharged to the gate region 8 through the interface of the first fixed potential insulating electrode 6. At this time, in the present embodiment, since the position where holes are pair-generated is the drain region 2 immediately below the source region 3, the position where holes are generated is closer to the gate region 8 and thus the gate region 8 is different from the conventional one.
The resistance of the hole extraction path to the hole is small.

As described above, in the present embodiment, generation of pairs of holes is suppressed in the transient state at turn-off,
Further, since the resistance of the generated hole discharge path is small, the amount of holes generated in the drain region 2 is
The sustain voltage at which the amount of holes extracted to the gate region 8 becomes equal can be improved compared to the conventional case.

In the present embodiment, like the conventional element structure, the breakdown due to the sustain operation which is known in the normal bipolar transistor does not occur. This is because, in the present embodiment, since there is no P-type region between the source region 3 through which the electron flow flows and the substrate region 1, even if the electron flow concentrates on one source region 3, the temperature of that part Becomes higher and the resistance becomes higher, so that the electron flow becomes difficult to flow, the electron flow flows from another source region 3 having a relatively low temperature and low resistance, and eventually the electron flow does not concentrate on any source region 3. That is because the so-called negative feedback is applied.

That is, in a semiconductor chip having a plurality of device structures according to the present embodiment formed, during the sustain operation, the electron flow has the property of flowing in the entire region where the device structure according to the present embodiment is formed. This property is due to the fact that, when this embodiment is used in an inductive load circuit for driving a motor or the like, a guard ring, etc. formed in the same semiconductor chip due to an increase in drain voltage generated by an induced electromotive force at turn-off. This is an advantage that the burden on the pressure resistant structure can be avoided.

Further, in the present embodiment, since the hole extraction path from the channel region 7 is short and the holes are less likely to stay, the blocking speed of the channel region 7, that is, the turn-off speed is also conventionally. Compared with the above, the range of use is expanded to applications requiring higher speed operation than before.

[Brief description of drawings]

FIG. 1 is a perspective view illustrating an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a surface structure in an embodiment of a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view of an embodiment of a semiconductor device according to the present invention seen from another angle.

FIG. 4 is another sectional view of the embodiment of the semiconductor device according to the present invention.

FIG. 5 is a perspective view of a conventional semiconductor device.

FIG. 6 is a sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 ... Substrate area 2 ... Drain region 3 ... Source area 4 ... First MOS type electrode 5 ... First insulating film 6 ... First fixed potential insulated electrode 7 ... Channel area 8 ... Gate area 9 ... First groove 10 ... Interlayer insulating film 11 ... Drain electrode 12 ... second groove 13 ... Source electrode 14 ... Second MOS type electrode 15 ... Second insulating film 16 ... Second fixed potential insulated electrode 18 ... Gate electrode

Claims (3)

[Claims] 1. A plurality of first grooves arranged parallel to each other are formed on one main surface of a semiconductor substrate of the first conductivity type which is a drain region, and the main surface sandwiched by the first grooves is provided. A source region of the first conductivity type is provided, and a fixed potential insulating electrode insulated from the drain region by an insulating film and kept at the same potential as the source region is provided inside the first groove. The fixed potential insulating electrode is made of a conductive material having a work function that forms a depletion region in the drain region that is adjacent to the drain region through the insulating film, and is a part of the drain region in contact with the source region. A fixed potential insulated electrode sandwiched between the fixed potential insulated electrodes, and a depletion region formed around the fixed potential insulated electrode to form a potential barrier for blocking movement of majority carriers. , A minority carrier is introduced into an interface of the insulating film surrounding the fixed potential insulating electrode to form an inversion layer, and an electric field from the fixed potential insulating electrode to the drain region is shielded to form a potential formed in the channel region. A plurality of second-conductivity-type gate regions, which are in contact with the main surface, the insulating film, and the drain region and are not in contact with the source region, are formed at regular intervals in order to reduce or eliminate the barrier and open the channel. 1 of the main surface, which is located at an unequal distance from the two facing gate regions in a main region surrounded by the two facing gate regions and two adjacent first trenches. A plurality of the source regions, the main region between the source region and the gate region remote from the source region is adjacent to and adjacent to the source region. Wherein a has a second groove in contact with the main surface communicated with the grooves with each other. 2. In two adjacent main regions sandwiched between the two gate regions, the gate region closest to the source region in each of the main regions is a separate gate region. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein the fixed potential insulating electrode is provided inside the second groove.