JP2003068890A - Nonvolatile semiconductor storage device and nonvolatile memory cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that since a residual polarization retains in a ferroelectric film in a 1-transistor ferroelectric memory cell, even when a reading voltage is applied to a gate, a current value cannot be considerably raised and data-holding characteristics are short. SOLUTION: A nonvolatile semiconductor storage device comprises a ferroelectric gate transistor MC having a first electrode DS, a second electrode S and a control electrode G, and a breaking transistor MS having a first electrode D, a second electrode S and a control electrode G in such a manner that the first electrode D of the gate transistor MC is connected to the second electrode S of the breaking transistor MS and the control terminal G of the transistor MC and the control terminal G of the transistor MS are commonly coupled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a nonvolatile memory element, and more particularly to a nonvolatile semiconductor memory device and a nonvolatile memory element using a ferroelectric gate transistor.

In recent years, a ferroelectric memory (FeRAM) has attracted attention as a nonvolatile semiconductor memory device capable of high integration, low power consumption and high speed operation. In particular, a semiconductor memory device using a one-transistor type ferroelectric memory element composed of one ferroelectric gate transistor using a ferroelectric film as a gate insulating film has a gate ferroelectric property for reading stored information. Since non-destructive read is possible without body polarization reversal, it is expected as a future nonvolatile semiconductor memory device. Further, there is a strong demand to provide a ferroelectric memory device having a large read current and capable of holding data for a long time.

[0003]

2. Description of the Related Art Conventionally, an EEPROM, a flash memory or the like has been mainly used as a non-volatile semiconductor memory device, but as a memory which realizes high integration, low power consumption, high speed operation and high durability. Ferroelectric memories using ferroelectric gate transistors have been attracting attention,
Has been actively researched and developed.

A ferroelectric gate transistor is a field effect transistor (FE) using a ferroelectric material for a gate insulating film.
T: Field Effect Transistor, which is a device that controls the current flowing between the source and drain depending on the polarization direction of the ferroelectric substance.

FIG. 1 is a diagram for explaining an example of a ferroelectric memory (nonvolatile semiconductor memory device) using a one-transistor (1T) type ferroelectric memory element, and FIG. 2 is shown in FIG. FIG. 3 is a diagram showing one ferroelectric memory element (nonvolatile memory element) in the ferroelectric memory of FIG.

In FIG. 1, reference numeral SA is a sense circuit, DEC is a decoder, and PS is a power supply circuit. 1 and 2, reference numeral MC
(MC1 to MCm) are dielectric memory elements (memory cell transistors), W (W1 to Wm) are word lines, G is a gate (control electrode), S is a source (second electrode), and SL is a source line (first). Bit line), D is the drain (first electrode),
DL indicates a drain line (second bit line). Here, the sense circuit SA and the plurality of memory elements (MC1 to MCm) connected thereto are provided in a plurality of columns.

As shown in FIG. 1, the ferroelectric memory (nonvolatile semiconductor memory device) has word lines W1 to Wm.
And a plurality of memory cells (memory element M provided in a matrix at intersections of the bit line pairs SL and DL of each column.
C: MC1 to MCm) and an external address signal A1
~ Aj is decoded and the corresponding memory cell is set to the word line W.
1 to Wm and a decoder DEC for accessing through the sense circuit SA, and a power supply circuit that generates power required for writing, reading and holding data to and from the memory cell and supplies the power to the decoder DEC and the sense circuit SA. And PS. The sense circuit SA connected to each bit line pair may be used, for example, by selectively connecting one sense circuit to a plurality of bit line pairs and further using the decoder DEC and the power supply circuit PS. It goes without saying that the configurations such as the above can be variously modified.

As shown in FIGS. 1 and 2, the nonvolatile semiconductor memory device (1-transistor type ferroelectric memory) targeted by the present invention is an FET using a ferroelectric material as a gate insulating film, and is 1 bit. Memorize The data stored in the memory element (memory cell) MC is a current flowing between the source S (source line SL) and the drain D (drain line DL) when the read voltage V _READ is applied to the word line W. Is detected by the sense circuit SA, data “0”
Is stored, or whether data “1” is stored is determined.

Specifically, in FIG. 1, for example, when the memory cell MC2 is used as a selected cell, a read voltage V _READ (for example, a read voltage V _READ ) is applied to a word line W2 connected to the selected cell MC2.
(Approx. 2.8V) and other non-selected cells MC
1 and the word lines W1 and W3 to Wm connected to MC3 to MCm are held at 0V, and the current flowing through the selected cell MC2 is supplied to the sense circuit S via the pair of bit lines SL and DL.
Detect by A. That is, for example, the selected cell MC2
Is turned on and a predetermined current flows between the bit line pair SL and DL as data "1", and data when the selected cell MC2 is off and no current flows between the bit line pair SL and DL is data "0". ]. Therefore, in order to read the state (data) of the selected cell MC2, the cell M in the holding (standby) state is read.
Source (S) and drain (D) of C1 and MC3 to MCm
There should be no current between and.

FIG. 3 is a diagram showing a conventional example of the ferroelectric memory device shown in FIG. 2, and FIG. 3 (a) shows an MFS-FET (metal / metal
Ferroelectric / Semiconductor FET: Metal-Ferroelectric-Semico
nductor FET), and FIG. 3 (b) is a MFIS-FET
(Metal / Ferroelectric / Insulator / Semiconductor FET: Metal-Ferr
3C shows an MFMIS-FET (metal / ferroelectric / metal / insulator / semiconductor FET: Metal-Ferroelectri).
c-Metal-Insulator-Semiconductor FET). 3A to 3C, reference numeral 11 is a semiconductor substrate (p-type silicon substrate: p-Si), 12 is a metal gate, 13 is a ferroelectric (ferroelectric film), and 14 is a buffer. Layers (insulators) and 15 are floating gates (metal layers).

The MFS-FET shown in FIG. 3A is a basic type of a ferroelectric memory device, and is formed by forming a ferroelectric (thin film) 13 directly on a semiconductor substrate 11.

In the MFIS-FET shown in FIG. 3B, it is difficult to form a ferroelectric / semiconductor interface having good characteristics in the MFS-FET of FIG.
A paraelectric (insulator) buffer layer 14 is inserted between the semiconductor substrate 11 and the semiconductor substrate 11. When the ferroelectric film 13 is formed directly on the semiconductor substrate 11 (silicon substrate) by using the current film forming technique (in the case of FIG. 3A), the ferroelectric substance is an oxide film, so that the high temperature During the crystallization process, a transition layer of paraelectric material such as SiO ₂ is formed at the interface between silicon (Si) and the ferroelectric material, and in fact, it often has an MFIS structure.

The MFMIS-FET shown in FIG. 3C is
In the MFIS-FET of FIG. 3B, a floating gate 15 of metal (or conductive oxide) is further inserted between the ferroelectric film 13 and the buffer layer 14, and the upper ferroelectric Body capacitor (MFM part: 1
2, 13, 15) and the lower MIS part (15, 14, 1)
There is a merit that the area of 1) can be designed independently.

Next, the operating principle of the ferroelectric gate transistor will be described.

FIG. 4 is a diagram for explaining the operation principle of the ferroelectric gate transistor (ferroelectric memory element) MC. FIG. 4 (a) shows an off state and FIG. 4 (b) shows an on state. Is shown. The memory element (transistor) shown in FIG. 4 is the MFS-FET shown in FIG.

First, the ferroelectric gate transistor MC
Is a device for controlling the conductance of the channel by polarization of the ferroelectric film (13) used as the gate insulating film.

As shown in FIGS. 4 (a) and 4 (b), when positive and negative voltages are applied to the gate 12 (G) and then returned to 0 V, the gate insulating film 13 is formed. The direction of polarization of the ferroelectric substance is different, and depending on the direction of polarization of the ferroelectric gate insulating film 13, the ON state (see FIG.
(B)) and the off state (FIG. 4 (a)) can be realized with the same gate voltage. That is, the polarization state of the ferroelectric substance 13 is changed by the write voltage applied in the past, and the value of the drain current (current flowing between the source S and the drain D) flowing when the read voltage is applied is controlled. You can

FIG. 5 is a diagram (part 1) for explaining the characteristics of the ferroelectric memory element (ferroelectric gate transistor).
And is a diagram showing the relationship of FIG. 5 and (a) and 5 (b) is the drain current of each ferroelectric gate transistor (I _D) and the gate voltage (V _G).

[0019] As shown in FIG. 5 (a), the drain current of the ferroelectric gate transistor (MC) - gate voltage characteristic (I _D -V _G characteristics) becomes hysteresis curve, the polarization of the ferroelectric (13) Therefore, it can be considered that the threshold voltage of the transistor is changed. In order to use this ferroelectric gate transistor as a memory device, the hysteresis of the I _D -V _G characteristic of the transistor is shown in FIG.
As in (a), it is necessary to adjust the threshold value of the transistor so that it does not cross V _G = 0V.

That is, as shown in FIG. 5B, the hysteresis of the I _D -V _G characteristic of the ferroelectric gate transistor is V
_{If G} = 0V is crossed, current cannot flow even during standby when V _G = 0V, so that it cannot be used as a memory element.

FIG. 6 is a diagram (part 2) for explaining the characteristics of the ferroelectric memory element.

As shown in FIG. 6, during standby, V _G
It is held at = 0 V (point B), but if the read voltage V _READ is applied in this state, it moves from point B to point C without returning to point A. As a result, the read current (drain current I _DR0 ) becomes small (the current at the time of reading cannot be made large), and the data retention characteristic of the memory becomes poor.

In order to adjust the threshold value of the ferroelectric gate transistor (MC) to improve the data retention characteristics as a memory, the metal of the gate (12) is changed (that is, a metal having a different work function is used as the gate. Do)
Alternatively, it is possible to implant ions in the channel portion.

FIG. 7 is a diagram for explaining threshold adjustment by changing the metal of the gate, FIG. 8 is a diagram for explaining the load line in FIG. 7, and FIG. 9 is a threshold for changing the metal of the gate. FIG. 6 is a diagram for explaining a problem in the case of performing the adjustment of FIG.

In FIG. 7, reference numeral RL1 indicates a load line before shift (before threshold adjustment), RL2 indicates a load line after shift (after threshold adjustment), and RL3 indicates a gate voltage V _G. When the read voltage is V _READ (V _G =
V _READ ) load line is shown. Here, FIG. 7 shows a ferroelectric (1) in an n-channel MFMIS-FET.
3) is SrBi ₂ Ta ₂ O ₉ (SBT), the insulator (buffer layer 14) is 5 nm in terms of SiO ₂ equivalent, MIS part and MFM
Area ratio (S _MIS / S _MFM ) to the part is S _MIS / S _MFM = 1
0, and the substrate concentration (N _A ) is N _A = 10 ¹⁵ cm ⁻³ . In FIG. 7, the vertical axis represents polarization (μC / cm ² ) and the horizontal axis represents applied voltage (gate voltage V _G ).

First, as shown in FIG. 8, the load line RL
The ferroelectric gate transistor is turned on in the inversion region of (RL1 to RL3), while the ferroelectric gate transistor is turned off in the depletion region and the storage region of the load line RL.

In FIG. 7, the ferroelectric gate transistor is shown.
Load line before adjusting the threshold of the ferroelectric memory device MC
For RL1, apply a positive voltage to the gate (G) to induce
Write to the electric body, then return the gate voltage to 0V
In the standby state, the operating point becomes the E point. At this time,
The point is on the inversion state of the load line and the transistor is on.
It remains. Therefore, the transistor I_D-V_GThe characteristics are
V as shown in FIG. _GHysteresis crosses = 0V
Becomes Thus, the transistor I_D-V_GCharacteristic is V
_G= 0V, V_GThe current is still on standby at = 0V
Since it flows, it can be used as a memory element.
Absent.

Therefore, like the load line RL2 in FIG.
The load line is shifted by the work function difference of the metal, and the operating point is set to point F. Here, since the point F is the depletion region of the load line RL2, the transistor is turned off and no current flows. Therefore, I _D -V _G characteristics of the transistor is shown in FIG 9 (b).

However, in the case of FIG. 9B, a large reverse voltage is applied to the ferroelectric substance, so that the polarization is inverted and the data retention characteristic is significantly deteriorated. Furthermore, when the read voltage V _READ is applied from the holding state, the load line moves like the load line (dotted line) RL3 in FIG.
The operating point F does not return on the saturation hysteresis of the ferroelectric substance, but moves as shown by the dotted arrow to reach the H point. as a result,
The read current is significantly smaller than that at point E.

FIG. 10 is a diagram for explaining the adjustment of the threshold value by ion implantation into the channel portion, FIG. 11 is a diagram for explaining the load line in FIG. 10, and FIG. It is a figure for demonstrating the subject at the time of inject | pouring and adjusting a threshold value.

In FIG. 10, reference numeral RL4 shows a load line when the substrate concentration of the p-type silicon substrate (p-Si) is low, and RL5 when the substrate concentration is high (ion implantation was performed to increase the substrate concentration. Case) load line, and
RL6 indicates a load line when the gate voltage V _G is the read voltage V _READ (V _G = V _READ ). Here, FIG.
0 is basically the same as that of FIG. 7, in FIG. 10, the substrate concentration (N _A), when N _A = 10 ¹⁵ cm ^-3 (when the substrate concentration is low: load line RL4), And N _A = 1
0 ¹⁸ cm ^-3 (when substrate concentration is high: load line RL
5) is shown. In FIG. 10, the vertical axis represents polarization (μC / cm ² ) and the horizontal axis represents applied voltage (gate voltage V _G ).

As shown in FIG. 11, the load line RL (R
A larger current flows as the difference ΔQ between the operating point (reversal region) on L4 to RL6 and the threshold charge increases. Therefore, even if the charges of the ferroelectrics are about the same, the I _D
Is very different.

In FIG. 10, regarding the load line RL4 when the substrate concentration of the ferroelectric gate transistor (ferroelectric memory element MC) is low, the operating point is held at point J, and the transistor remains on. . I _{D at} this time
The −V _G characteristic is as shown in FIG.

On the other hand, regarding the load line RL5 when the ion implantation is performed to increase the substrate concentration, the operating point (K
The point) is in the depletion region on the load line, and the transistor is not on. Therefore, I _D -V _G characteristics, FIG. 12
It looks like (b).

When the read voltage V _READ is applied to the gate (G), the load line moves like the load line RL6 shown by the dotted line in FIG. At this time, operating point K
Moves to point L as indicated by the dotted arrow. However, the read current cannot be increased because the amount of electric charge for inverting the transistor is increased by the ion implantation. In FIG. 10, point L is still in the depletion region and is not turned on.

As described above, in order to adjust the threshold value of the ferroelectric gate transistor and improve the data retention characteristics as a memory, it is conceivable to change the metal of the gate or ion-implant the channel portion. It was not a valid solution.

[0037]

FIGS. 13 and 14 are views for explaining the problems of the conventional ferroelectric memory device. Here, FIG. 13A shows a state of voltage application during data writing, and FIG. 13B shows a state of voltage application during data retention. In addition, MFIS-FE
T (see FIG. 3 (b)) and MFMIS (see FIG. 3 (c))
It can be considered that the MFM ferroelectric capacitor is equivalently connected in series to the gate of the MISFET. Further, FIG. 14A shows the relationship between the charge (Q) of the ferroelectric film (MFM ferroelectric capacitor) and the voltage (V), and FIG. 14B shows the charge (Q) of the MIS portion and the voltage. FIG. 14 shows the relationship with (V), and FIG.
(C) shows how to obtain the operating point in the ferroelectric memory device.

In FIG. 13A, reference numeral V _T indicates the voltage applied to the gate G during writing (the entire applied voltage). The voltage of the source S and the drain D is 0V. At this time, the voltage (total voltage) V _T applied to the gate is divided, the voltage V _{F is} applied to the ferroelectric film, and the voltage V _M is applied to the MIS portion. The Q-V characteristic of the ferroelectric film is as shown in FIG. 14A, and the Q-V characteristic of the MIS portion is
The V characteristic is as shown in FIG. Then, at the time of writing data, as shown in FIG.
V _T = V _F + V _M.

As shown in FIG. 13B, the data storage
Keep the terminals (gate G, source S and drain
IN D) is grounded (0V), and voltage V_TIs also 0V
To be done. At this time, the remanent polarization (Q_M)But
Since it remains, the MIS part (buffer
V in the layer 14)_M'(Q_M= C_MV_M': C_MIs the paraelectric material
Voltage remains) and the ferroelectric film has V
_M'Voltage opposite to V _F'Is applied. Obey
When the data is retained, the voltage V_F'
(= -V_M': Depolarized electric field) remains applied
Therefore, the polarization of the ferroelectric film is gradually destroyed and the
Even if a read voltage is applied to the gate G, the current value is too large.
Should be solved and the data retention characteristics should be short.
There are challenges.

In view of the above-mentioned problems in the conventional nonvolatile semiconductor memory device, the present invention provides a large read current,
Another object of the present invention is to provide a ferroelectric memory element (nonvolatile memory element) capable of holding data for a long time and a nonvolatile semiconductor memory device using the same.

[0041]

According to the first aspect of the present invention, a plurality of word lines, a plurality of bit line pairs, and a matrix shape at intersections of the word lines and the bit line pairs are formed. A plurality of memory cells provided in each, a sense circuit connected to each bit line pair, and a decoder for decoding an address signal to access the corresponding memory cell via the word line and the sense circuit. A power supply circuit that generates a voltage required to write, read, and hold data in the memory cell, wherein each memory cell has a first
A ferroelectric gate transistor having an electrode, a second electrode, and a control electrode; and a cutoff transistor having a first electrode, a second electrode, and a control electrode, and a first electrode of the ferroelectric gate transistor is connected to the cutoff transistor. Second
There is provided a nonvolatile semiconductor memory device characterized in that the control terminal of the ferroelectric gate transistor and the control terminal of the cutoff transistor are commonly connected to the electrodes.

According to the second aspect of the present invention, the first electrode,
A ferroelectric gate transistor having a second electrode and a control electrode; and a cutoff transistor having a first electrode, a second electrode and a control electrode, wherein the first electrode of the ferroelectric gate transistor is the second of the cutoff transistor. Provided is a non-volatile memory device, characterized in that the control terminal of the ferroelectric gate transistor and the control terminal of the cutoff transistor are commonly connected to the electrodes.

FIG. 15 is a diagram for explaining the principle of the ferroelectric memory device according to the present invention.

As is apparent from the comparison between FIG. 15 and FIG. 2, the ferroelectric memory element (memory cell) M according to the present invention.
CS is an N-channel MIS transistor (M
OS transistor) MS as source line (first bit line)
It is arranged in series between SL and the drain line (second bit line) DL.

That is, as shown in FIG. 15, the ferroelectric memory element MCS of the present invention includes a ferroelectric gate transistor (ferroelectric gate transistor portion) MC and a MIS transistor (MIS transistor portion: cutoff transistor) MS. The respective gates of the ferroelectric gate transistor MC and the MIS transistor MS are commonly connected to the word line W.

MIS transistor (cutoff transistor)
The MS cuts off the electric current of the ferroelectric gate transistor MC while keeping it in the ON state, and as a result, the polarization in the ferroelectric film of the ferroelectric gate transistor MC that holds the data due to the depolarization electric field described above. It is designed to suppress the destruction of. That is, even if the ferroelectric gate transistor MC is in the ON state, the MIS transistor MS is turned off in the standby state when the gate voltage is 0 V, so that it is between the source line SL and the drain line DL (pair of bit lines). No current flows.

Therefore, the gate voltage during standby can be set higher than the threshold voltage of the ferroelectric gate transistor MC in which the polarization is in the ON state, whereby the reverse voltage applied to the ferroelectric film during standby can be set. It is possible to reduce the directional electric field and minimize the destruction of polarization. As a result, it is possible to provide a ferroelectric memory (nonvolatile semiconductor memory device) with a large read current and good retention characteristics.

The principle of the ferroelectric memory device according to the present invention has been described above. However, if a MIS transistor is simply added to the ferroelectric gate transistor MC, it is disadvantageous for high integration. In each of the embodiments described below, a split gate structure in which a floating gate is formed halfway in the channel region is mainly used to realize this function by one element.

[0049]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a nonvolatile semiconductor memory device and a nonvolatile memory element according to the present invention will be described below in detail with reference to the drawings.

FIG. 16 is a diagram showing a first embodiment of the ferroelectric memory element according to the present invention, and corresponds to the above-described FIG. 15 directly configured as a memory element. In FIG. 16, reference numeral 11 is a semiconductor substrate (p-type silicon substrate: p-Si), 12 is a metal gate, 13 is a ferroelectric (ferroelectric film), and 14 is a buffer layer (insulator).
Reference numeral 21 indicates a gate, and 22 indicates a silicon oxide film (insulator). Here, the gate (control electrode) 21 and the insulator 22 of the MIS transistor (blocking transistor) MS may be made of the same material as the metal gate 12 and the buffer layer 14 of the ferroelectric gate transistor MC in the same process. For example, it may be manufactured in another process using another substance in consideration of characteristics and the like.

Ferroelectric memory device MCS of the first embodiment
Is a pair of bit lines (source line SL and drain line D
L), a ferroelectric gate transistor (ferroelectric gate transistor portion) MC and a MIS transistor (MIS transistor portion) MS connected in series, and these ferroelectric gate transistors MC and M are provided.
Each gate G of the IS transistor MS is commonly connected to the word line W. It should be noted that the ferroelectric memory element MCS of this embodiment and each of the embodiments described below has the same structure as that shown in FIG.
It is used as a memory cell of a ferroelectric memory (nonvolatile semiconductor device) as shown in FIG.

The ferroelectric gate transistor MC has the same structure as that shown in FIG. 3B, but this is merely an example, and the structure shown in FIG. 3A or FIG. Good. The MIS transistor MS is configured as an N-channel type MIS transistor, is turned on when the read voltage V _READ is applied to the word line W, and is turned off when the holding voltage (for example, 0 V) is applied to the word line W. Is configured to be. Although the ferroelectric gate transistor MC and the MIS transistor MS are both N-channel type, they may be P-channel type by changing the driving voltage for reading, writing and holding. It goes without saying that you can do it.

As described above, in the ferroelectric memory element MCS of the first embodiment, the source (second electrode) S of the ferroelectric gate transistor MC is connected to the source line (first bit line) SL.
, The drain (first electrode) D of the ferroelectric gate transistor MC is connected to the source S of the MIS transistor MS, the drain D of the MIS transistor MS is connected to the drain line (second bit line) DL, Furthermore, the ferroelectric gate transistor MC and the MIS transistor M
Each gate G of S is commonly connected to the word line W. As a result, the read voltage V _{READ is} applied to the word line W.
Is applied, the MIS transistor MS is turned on, and the data held in the ferroelectric gate transistor MC is read out as in the conventional ferroelectric memory element. Then, at the time of holding data, the voltage of the word line W becomes 0 V, the MIS transistor MS is turned off, the drain of the ferroelectric gate transistor MC becomes a floating state (high impedance state), and the influence of the depolarizing electric field described above is removed. The breakdown of polarization in the ferroelectric film is suppressed. This makes it possible to increase the read current of the ferroelectric memory element and improve the holding characteristics.

FIG. 17 is a diagram showing a second embodiment of the ferroelectric memory device according to the present invention.

As is clear from the comparison between FIG. 17 and FIG. 16, the ferroelectric memory element MCS of the second embodiment is similar to the first embodiment described above in that the drain (drain region) of the ferroelectric gate transistor MC. ) D and the source (source region) S of the MIS transistor MS are configured as one region, and the area occupied by the ferroelectric memory element MCS can be reduced as compared with the first embodiment. .

18 to 25 are views showing the third to tenth embodiments of the ferroelectric memory device according to the present invention.
Each of these shows an example of a split gate type ferroelectric memory device. Here, reference numeral 15 indicates a floating gate (metal layer).

As shown in FIG. 18, the ferroelectric memory element MCS of the third embodiment can be roughly divided into four regions R11 to R14 due to the vertical laminated structure, and the region R11 is The region R12 corresponds to the MIS (MOS) transistor MS including the metal gate 12 (21), the insulator (buffer layer: gate insulating film) 14 (22) and the semiconductor substrate (p-Si) 11, and the region R12 is the metal gate 1.
2, a ferroelectric (ferroelectric film) 13, an insulator 14, and a semiconductor substrate 11 corresponding to a MFIS-structured ferroelectric gate transistor MC, and a region R13 includes a metal gate 12, a ferroelectric 13, This corresponds to the ferroelectric gate transistor MC having the MFMIS structure including the metal layer 15, the insulator 14 and the semiconductor substrate 11. The region R14
Is composed of a ferroelectric substance 13, a metal layer 15, an insulator 14 and a semiconductor substrate 11. Considering the region R14 including the metal gate 12 in the adjacent region R13, MF is also considered.
It corresponds to the ferroelectric gate transistor MC having the MIS structure. Further, for example, in the N-channel type memory element MCS as in the present embodiment, when considering the electric field of the memory element MCS, a low potential voltage is applied to the region R14 when reading the data of the memory element MCS. It is preferable to dispose on the source line SL side.

FIG. 19 is a diagram showing a fourth embodiment of the ferroelectric memory device according to the present invention. 19 to 25, the source line SL, the drain line DL, the word line W and the like are omitted.

As is clear from the comparison between FIG. 19 and FIG. 18, the ferroelectric memory element MCS of the fourth embodiment is similar to that of FIG.
In the ferroelectric memory device of the fourth embodiment shown in FIG. 8, an n ⁺ -type impurity region is provided in the semiconductor substrate 11 in the region R12, and the MFIS component of the region R12 is formed into a transistor (M
It does not operate as C). That is, using the MFMIS constituent part of the region R13 (region 14) as the ferroelectric gate transistor MC and the MIS (MOS) constituent part of the region R11 as the MIS transistor MS, these ferroelectric gate transistors MC and MIS are used. The transistor MS is divided and used.

FIG. 20 is a diagram showing a fifth embodiment of the ferroelectric memory device according to the present invention. The ferroelectric memory element MCS of the fifth embodiment is similar to the memory element of the fourth embodiment described above in that the n ⁺ -type impurity region is provided in the semiconductor substrate 11 of the region R22, and the ferroelectric gate transistor MCS is formed. As the MC, the MFMIS constituent part of the region R24 (region 23) is
Further, the MI of the region R21 is used as the MIS transistor MS.
The S component is divided and used.

FIG. 21 is a diagram showing a sixth embodiment of the ferroelectric memory element according to the present invention.

Ferroelectric memory device MCS of the sixth embodiment
In, the regions R31 and R33 correspond to the MIS transistor MS including the metal gate 12 (21), the insulator 14 (22) and the semiconductor substrate 11, respectively, and the region R32 corresponds to the metal gate 12, the ferroelectric 13 and the metal layer. 1
5, MFMI including insulator 14 and semiconductor substrate 11
This corresponds to the ferroelectric gate transistor MC having the S configuration.

FIG. 22 is a diagram showing a seventh embodiment of the ferroelectric memory element according to the present invention, which is a simplified version of the sixth embodiment described above.

That is, in the ferroelectric memory element MCS of the seventh embodiment, the MIS transistor MS is the sixth
Similar to the embodiment, the metal gate 12 (21), the insulator 14
(22) and the regions R31 and R33 formed of the semiconductor substrate 11, and the ferroelectric gate transistor MC
Is composed of a region R32 of the MFIS structure including the metal gate 12, the ferroelectric 13, the insulator 14, and the semiconductor substrate 11.

That is, in the ferroelectric memory element MCS of the sixth and seventh embodiments, the MIS transistor MS is provided on each side (source side and drain side) of the ferroelectric gate transistor MC. ing. Therefore, the ferroelectric gate transistor (R32)
Is coupled to the source of the first MIS transistor (R31), and the source of the ferroelectric gate transistor (R32) is coupled to the source of the second MIS transistor (R3).
3) is coupled to the drain, and the gate G of the ferroelectric gate transistor (R32) and the control terminals G, G of the first and second MIS transistors (R31, R33) are commonly coupled.

FIG. 23 is a diagram showing an eighth embodiment of the ferroelectric memory device according to the present invention. The N-channel type ferroelectric memory device of the third embodiment shown in FIG. 18 is a P-channel type. It shows the one configured with. In FIG. 23,
Reference numeral 10 indicates a well (n-Si).

As is apparent from FIGS. 23 and 18,
The ferroelectric memory device according to the present invention is not limited to the N-channel type, and a P-channel type structure corresponding to each embodiment is also possible.

FIG. 24 is a diagram showing a ninth embodiment of the ferroelectric memory element according to the present invention.

As shown in FIG. 24, in the ferroelectric memory element MCS of the ninth embodiment, the region R41 is a MIS transistor including the metal gate 12 (21), the insulator 14 (22) and the semiconductor substrate 11. Corresponding to MS,
The region R43 (R44) includes the metal gate 12 and the ferroelectric 1.
3. Ferroelectric gate transistor MC of MFMIS structure composed of 3, metal layer 15, insulator 14 and semiconductor substrate 11.
Corresponding to. The region R42 includes the metal gate 12, the insulator 14, the metal layer 15, the insulator 14, and the semiconductor substrate 1.
Although it is composed of 1, the region R42 is formed by this region R42.
1 and the region R43 (R44) are divided.

In each of the above embodiments, the insulator (buffer layer) 14 and M of the ferroelectric gate transistor MC.
The insulator (gate insulating film) 22 of the IS transistor MS includes SiO ₂ , SiON, Si ₃ N ₄ and Zr.
_{O 2, HfO 2, La 2} O 3, SrTiO 3, SrTa 2 O 6
A high dielectric constant material such as Further, as the metal layer (floating gate) 15, Pt, Ti,
In addition to metals such as Ir, conductive oxides such as IrO ₂ and RuO ₂ , conductive nitrides such as TiN, TaN, and ZrN, and polysilicon and a laminated structure thereof can be used. Further, as the ferroelectric substance (ferroelectric film) 13, Pb (Zr, Ti) O ₃ (PZT) system, SrBi ₂ T
a ₂ O ₉ (SBT) system, (Bi, La) ₄ Ti ₃ O ₁₂ (BL
It is possible to use a T) -based material or a material such as Sr ₂ (Ta, Nb) ₂ O ₇ .

As described above, in the ferroelectric memory device according to each of the embodiments of the present invention, the drain current is turned off in the MIS transistor portion during data retention, so that the polarization of the ferroelectric substance, which is a problem during standby, is reduced. Therefore, the read current can be increased, and the data retention characteristic can be improved.

[0072]

As described above in detail, according to the present invention, the read current of the nonvolatile memory element (nonvolatile semiconductor memory device) can be increased and the data retention characteristic can be improved. it can.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an example of a ferroelectric memory using a 1-transistor (1T) type ferroelectric memory element.

2 is a diagram showing one ferroelectric memory element in the ferroelectric memory of FIG. 1. FIG.

FIG. 3 is a diagram showing a conventional example of the ferroelectric memory device of FIG.

FIG. 4 is a diagram for explaining the operation principle of a ferroelectric gate transistor.

FIG. 5 is a diagram (No. 1) for explaining the characteristics of the ferroelectric memory element.

FIG. 6 is a diagram (No. 2) for explaining the characteristics of the ferroelectric memory element.

FIG. 7 is a diagram for explaining the adjustment of the threshold value by changing the metal of the gate.

FIG. 8 is a diagram for explaining load lines in FIG. 7.

FIG. 9 is a diagram for explaining a problem when the threshold metal is adjusted by changing the metal of the gate.

FIG. 10 is a diagram for explaining adjustment of a threshold value by ion implantation into a channel portion.

FIG. 11 is a diagram for explaining load lines in FIG.

FIG. 12 is a diagram for explaining a problem in the case of adjusting the threshold value by implanting ions into the channel portion.

FIG. 13 is a diagram (No. 1) for explaining the problem of the conventional ferroelectric memory device.

FIG. 14 is a diagram (No. 2) for explaining the problem of the conventional ferroelectric memory element.

FIG. 15 is a diagram for explaining the principle of the ferroelectric memory device according to the present invention.

FIG. 16 is a diagram showing a first embodiment of a ferroelectric memory element according to the present invention.

FIG. 17 is a diagram showing a second embodiment of the ferroelectric memory element according to the present invention.

FIG. 18 is a diagram showing a third embodiment of the ferroelectric memory element according to the present invention.

FIG. 19 is a diagram showing a fourth embodiment of the ferroelectric memory element according to the present invention.

FIG. 20 is a diagram showing a fifth embodiment of the ferroelectric memory element according to the present invention.

FIG. 21 is a diagram showing a sixth embodiment of the ferroelectric memory element according to the present invention.

FIG. 22 is a diagram showing a seventh embodiment of the ferroelectric memory element according to the present invention.

FIG. 23 is a diagram showing an eighth embodiment of the ferroelectric memory element according to the present invention.

FIG. 24 is a diagram showing a ninth embodiment of the ferroelectric memory element according to the present invention.

[Explanation of symbols]

11 ... Semiconductor substrate (p-type silicon substrate: p-Si) 12 ... Metal gate 13 ... Ferroelectric material (ferroelectric film) 14 ... Buffer layer (insulator) 15 ... Floating gate (metal layer) 21 ... Gate 22 ... Silicon oxide films A1 to Aj ... Address signal D ... First electrode (drain) DEC ... Decoder DL ... Drain line (second bit line) G ... Control electrode (gate) MCS, MC1 to MCm ... Dielectric memory element (memory Cell transistor) MC ... Dielectric gate transistor MS ... Cutoff transistor (MIS transistor) PS ... Power supply circuit S ... Second electrode (source) SA ... Sense circuit SL ... Source line (first bit line) W, W1 to Wm ... Word line

Claims (18)

[Claims] 1. A plurality of word lines, a plurality of bit line pairs, a plurality of memory cells arranged in a matrix at intersections of the word lines and the bit line pairs, and the bit line pairs. A sense circuit connected to the memory cell, a decoder for decoding an address signal to access a corresponding memory cell through the word line and the sense circuit, and a decoder necessary for writing, reading, and holding data in the memory cell. A non-volatile semiconductor memory device including a power supply circuit for generating a voltage, wherein each memory cell includes a ferroelectric gate transistor having a first electrode, a second electrode and a control electrode; A cutoff transistor having two electrodes and a control electrode, wherein the first electrode of the ferroelectric gate transistor is a second electrode of the cutoff transistor With binding to, non-volatile semiconductor memory device, characterized in that the coupling the control terminal of the control terminal and the blocking transistor of the ferroelectric gate transistor in common. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the ferroelectric gate transistor has an MFS structure including a metal gate, a ferroelectric substance and a semiconductor substrate. apparatus. 3. The non-volatile semiconductor memory device according to claim 1, wherein the ferroelectric gate transistor is a metal gate, a ferroelectric substance, an insulator, and a semiconductor substrate.
A non-volatile semiconductor memory device having an IS structure. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the ferroelectric gate transistor has an MFMIS structure including a metal gate, a ferroelectric, a metal layer, an insulator, and a semiconductor substrate. Nonvolatile semiconductor memory device. 5. The split gate structure according to claim 1, wherein the ferroelectric gate transistor and the cutoff transistor are formed by forming a metal layer of the ferroelectric gate transistor halfway in a channel region. A non-volatile semiconductor memory device comprising: 6. The nonvolatile semiconductor memory device according to claim 5, wherein an impurity region is formed in the semiconductor substrate between a region forming the ferroelectric gate transistor and a region forming the cutoff transistor. A non-volatile semiconductor memory device characterized in that the ferroelectric gate transistor and the cutoff transistor are separated from each other. 7. The non-volatile semiconductor memory device according to claim 1, wherein the control electrode of the ferroelectric gate transistor and the control electrode of the cutoff transistor are shared. . 8. The non-volatile semiconductor memory device according to claim 1, wherein the cutoff transistor is configured as a MIS transistor including a metal gate, an insulator and a semiconductor substrate. 9. The non-volatile semiconductor memory device according to claim 8, wherein the MIS transistor is a first MIS.
A first gate electrode of the ferroelectric gate transistor, and a second MIS transistor.
Coupled to the second electrode of the MIS transistor, the second electrode of the ferroelectric gate transistor is coupled to the first electrode of the second MIS transistor, and the control terminal of the ferroelectric gate transistor and the A non-volatile semiconductor memory device characterized in that the control terminals of the first and second MIS transistors are commonly coupled. 10. A ferroelectric gate transistor having a first electrode, a second electrode and a control electrode, and a cutoff transistor having a first electrode, a second electrode and a control electrode, wherein A non-volatile memory device, wherein one electrode is coupled to a second electrode of the cutoff transistor, and the control terminal of the ferroelectric gate transistor and the control terminal of the cutoff transistor are commonly connected. 11. The non-volatile memory device according to claim 10, wherein the ferroelectric gate transistor has an MFS structure including a metal gate, a ferroelectric and a semiconductor substrate. 12. The non-volatile memory device according to claim 10, wherein the ferroelectric gate transistor comprises a metal gate, a ferroelectric substance, an insulator, and a semiconductor substrate.
A non-volatile memory device having an IS structure. 13. The non-volatile memory device according to claim 10, wherein the ferroelectric gate transistor has an MFMIS structure including a metal gate, a ferroelectric, a metal layer, an insulator and a semiconductor substrate. Non-volatile memory device. 14. The non-volatile memory device according to claim 10, wherein the ferroelectric gate transistor and the cutoff transistor have a split gate structure in which a metal layer of the ferroelectric gate transistor is formed halfway in a channel region. A non-volatile memory device characterized by being configured. 15. The nonvolatile memory element according to claim 14, wherein an impurity region is formed in the semiconductor substrate between a region forming the ferroelectric gate transistor and a region forming the cutoff transistor. A non-volatile memory device, wherein the ferroelectric gate transistor and the cutoff transistor are separated from each other. 16. The non-volatile memory element according to claim 10, wherein the control electrode of the ferroelectric gate transistor and the control electrode of the cutoff transistor are shared. 17. The non-volatile memory device according to claim 10, wherein the cutoff transistor is configured as a MIS transistor having a metal gate, an insulator and a semiconductor substrate. 18. The non-volatile memory element according to claim 17, wherein the MIS transistor is a first MIS.
A first gate electrode of the ferroelectric gate transistor, and a second MIS transistor.
Coupled to the second electrode of the MIS transistor, the second electrode of the ferroelectric gate transistor is coupled to the first electrode of the second MIS transistor, and the control terminal of the ferroelectric gate transistor and the A non-volatile memory device, wherein the control terminals of the first and second MIS transistors are commonly coupled.