JP2003067360A - Method and device for sum of products calculation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a sum of products calculation requiring a large amount of calculations in an orthogonal transformation processing. SOLUTION: This device for sum of products calculation comprises a data selection means 2 for selecting eight pieces of data in unit of sum of products calculation from a data storage means 1, a zero/non-zero judgment means 3 for judging whether each of the selected eight pieces of data is zero or not zero, an address transformation means 4a for performing, based on the positions of the non-zero elements in the eight pieces of data, an address transformation for a data address generated in a CPU 6 so that only the non-zero elements can be read out continuously, and an address transformation means 4b for performing an address transformation for a conversion factor generated in a CPU 6 so that the conversion factor for the non-zero element can be read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sum-of-products calculation method and a sum-of-products calculation for high-speed orthogonal transformation processing used for signal processing such as information compression of sound information, image information, video information, and coding. The present invention relates to a computing device.

[0002]

2. Description of the Related Art As information devices have become more sophisticated, orthogonal transform processing, which is essential for encoding and compressing information, has become more important. In addition, in terms of versatility of information equipment, and in order to respond to the speed of technological innovation, more general-purpose hardware and an orthogonal transform processing method that can support more general data structures are required. There is.

For the sake of concrete description, the JPEG process, which is a widely used still image coding technique, will be taken as an example below. JPEG is an image compression / encoding method that includes discrete cosine transform (DCT), quantization, run-length encoding, Huffman encoding, and the like as technical elements. 6 to 8 are for the purpose of simply explaining these.

FIG. 6 schematically shows the cutout of data blocks A1, A2, A3, ... As the unit of JPEG processing from the image data D1. JPEG processing is N
And M are natural numbers, and this is performed for a data block of size 8N × 8M. The 8Nx8M data block is
The data is thinned out and finally the size becomes 8x8.
The JPEG processing itself is performed on all 8 × 8 data blocks. Therefore, the description will be given below by taking an 8 × 8 data block as an example.

As a concrete example, it is assumed that the data of a certain data block is as shown in FIG. JPE
The first step of G processing is to perform DCT processing on it. The DCT process is a kind of orthogonal transform and transforms image data into the frequency domain. If the DCT process is expressed by a mathematical formula,

[0006]

[Equation 1]

It is expressed as follows. In the equation (1), P is image data, C is a conversion coefficient, and i and j indicate the positions of pixels in the horizontal and vertical directions, respectively. Also, m,
n indicates frequency components in the horizontal and vertical directions, respectively. Further, B is a bias value for converting pixel data that is originally unsigned data into signed data for convenience of calculation. S obtained by the above calculation is a transformation of the original image into the frequency domain.

By this processing, the data shown in FIG.
It is converted into the data of FIG. When decoding the image,
For this data, the inverse DC as shown in equation (2) below
The original data is restored by performing the T process.

[0009]

[Equation 2]

The next step in JPEG processing is quantization. Human visual characteristics are sensitive to low frequency data, and conversely insensitive to high frequency data. By using this characteristic, the data in the low frequency region can be expressed on a finer scale, while the data in the high frequency region can be expressed on a coarser scale, thereby reducing the overall data amount. . Such an operation is called scalar quantization.

If a quantization scale as shown in FIG. 7 (d) is used, the data shown in FIG. 7 (b) is quantized into the data shown in FIG. 7 (c). As is clear from FIG. 7C, the number of zero elements is increasing.

The next step in the JPEG process is run-length coding. 8 and 9 are for explaining this. First, 64 elements of 8 × 8 are rearranged into one column of data as shown in FIG. 8B in a zigzag scan order as shown in FIG. 8A. This means that there is data on the low frequency side in a dimensional sense at the beginning, and the data on the high frequency side is arranged in a later order.

FIG. 9 is an example in which the data of FIG. 7C is rearranged, and the data of FIG. 9A is rearranged as shown in FIG. 9B. In actual run length coding, the chain of zeros in this sequence is further coded. For example, as shown in FIG. 9C, when the data after a certain position are all zero, all the chains of the zeros are replaced with one data terminal symbol (End Of Block, EOB for short). Further, other zeros can be replaced with symbols, but this is omitted because it is far from the gist of the present invention.

The next step in JPEG is Huffman encoding, which is also omitted from the point of the present invention.

By the way, in the processing of the entire JPEG, especially the DCT processing requires a very large amount of calculation. In other words, speeding up this part leads to speeding up of the entire JPEG processing. Hereinafter, taking the DCT operation as an example, the speedup will be described.

The DCT operation is as shown in the above equation (1), which is executed as a two-step one-dimensional process as shown below.

[0017]

[Equation 3]

[0018]

[Equation 4]

In order to make this calculation easier to understand, the conversion coefficient is

[0020]

[Equation 5]

When written in the form of matrix calculation, the following form is obtained.

[0022]

[Equation 6]

[0023]

[Equation 7]

This is schematically shown in FIG. 10 (a),
As in (b), the row-direction arithmetic processing and the column-direction arithmetic processing (each indicated by an arrow in the processing direction) are sequentially executed from either the row or the column. What is important here is that there is a degree of freedom regarding the execution order of equations (3) and (4). In principle, the final result does not depend on this order of execution, except for errors due to operations being performed with finite precision.

Speeding up the DCT calculation is equivalent to speeding up such matrix calculation. In order to increase the speed, there are the following methods used in the conventional example.

The method used in Japanese Patent Laid-Open No. 4-70060 is to skip the DCT operation when all the data in the data block are zero.

As is clear from the above equation, under such conditions, the calculation results are all zero, so the calculation can be omitted. Such a condition is highly likely to be satisfied especially when it is called a progressive type.

The method used in Japanese Patent Laid-Open No. 4-137975 is such that, in hardware capable of performing four parallel operations, the operation is skipped when the four elements are zero.

The accuracy of the data used in the DCT calculation is 1
Often 6 bits, four pieces of data can be processed simultaneously in hardware having a 64-bit arithmetic register. This parallel operation speeds up the processing, and further speeds up the processing by omitting the operation when the data for which the result is trivial is zero. This technique is also described in JP-A-4-200079.

The method used in Japanese Patent Laid-Open No. 4-220081 is similar to the above-mentioned Japanese Patent Laid-Open No. 4-70060, but the data in the data block is a DC component, that is, (0, 0) element. It corresponds to the case of only. At this time, all the data have the same value in the DCT calculation result, and the calculation result can be obtained only by calculating one data.

Further, the method used in Japanese Patent Laid-Open No. 10-63646 has a plurality of arithmetic means corresponding to the state of data, and selects the most suitable arithmetic means among these arithmetic means according to the position of EOB. The calculation speeds up.

FIG. 11 simply illustrates this. Assuming that the EOB appears at the position shown in FIG. 11A, the data after that are all zero, as described above. On the contrary, the data before that are likely to be non-zero. In other words, fill the non-zero data position,
When displaying the position of data that is zero without filling,
The distribution of zero and non-zero data when EOB appears at a certain point is likely to be as shown in FIG. 11 (b). The DCT calculation can be speeded up by preparing a plurality of calculation means corresponding to the bias of the data and selecting the most suitable calculation means.

Japanese Unexamined Patent Publication No. 10-322699 has a similar concept to the above example, but the data area is divided into two areas in advance, and the fast DCT algorithm is always used in the low frequency area where the data is likely to be not zero. Is performed, and normal DCT is performed in other areas. As shown in FIG. 12A, for example, the data area is divided into four areas, and it is assumed that the upper left area Z1 always has data. As shown in FIG. Are all to be processed, and the other areas are individually judged and processed as zero and non-zero.

By fixing the processing to some extent, this reduces the load for condition judgment required in the prior art example.

Japanese Unexamined Patent Application Publication No. 11-41601 uses all of the four parallel operations described above, a plurality of operation means, and the condition determination based on the EOB position.

[0036]

The above-mentioned conventional examples are effective, respectively, but the following problems remain.

Japanese Unexamined Patent Publication Nos. 4-70060 and 4-2.
What is described in 20081 is speeding up only when the data is in a special state, and is less effective under more general conditions.

JP-A-4-137975 and JP-A-4-137975
The one based on the four parallel operation hardware as described in 201009 has a heavy load of sorting and disassembling four data, and a load of determining whether the four data are zero or non-zero. Further, although the effect of the four parallel arithmetic processing is very large, it is not effective except for hardware having such a function.

As a concrete example, assume the data as shown in FIG. It is assumed that the filled parts in the figure are non-zero elements. In this case, if four parallel operations are used, FIG.
It is necessary to perform the calculation for the element at the filled position in 3 (b). Of course, due to the effect of the parallel operation, it is considered that the increase of the operation processing time is small, but at the same time, there is no effect of speeding up the processing as compared with the simple processing. In addition, data zero / non-zero determination and data alignment / decomposition processing are additionally required.

Japanese Unexamined Patent Publication No. 10-63646 and Japanese Unexamined Patent Publication No. 10-322699 have a plurality of arithmetic means, which increases the complexity of processing. Further, the condition judgment based on EOB is not always effective. For example, assume the same data as shown in FIG. 14A as above. Then,
The determination by EOB is based on the assumption that the data shown in FIG. 14B is used, and it is necessary to perform a very redundant calculation. Japanese Patent Laid-Open No. 11-41601 is also similar to the above.

As described above, the method for speeding up the orthogonal transformation process in the conventional example is applicable only to the case of special data, and also assumes a specific hardware structure. In addition, some of them require a very complicated structure.

The present invention solves the above problems and provides sound information,
It is an object of the present invention to provide a product-sum calculation method and a product-sum calculation device for performing high-speed orthogonal transformation processing used for information processing such as image information and video information and signal processing such as encoding.

[0043]

In order to achieve the above-mentioned object, the product-sum calculation method of the present invention performs a product-sum calculation by sequentially reading N pieces of data constituting a product-sum calculation unit in a predetermined address order. In the multiply-accumulate operation method, it is determined whether each of the N pieces of data is zero or non-zero, and based on the information indicating the position of the non-zero element in the N pieces of data, Address conversion is performed so that only non-zero elements can be continuously read, and the product-sum operation is sequentially performed on the data read by the converted address.

In this product-sum operation method, the address conversion based on the position where the non-zero element exists in the N pieces of data is also performed for the address for reading the conversion coefficient necessary for performing the product-sum operation. The conversion coefficient corresponding to the non-zero element is read by the converted address.

In addition, the product-sum calculation apparatus of the present invention is a data-processing apparatus that performs a product-sum calculation by sequentially reading out N pieces of data forming a product-sum calculation unit in a predetermined address order. Is stored in the data storage means, the data selection means that cuts out N pieces of data, which is a unit of product operation, from the data to be processed stored in the data storage means, and the N selected by the data selection means. Based on the information indicating the position where the non-zero element exists in the zero / non-zero determination means for determining whether each of the data is zero or non-zero and the zero / non-zero determination result, with respect to the address,
Address conversion means for performing address conversion such that only the non-zero element can be continuously read, and the product-sum operation is performed on the data read by the address after the address conversion by the address conversion means. The means is used to perform the sum of products operation.

In such a product-sum calculation device, the N
Address conversion means for performing address conversion based on the position where a non-zero element exists in each piece of data, data address conversion means for performing address conversion for addresses for sequentially reading the N pieces of data, and the conversion coefficient A conversion coefficient address conversion unit for performing address conversion on the address for reading the data is provided, and only the non-zero element can be continuously read by the data address conversion unit for the address for reading the data. The address conversion is performed so that the address for reading the conversion coefficient is subjected to the address conversion so that the conversion coefficient address conversion means can read the conversion coefficient corresponding to the non-zero element. I have to.

As described above, according to the present invention, it is determined whether each of the N pieces of data forming the product-sum operation unit is zero or non-zero, and the information indicating the position where the non-zero element exists in the N pieces of data is used. Based on, for example, CPU and DSP (Digi
(Tal Signal Processor) etc., the address conversion is performed so that only the non-zero elements can be continuously read, and the addresses are read in the address order after the address conversion. The product-sum operation is sequentially performed on the data.

In this way, consecutive addresses generated by the CPU, DSP, etc. (N pieces of data cut out as a unit of multiply-accumulate operation are stored in order from the data position 0, 1, for example.
2, 3, ...) are converted into addresses in which only non-zero element data can be sequentially accessed, and the data is read in the converted address order to perform the multiply-accumulate operation. There is.

As a result, the CPU, DSP, etc. simply read the data to be operated by consecutive addresses and perform the sum-of-products operation, but in reality, only non-zero elements that are sparsely and only randomly exist. Will be read continuously one after another. Therefore, even if the data of the non-zero elements to be subjected to the multiply-accumulate operation exist in a sparse state, the non-zero elements in the sparse state can be continuously read one after another.
It is possible to efficiently perform the product-sum calculation amount that accompanies the orthogonal transform processing, and to significantly reduce the calculation amount.

Further, since the address conversion is performed also for the address for reading the conversion coefficient necessary for performing the product-sum operation, it corresponds to the non-zero element data existing in a sparse state. Only the transform coefficients can be accessed sequentially.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. The contents explained in this embodiment are
It is an explanation of the product-sum calculation method and the product-sum calculation device of the present invention.

Although the product-sum calculation method and the product-sum calculation device of the present invention are not applied to a specific orthogonal transformation,
In this embodiment, for concrete description, a case where the present invention is applied to JPEG processing which is a widely used still image coding technique is taken as an example.

The basic idea of the present invention is that a general CP
In the U and DSP, the product-sum operation efficiency is poor when the data to be sum-added are sparsely arranged side by side, but the product-sum operation is efficiently performed on the data that are densely arranged. It utilizes what can be done.

Therefore, in the present invention, the address conversion processing depending on the data positions arranged in a sparse state is performed, so that the software in the product-sum operation processing means such as the CPU and the DSP is as if the data is densely packed. Is made to appear as if they are distributed.

The present invention can be roughly divided into two processes (the first process and the second process).

In the first process, N pieces of one product-sum operation unit are formed from the data storage means in which the data to be processed is stored (here, since JPEG is taken as an example, N =
8) This is a non-zero element position determination process of cutting out data and determining at what position the non-zero element exists in the product-sum operation unit.

The second process is an address conversion process for converting the address generated by the CPU or DSP based on the determination process of the non-zero element position determined by the first process.

The addresses generated by the CPU and DSP are, in this case, addresses for sequentially reading eight data (referred to as data addresses) and addresses for reading conversion coefficients corresponding to the respective data ( (There is a conversion coefficient address), and it is necessary to perform address conversion of both the data address and the conversion coefficient address. However, since the address conversion processing can be considered in the same way, first, the processing for the data address will be described. .

FIG. 1 is a diagram for explaining the first process, and FIG. 2 is a diagram for explaining the second process. In FIG. 1, eight pieces of data cut out from the data stored in the data storage means 1 as the product-sum operation unit (as described above, since JPEG is taken as an example, one product-sum operation unit) As 8 pieces of data, and the data position is "0" to "7"
Is expressed by the data selection means 2 and the zero / non-zero judgment means 3 judges the zero / non-zero of the cut-out eight data.

Here, the black-painted portion is a non-zero element, the data of the non-zero element is represented by "1", and
If the zero element data is represented by "0", this cut-out 8
The result of the zero / non-zero judgment for each piece of data is “1001011
It becomes 0 ". When expressed in decimal, it becomes" 150 ", and the address conversion processing is performed based on the information indicating the position of the non-zero element which is the result of the zero / non-zero judgment by the zero / non-zero judgment means. .

First, the address conversion means performs the addressing mode setting process using the information indicating the position of the non-zero element. This addressing mode setting process is performed by "0" to "25" in the addressing mode selection means 41.
This is a process of acquiring the addressing data in the addressing data storage means 42 by using the position of "150" of "5" as a key.

The addressing data storage means 42 stores "0" to "2" in the addressing mode selection means 41.
The data length and the data position corresponding to each of "55" are described. For example, "150" of the addressing mode selecting means 41 has a data length of "4" and data positions of "1, 2, 4, 7". ".
That is, “15” of the addressing mode selection means 41
“0” has four non-zero element data out of eight data, and four of them are data positions of “0” to “7”.
It is shown that it exists at the positions of "1", "2", "4", and "7".

Incidentally, "0" of the addressing mode selection means 41 means that there is no non-zero element, so that the data position does not exist. Further, in "255" of the addressing mode selection means 41, all eight data are non-zero elements, and the eight data are "0",
"1", "2", "3", "4", "5", "6",
It indicates that the data exists at the data position of "7".

In this way, the number of non-zero elements and their data positions are set for the eight pieces of data cut out as one product-sum operation unit. Then, the address conversion process based on the contents set in this way is performed. This address conversion process is performed as shown in FIG.

First, the base address stored in the base address storage means 43 (the address set as the first address for the eight pieces of data cut out as the product-sum operation unit) is read out and read out. A base address (0x1000) is a continuous address generated by a CPU or DSP as a product-sum operation processing unit so as to sequentially read out eight pieces of data cut out as a product-sum operation unit (this is a virtual address here). Called address, 0x
1000,0x1001, 0x1002, ...)). The virtual address output from the CPU or DSP is input to the virtual address input means 44.

For example, when the base address 0x1000 is subtracted from the virtual address 0x1000, it is "0". The addressing data of the addressing data storage means 42 set in FIG. 1 (in this case, the data length is The data position is "1,"
2, 4, 7 ”),“ 1 ”is written as the data position, and this“ 1 ”is set to the base address 0x10.
00 to obtain 0x1001 as the physical address. This physical address 0x1001 is stored in the physical address storage means 45.

Similarly, when the base address 0x1000 is subtracted from the virtual address 0x1001, the result is "1", and with the "1" as a key, the addressing data of the addressing data storage means 42 set in FIG. The data position is "1,"
2, 4, 7 ”), in this case,“ 2 ”is written as the data position, and this“ 2 ”is added to the base address 0x1000 to obtain the physical address 0x1.
002 is obtained. This physical address 0x1002 is stored in the physical address storage means 45.

When the base address 0x1000 is subtracted from the virtual address 0x1002, the result is "2",
Using the "2" as a key, the addressing data of the addressing data storage means 42 set in FIG. 1 (similarly, the data length is "4" and the data position is "1, 2,
4, 7 ”), in this case,“ 4 ”is written as the data position, and this“ 4 ”is added to the base address 0x1000 to obtain the physical address 0x1.
To get 004. This physical address 0x1004 is stored in the physical address storage means 45.

Further, when the base address 0x1000 is subtracted from the virtual address 0x1003, it is "3", and with the "3" as a key, the addressing data of the addressing data storage means 42 set in FIG. The data position is "1, 2,
4, 7 ”), in this case,“ 7 ”is written as the data position, and this“ 7 ”is added to the base address 0x1000 to obtain the physical address 0x1.
Get 007. This physical address 0x1007 is stored in the physical address storage means 45.

By such processing, the CPU and DSP
Generated virtual addresses 0x1000, 0x1001,
Physical address 0x for 0x1002 and 0x1003
1001,0x1002,0x1004,0x1007
Is obtained.

This physical address 0x1001, 0x10
02, 0x1004, 0x1007 are addresses indicating the positions corresponding to the non-zero elements for the eight pieces of product-sum operation units cut out by the data selecting means 2 shown in FIG.

As described above, according to the present invention, when the data of the non-zero elements to be sum-of-products calculated are lined up in a sparse manner, the CPU and When viewed from the DSP side, the non-zero element data scattered in a sparse state will appear as if they were continuously arranged in a dense state.

This is a common CPU, as described above.
In a DSP or DSP, the product-sum operation efficiency is poor when the data to be subjected to the product-sum operation are arranged side by side in a sparse state. However, the product-sum operation can be efficiently performed on the data existing in a dense state. This is what is possible, and is extremely convenient for a CPU or DSP in which a program that performs a product-sum operation on such continuous data is set.

That is, even if the non-zero element data to be subjected to the multiply-accumulate operation among the eight pieces of data cut out as the multiply-accumulate operation unit exist only in a sparse state, the address conversion processing described above is performed. , The CPU and DSP only read the data to be calculated by successive addresses and perform the multiply-accumulate operation. In reality, only the non-zero elements existing only in the sparse state are continuously read. Will be done. As a result, the product-sum calculation can be performed efficiently, the amount of calculation can be significantly reduced, and high-speed product-sum calculation can be performed.

FIG. 3 is a flowchart showing the procedure of the processing described above. Although overlapping with the above description, the processing procedure will be described again with reference to FIG. 3. First, N pieces of data cut out as a product-sum operation unit (JPEG is taken as an example in this embodiment). Therefore, eight pieces of data) are cut out (step s1), and it is determined whether or not each piece of the cut out eight pieces of data is zero (step s2).

Then, by the zero / non-zero determination processing,
According to the non-zero determination result, the addressing mode setting means 41 and the addressing data storage means 42 are used to set the addressing mode (step s3).

This is to obtain the addressing data depending on the information indicating the position of the non-zero element obtained from the zero / non-zero determination result from the addressing data storage means 42. In the example of FIG. The zero / non-zero judgment result of the cut out eight data is "10010".
110 ", which is the decimal number" 150 "
As the key, the addressing mode selection means 41 acquires the addressing data having the data length “4” and the data positions “1, 2, 4, 7” from the addressing data storage means 42 and sets it.

Then, the base address is set together with the addressing mode setting (step s).
4). This base address is 0x1000 here, as described above. Then, the number of remaining data is set to the data length (step s5). Setting the number of remaining data to the data length means setting the data length obtained by the addressing data storage means 42.
In the above example, since the data length obtained by the addressing data storage means 42 is "4", that "4" is set.

Then, it is judged whether or not the number of remaining data is zero (step s6), and if it is zero, the processing is terminated. If it is not zero, the sum of products is applied to the data at the address designated by the physical address. Calculation is performed (step s7).

Next, 1 is added to the virtual address (step s8), and 1 is subtracted from the number of remaining data (step s8).
9) and returns to the process of step s6. This is for example
When the multiply-accumulate calculation process for the virtual address 0x1000 is completed, 1 is added to 0x1001, and "1" is subtracted from the remaining data number (4 in this case) at that time to set the remaining data number to "3" and step s6 is executed. Done, in this case,
Since the number of remaining data is not zero, virtual address 0x1001
Is performed with the physical address 0x1002 for

Then, when the product-sum operation processing for this virtual address 0x1001 is completed, 1 is added to it and 0 is added.
x1002 and the number of remaining data at that time (3 in this case)
Is subtracted from "1" to set the number of remaining data to "2", and step s6 is performed. In this case, since the number of remaining data is not zero,
Physical address 0x1 for virtual address 0x1002
The sum of products operation according to 004 is performed.

When the product-sum calculation process for this virtual address 0x1002 is completed, 1 is added to it and 0x100 is added.
3, and "1" is subtracted from the number of remaining data (2 in this case) at that time to set the number of remaining data to "1".
6. In this case, since the remaining data number is not zero, the physical address 0x100 with respect to the virtual address 0x1003
The sum of products operation according to 7 is performed.

When the product-sum operation processing for this virtual address 0x1003 is completed, 1 is added to it and 0x100 is added.
4 and subtract “1” from the number of remaining data (1 in this case) at that time to set the number of remaining data to “0”
If step 6 is performed, the number of remaining data is zero in this case, so the process ends.

As described above, the CPU and DSP generate continuous data addresses and perform arithmetic processing in accordance with the continuous data addresses. However, in reality, the product in which the continuous addresses exist in a sparse state is used. A process of converting the data to be summed into physical addresses pointing one after another is performed, and as a result, only non-zero elements that exist only in a sparse state are continuously read out.

When the sum of products operation is performed, the conversion coefficient shown in the equations (6) and (7) is used. For this conversion coefficient, nonzero elements existing in a sparse state are also used. It is necessary to read corresponding data, and the conversion coefficient address for reading the conversion coefficient also needs to be subjected to the same address conversion as described above.

FIG. 4 is an overall block diagram of the product-sum calculation apparatus of the present invention. Data storage means 1 for storing the data to be processed, and this data storage means 1 constitutes one product-sum calculation unit. Data selecting means 2 for cutting out data (here, 8 pieces of data), and zero / non-zero for judging 0 or non-zero with respect to 8 pieces of data of the product-sum operation unit cut out by this data selecting means 2. Judgment means 3, address conversion means for performing the above-mentioned address conversion processing (this address conversion means has an address conversion means 4a for a data address and an address conversion means 4b for a conversion coefficient address), and a conversion necessary for performing a product-sum operation. Transform coefficient storage means 5 for storing coefficients, CPU or D for performing product-sum calculation processing
It is composed of an SP (here, CPU) 6.
Note that, of the constituent elements in FIG. 4, the same constituent elements as those shown in FIGS. 1 and 2 are designated by the same reference numerals.

The address conversion means 4a and 4b have an addressing mode selection means 41, an addressing data storage means 42, and a base address storage means 43, respectively, and operate as described with reference to FIGS. To do.

FIG. 5 is a block diagram showing this FIG. 2, and in addition to the base address storage means 43, the addressing mode selection means 41, and the addressing data storage means 42, a data address generated by the CPU 6 or a conversion coefficient. It is configured to have a virtual address input means 44 for inputting an address as a virtual address, and a physical address storage means 45 for storing a physical address generated by performing address conversion processing on the virtual address.

The CPU 6 uses the data address generating means 61,
The conversion coefficient address generation means 62 and the product-sum calculation means 63 are provided. The data address and the conversion coefficient address are generated, and the product-sum calculation processing is performed.
It also has a function of controlling the overall operation of each component shown in FIG.

The address generated by the data address generating means 61 is an address (data address) for sequentially reading out eight pieces of data cut out as a product-sum operation unit.
This data address is given to the address conversion means 4a and inputted as a virtual address to the virtual address input means 44 (see FIG. 5) included in this address conversion means 4a.

Further, the address generated by the conversion coefficient address generation means 62 is an address (conversion coefficient address) for reading the conversion coefficient, and this conversion coefficient address is given to the address conversion means 4b to perform this address conversion. The virtual address input means 44 (FIG. 5) included in the means 4b.
Input) as a virtual address.

Since the address conversion processing of the address conversion means 4a and 4b in the product-sum calculation device having such a configuration has already been described in detail, the description of the address conversion processing will be omitted and the overall processing will be omitted. explain.

First, as described with reference to FIG. 1, the addressing mode selection means 41 is operated by the addressing data storage means 42 based on the information indicating the position of the non-zero element in the eight pieces of data cut out as the product-sum operation unit. Information indicating a certain data length and data position is designated, and information indicating the data length and data position is set as addressing data. Then, as described in FIG. 2, the CPU
No. 6 continuous data address generated by the data address generating means 61 (virtual addresses 0x1000, 0x10
, 0) by the address conversion means 4a, the physical addresses (0x1001,0 in the above example) that continuously indicate only non-zero elements.
x1002, 0x1004, 0x1007),
The data indicated by the physical address is read from the data storage means 1, and the read data is given to the product-sum calculation means 63.

On the other hand, similarly, the conversion coefficient address generated by the conversion coefficient address generation means 62 of the CPU 6 is subjected to the address conversion processing by the address conversion means 4b in the same manner as the data address, so that the conversion coefficients corresponding to the non-zero elements are consecutive. To generate a physical address that is physically pointed to, and the conversion coefficient storage unit 5
The conversion coefficient indicated by the physical address is read from, and the read conversion coefficient is used as the product-sum calculation means 63.
Given to.

In this way, the address translation means 4a, 4b
The non-zero element data is sequentially read by the physical address generated by, and the conversion coefficient corresponding to the non-zero element is sequentially read, and these are supplied to the sum-of-products calculating means 63 to perform the sum-of-products calculation. Be seen.

At this time, only the continuous data address and the conversion coefficient address are generated from the CPU 6, but the continuous data address and the conversion coefficient address are non-zero elements existing in a sparse state and The corresponding conversion coefficients are converted into physical addresses that successively point to each other, so that even if the non-zero element data to be subjected to the multiply-accumulate data exist in a sparse state, the CP
U6 merely generates continuous data addresses and conversion coefficient addresses, reads out data according to the data addresses, and performs a product-sum operation. In reality, sparse nonzero element data and Since only the corresponding conversion coefficient is sequentially read out to perform the product-sum calculation, efficient product-sum calculation can be performed, and the amount of calculation can be significantly reduced.

The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present invention.

Further, according to the present invention, a processing program in which a processing procedure for realizing the above-described present invention is described is created, and the processing program is recorded in a recording medium such as a floppy disk, an optical disk, a hard disk. The present invention also includes a recording medium in which the processing program is recorded. Further, the processing program may be obtained from the network.

[0099]

As described above, according to the present invention,
It is determined whether each of the N pieces of data forming the product-sum operation unit is zero or non-zero, and based on the information indicating the position where the non-zero element exists in the N pieces of data, the CPU and the DS
Addresses generated by the product-sum operation processing means such as P are subjected to address conversion so that only non-zero elements can be continuously read out, and data read out in the address order after the address conversion is performed. The sequential product-sum calculation is performed.

As described above, continuous addresses generated by the CPU or DSP are converted into addresses in which only non-zero elements can be sequentially accessed, and the data is read in the converted address order to perform the product-sum operation. I am trying to do it.

As a result, the CPU, DSP, etc. simply read the data to be operated by consecutive addresses and perform the sum-of-products operation. In reality, only non-zero elements that exist only in a sparse state are successively detected. Will be read continuously. Therefore, even if the non-zero element data to be subjected to the multiply-accumulate operation exist in a sparse state, the non-zero elements in the sparse state and the corresponding conversion coefficient are continuously read one after another. As a result, the product-sum operation associated with the orthogonal transform process can be efficiently performed, and the amount of the operation can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a product-sum calculation process of the present invention, in which eight pieces of data serving as a product-sum calculation unit are cut out from data to be processed, and how non-zero elements are included in the eight pieces of data. It is a figure explaining the process which judges whether it exists in a certain position, and acquires the information which shows a data length and a data position based on it.

FIG. 2 is a diagram illustrating a product-sum calculation process according to the present invention.
It is a figure explaining the address translation process which translates the address produced | generated by CPU or DSP based on the process shown by 1.

FIG. 3 is a flowchart illustrating an overall processing procedure of sum of products calculation processing according to the present invention.

FIG. 4 is an overall configuration diagram of a product-sum calculation apparatus of the present invention.

5 is a diagram showing the address conversion operation shown in FIG. 2 as a block diagram.

FIG. 6 shows N × N (8 ×
It is a figure which illustrates the cutout of the data block of 8) typically.

FIG. 7 is a diagram illustrating an example of data of an N × N (8 × 8) data block that is a processing unit, and an example of processing of converting the data into a frequency domain and then performing quantization.

[Fig. 8] Fig. 8 is a diagram for describing run-length encoding processing.

FIG. 9 is a diagram showing a case where the data in FIG. 7C is rearranged and a chain of zeros is replaced with EOB.

FIG. 10 is a diagram illustrating whether the processing for N × N (8 × 8) data blocks as a processing unit is performed in the row direction or the column direction.

FIG. 11 is a diagram for explaining an example of selecting an optimum arithmetic means according to the position of EOB to simplify the orthogonal transform arithmetic in the conventional technique.

FIG. 12 is a processing unit N × N in the related art.
It is a figure explaining the example which aims at simplification of orthogonal calculation by dividing a data block of (8x8) into some areas, and performing a calculation.

FIG. 13 is a problem in performing multiply-accumulate operation on data in N × N (8 × 8) data blocks, which is a processing unit, by four parallel operations (four parallel operations in the row direction) which is one of the conventional techniques It is a figure explaining a point.

FIG. 14 is a diagram for explaining a problem when performing a product-sum operation on the data in N × N (8 × 8) data blocks, which is a processing unit, using the determination of EOB, which is one of the conventional techniques. is there.

[Explanation of symbols]

1 data storage means 2 data selection means 3 zero / non-zero determination means 4a address conversion means (address conversion means for data addresses) 4b address conversion means (address conversion means for conversion coefficient addresses) 5 conversion coefficient storage means 6 CPU 41 addressing mode Selection means 42 Addressing data storage means 43 Base address storage means 61 Data address generation means 62 Transform coefficient address generation means 63 Sum of products calculation means

Claims (4)

[Claims] 1. A product-sum operation method in which N pieces of data forming a product-sum operation unit are sequentially read out in a predetermined address order to perform a product-sum operation, and whether each of the N pieces of data is zero or non-zero is determined. Based on the information indicating the position of the non-zero element in the N data, the address is converted so that only the non-zero element can be continuously read, and the conversion is performed. A product-sum operation method characterized by sequentially performing a product-sum operation on data read by a subsequent address. 2. The address conversion based on the position where a non-zero element exists in the N pieces of data is also performed for an address for reading a conversion coefficient necessary for performing a product-sum operation, and the converted address The sum-of-products calculation method according to claim 1, wherein the conversion coefficient corresponding to the non-zero element is read by. 3. A product-sum calculation apparatus which sequentially reads N pieces of data constituting a product-sum calculation unit in a predetermined address order to perform a product-sum calculation, and data storage means for storing data to be processed. From the data to be processed stored in the data storage means, data selecting means for cutting out N pieces of data serving as a product-sum operation unit and N pieces of data cut out by the data selecting means are each zero or non-zero. Only the non-zero element is continuously read from the address based on the zero / non-zero determining means for determining whether it is zero and the information indicating the position where the non-zero element exists in the zero / non-zero determination result. Address conversion means for performing address conversion so that it becomes possible, and multiply-accumulate operation is performed on the data read by the address after the address conversion by this address conversion means. Product-sum operation unit, wherein the door. 4. The address conversion means for performing address conversion based on the position where a non-zero element exists in the N data is a data address for performing address conversion on addresses for sequentially reading the N data. A conversion unit and a conversion coefficient address conversion unit that performs address conversion on the address for reading the conversion coefficient are provided, and only the non-zero element is provided by the data address conversion unit for the address for reading the data. Is converted so that the conversion coefficient can be continuously read, and for the address for reading the conversion coefficient, the conversion coefficient address conversion unit can read the conversion coefficient corresponding to the non-zero element. 4. The product-sum calculation apparatus according to claim 3, which performs such address conversion.