JP2003067349A - Simd type microprocessor performing table conversion process corresponding to hysreresis of input value - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a table conversion process corresponding to input value hysteresis of a nonlinear operation in an SIMD type microprocessor at few number of operation cycles. SOLUTION: This SIMD type microprocessor is provided with a plurality of processor elements. The predetermined operation in the processor elements that output data corresponding to input data are prepared previously by the predetermined table is defined. The operation is performed continuously in the predetermined order in a plurality of processor elements. A table converter is provided in which the input data are state data and data before conversion, the output data are data after conversion and the next state data, and the next state data in the output data becomes the state data of the input data in the operation concerning the next processor element performed continuously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a SIMD (Single Instruct).
in-stream Multiple Data-s
stream; single instruction multiple data processing type microprocessor.

[0002]

2. Description of the Related Art In a SIMD type microprocessor, the same arithmetic processing can be simultaneously executed on a plurality of data by one instruction. With this function, it is frequently used in applications related to processing (for example, image processing) in which the calculation is the same but the data amount is very large.

In the ordinary arithmetic processing in the SIMD type microprocessor, a plurality of arithmetic units (Proces) are used.
Sor Element [PE]; processor element) is arranged and the same operation is simultaneously performed on a plurality of data. However, in the “non-linear processing” in which the content of the arithmetic processing cannot be expressed by a single arithmetic expression, the arithmetic expression is changed according to the data to be calculated, and therefore the same processing cannot be executed at the same time. Then, it is unavoidable to perform sequential processing for each data, and eventually the effect of being SIMD is lost.

A normal SISD (Single Inst)
ructin-stream Single Data
Even in a processor of the type (-stream; single instruction / single data processing) type, a non-linear processing in which an arithmetic expression is changed according to data to be operated may make a program for performing arithmetic processing very complicated. In order to prevent this, it is general to prepare all the processed data after the calculation with respect to the pre-calculation data, make them into a table, and perform table conversion based on the pre-calculation data to obtain the post-calculation data. Specifically, a RAM (Random Access Mem)
ory), the above table is stored, and the data obtained from the RAM by using the value obtained by adding the address at the head of the table to the pre-computation data as the address pointer is the post-computation data. For example, when the operation data (data before operation / data after operation) is 8 bits, a conversion table having a size of 256 bytes is required.

Since the size of this conversion table increases by the power of 2 (unit) as the bit width of the operation data increases, if the bit width of the operation data is considerably large, the operation data can be divided into arbitrary sections. A method is also disclosed in which the table is divided and the approximate expression in that section is held.

When the table conversion is adopted in the SIMD type microprocessor, it has been considered that a table is required for each operation unit. For example, 256 SIMD (that is, calculation unit [calculation unit, P
[E] has 256 SIMD processors,
8-bit operation data (data before operation / data after operation)
When performing table conversion of 256 bytes (R
For the calculation unit, that is, 256 tables are required on the AM. Therefore, there was a big problem in terms of cost. Therefore, various inventions have been devised and disclosed for the table conversion of the non-linear operation of the SIMD type microprocessor.

In Japanese Patent Laid-Open No. 5-67203, each S
PE (Processor Elemen) in IMD units
(t: processor element) A method has been proposed in which pre-calculation data is sequentially output to the outside from an output register incorporated therein, table conversion is sequentially performed externally, and the converted data is sequentially input to an input register incorporated in the PE. In this method, the number of conversion tables is one, so the increase in cost can be suppressed, but after all, since the processing is sequential, the processing time is PE
However, it is disadvantageous in terms of calculation speed. Also, if this conversion processing is executed in parallel with the normal processing in PE, the total processing time can be reduced,
There are still problems that the input / output registers are used exclusively for this conversion work and cannot be used for other purposes, and if the data after conversion processing is required, the processing time is waited and parallel processing is impossible. Remain.

Japanese Laid-Open Patent Publication No. 7-
In 199919, the situation is almost the same as above. Non-linear operation is performed by installing a dedicated register used as a shift register in PE and inserting a non-linear unit to form a circular communication path. In this case as well, it is necessary to perform cycle processing for the number of PEs. Is.

Further, in Japanese Patent Laid-Open No. 9-305550, data before conversion and data after conversion are sequentially input from the outside, and the data before conversion and the data before calculation input in each PE are compared. A method has been proposed in which the converted data is stored and this value is used as the calculated data. In this case, the calculation processing time depends on the number of combinations of values that can be taken by the pre-calculation data (that is, the number of words in the conversion table). Therefore, when the number of words is smaller than the number of PEs, the speedup is realized. It However, when the pre-computation data is 8-bit data, the number of cycles is about 256 regardless of the number of PEs, and thus there is a problem that the computation processing time becomes long even in this case. Also, a method may be envisaged in which this conversion processing is performed in parallel with other normal processing, but even in that case, the same problem as in JP-A-5-67203 arises.

Further, in Japanese Patent No. 2812292, post-computation data is obtained by giving pre-computation data as an address pointer from each PE to a conversion table RAM having the same number of output ports as PEs. A method has been proposed. In this method, the conversion speed is completed in about one cycle, but the increase of the output ports increases the cost of RAM, and it is impossible to have more than several tens of ports. Therefore, there is a problem that SIMD microprocessors with a large number of PEs cannot be supported.

In the above-mentioned conventional technique, the non-linear processing of the data in each PE in the SIMD type microprocessor equipped with one table converter can be classified into the following two types of data sequential processing.

Processing method: The pre-conversion data is taken out from the PE and used as an address pointer of the corresponding table value, and the global processor (Global Pr)
(GP) or an external memory controller loads the data corresponding to the address into the PE to realize the table conversion. This is repeated for all PEs in sequence.

As will be described later, the global processor (GP) is a main part of the SIMD type microprocessor. The GP itself is a SISD type processor, has a built-in program RAM and data RAM, decodes the program code, and performs various arithmetic processes and various controls related to the SIMD type microprocessor as a whole.

Processing method: When the pre-conversion data is data represented by, for example, 8 bits, 0 to 25 in GP
Set a variable (register) that is incremented by 5. Each of those values from 0 to 255 and each P
At E, each pre-computation data is compared, and if they match, each P
The operation result flag of E is changed (“1” is set).
The post-conversion data corresponding to only the PE whose flag is set is loaded. When the above variable is incremented from 0 to 255, table conversion is realized.

In the case of the above processing method, even if there are a plurality of PEs having the same pre-computation data, the GP has no means for grasping the fact, and in the end, the above processing must be repeated for the number of PEs. Further, in the case of the processing method, since there is no means for the GP to grasp the contents of the pre-computation data of each PE in advance, it is necessary to repeat the total number of pre-conversion data, that is, 256 computations in the above example.

By the way, when the above processing method is followed, P
The values stored in the register files of the individual PEs are sequentially converted into tables one by one in the order in which Es are arranged. At that time, the history of the pre-conversion data input to the table conversion unit, that is, processing that dynamically changes the table used for conversion corresponding to the hysteresis, and the history of the input pre-conversion data itself The process to monitor is
It is expected that additional requirements will be made. However, in the prior art, the focus is only on speeding up the table conversion process. On the other hand, at present, most of the techniques related to the table conversion process that considers the hysteresis of the input value are not disclosed.

As described above, in order to realize the table conversion process corresponding to the hysteresis monitoring of the input value, the process of selecting the table or the input state to be applied to the next data from the result value of the table conversion for one data is performed. , Each PE or GP must calculate. Then, the number of cycles required for table conversion increases as a whole.

[0018]

SUMMARY OF THE INVENTION The present invention relates to a nonlinear operation in a SIMD type microprocessor, particularly in the above PE sequential table conversion processing (processing method),
The object is to realize a table conversion process corresponding to the hysteresis of an input value with a smaller number of operation cycles.

[0019]

The present invention has been made to achieve the above object. A table converter according to a first aspect of the present invention includes a plurality of processor elements, which is a predetermined operation in the processor elements, and output data for input data is prepared in advance by a predetermined table. In a SIMD type microprocessor in which an operation is defined and a plurality of processor elements continuously perform the above operation in a predetermined order, input data is state data and pre-conversion data, and output data is after conversion. The data and the next state data, and the next state data in the output data is a table converter which becomes the state data of the input data in the operation regarding the next processor element that is continuously performed.

In the table converter according to the second aspect of the present invention, the bit lengths of the state data and the next state data are
The table converter according to claim 1, which can be changed and set.

In the table converter according to a third aspect of the present invention, the state data of the input data is the next state data of the output data immediately before the operation relating to the processor element which is continuously performed, or , Or a fixed setting value, which is determined by a condition flag included in each processor element.

A SIMD type microprocessor according to a fourth aspect of the present invention is equipped with the table converter according to the first to third aspects, and a plurality of processor elements are continuously arranged in a predetermined order. SIMD by the above calculation
Type microprocessor.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a SIMD type microprocessor 2 according to the present invention. The SIMD microprocessor 2 is roughly composed of a global processor 4, a register file 6, an operation array 8 and a table conversion unit 50. The table conversion unit 50 includes a memory and register file control unit 52 and a table memory 54.

(1) Global Processor The global processor 4 itself is a so-called SI.
This is an SD type processor, which has a program RAM 10 and a data RAM 12 built therein (see FIG. 2) and decodes the program to generate various control signals. This control signal is supplied to the register file 6 and the arithmetic array 8 in addition to the various built-in blocks. Further, when a GP (global processor) instruction is executed, various arithmetic processing and program control processing are performed using a built-in general-purpose register, an ALU (arithmetic logical operation unit), and the like.

(2) Register file Holds data processed by a PE (processor element) instruction. PE (processor element) 3
As is well known, it is a structural unit that executes individual calculations in a SIMD microprocessor. As shown by the register file 6 and the arithmetic array 8 of FIG. 2, the SI of FIG.
The MD type microprocessor 2 includes four PEs 3. Usually, the PE 3 is set to 256 (or the like), for example. The PE instruction is a SIMD type instruction,
The same processing is simultaneously performed on a plurality of data held in the register file 6. This register file 6
Control of reading / writing of data from / to is performed by control from the global processor 4. The read data is sent to the arithmetic array 8 and written in the register file 6 after the arithmetic processing in the arithmetic array 8.

The register file 6 is the processor 2
It can be accessed from the outside, and apart from the control of the global processor 4, a specific register is read / written from the outside.

(3) Arithmetic array PE instruction arithmetic processing is performed. All processing control is performed from the global processor 4.

(4) Memory and register file control circuit 52 in the table conversion unit 50 Controls access to the register file 6 from outside the processor 2. Further, it is also connected to a table memory (table RAM) 54 in which a table for table conversion is stored, and table conversion can be performed on the data of the register file 6.

FIG. 2 is a block diagram showing a detailed configuration of the SIMD type microprocessor 2 which is a preferred embodiment according to the present invention. FIG. 2 shows an example in which the number of PEs is four. As mentioned above, usually 256 PE etc.
3 is set.

The global processor 4 has a built-in program RAM 10 for storing programs of this processor and a data RAM 12 for storing operation data. Further, a program counter (PC) 14 that holds the address of the program, G0, G1, G2, and G3 registers (1 that are general-purpose registers for storing data for arithmetic processing)
6, 18, 20, 22), a stack pointer (SP) 24 that holds the address of the save destination data RAM at the time of register save / restore, and a link register (LS) (LS) that holds the call source address at the time of subroutine call. IRQ (Interrupt ReQu)
est; interrupt request) and NMI (Non-Maska)
ble Interrupt ReQuest; an LI register (not shown) and an LN register (not shown) for holding a branch source address at the time of a prohibition impossible interrupt request),
A processor status register (P) (not shown) that holds the state of the processor is incorporated.

These registers, instruction decoder (not shown), ALU (not shown), memory control circuit (not shown), interrupt control circuit (not shown), external I.
/ O control circuit (not shown) and GP arithmetic control circuit 5
6 is used to execute the GP instruction.

When the PE instruction is executed, the instruction decoder,
The register file control circuit 58 and the PE operation control circuit (not shown) are used to control the register file 6 and the operation array 8. In addition, data RAM
It is set so that data can be transferred from 12 to a plurality of PE register files 6.

In the register file 6, one P
32 8-bit registers 34 are built in each E unit, and (for example) 256 PE (32) sets are
It has an array configuration. The register 34 is R for each PE.
0, R1, R2 ,. ． ． Called R31. Each register 34 has one read port and one write port for the arithmetic array 8, and is accessed from the arithmetic array 8 by an 8-bit read / write dual-use bus. Of the 32 registers, 24 (R0-R2
3) is accessible from the outside of the processor, and clock (CLK) and address (Address)
By inputting the read / write control (RWB), reading / writing can be performed with respect to an arbitrary register 34. The remaining eight registers (R24 to R31) 34 are used for temporarily storing PE calculation data.

Data RA of the global processor 4 is stored in the remaining eight registers (R24 to R31) 34.
The data from M12 may be written. A write control signal from the global processor 4 and a condition register (T register) 5 (described later) in the arithmetic array 8
3 and the contents of the data (flag) stored in
Eight registers 34 built in the register file 6
(R24 to R31), the data in the data RAM 12 of the global processor 4 has a plurality of PEs (which satisfy the condition).
It is also possible to write to 3 simultaneously. Further, the data RAM 12 is provided with a 64-bit output port, and even one PE 3 can simultaneously write 64-bit data to the eight registers 34.

The arithmetic array 8 contains a 16-bit ALU 36, a 16-bit A register 38, and an F register 40. In the operation by the PE instruction, the data read from the register file 6 or the data given from the global processor 4 is used as an input on one side of the ALU 36, and A
This is performed by using the contents of the register 38 as the input on the other side. The calculation result is stored in the A register 38. Therefore, the data given from the R0 to R31 register 34 or the global processor 4 and the A register 3
An operation will be performed with the data stored in 8.

The 8-bit data of the register file 6 is shifted by the shift / expansion circuit 44 by an arbitrary bit,
Left shift and input to ALU36.

<< First Embodiment >> SIM according to the present invention
The D-type microprocessor 2 sets the table conversion unit 50 to 1
The non-linear operation of the data in each PE 3 is carried out by the table mounted therein and contained therein. In addition, the SI according to the present invention
In the MD type microprocessor 2, “By extracting the pre-conversion data from the PE and using it as the address pointer of the corresponding table value, the GP or the external memory controller loads the data corresponding to the address into the PE, Table conversion is performed. This is repeated for all PEs in sequence. "

Further, the SIMD microprocessor 2 according to the present invention performs a process of selecting one table from a plurality of tables corresponding to the hysteresis of the input data before the table conversion. That is, (1) A plurality of conversion tables are prepared for one non-linear operation. Each table (case) is regarded as one "state". This constitutes a state machine. (2) The contents are different. (3) The conversion table used in the next (successive) data conversion is dynamically selected by monitoring the state transition of the input data after the table conversion. Such processing is performed.

That is, if the input data before table conversion and the "state" at that time are fixed, the data after table conversion and the next "state" are uniquely determined. In such a table conversion process, it becomes possible to configure a state machine by including the transition destination state value after conversion in the output data, thus enabling dynamic table selection and hysteresis of the input value. Become.

FIG. 3 shows a memory configuration, particularly a table memory configuration, for realizing the above table conversion processing. In the table memory of FIG. 3, the number of bits of data to be handled is n bits (n ≧ 0) and the “state” number is represented by s bits (s ≧ 0). If the bit width of one word is w bits, s + n ≦
w.

In the memory table of FIG. 3, the combination of the n-bit pre-conversion data and the "state" represented by s bits is an address that serves as an address pointer. The following transition destination state (data related to) is stored. The s-bit indicating the state may be arranged higher or lower than n bits.

FIG. 4 shows a detailed configuration of the table conversion unit 50 of the first embodiment in the SIMD type microprocessor 2 according to the present invention. The operation of the table conversion unit 50 will be described below.

First, an address pointer ((n + s) bits) is generated from the pre-conversion data (n bits) read from the memory and register file control circuit 52 in FIG. 2 and the initial state value (s bits). To be done. With this address pointer, the table memory 62 of FIG.
From, the converted data (n bits) and the next transition destination state value (s bits) are acquired. This "next transition destination state value"
The (s bit) is returned to the address generator 60. Next, the pre-conversion data (n bits) read subsequently from the memory and register file control circuit 52 in FIG.
And the transition destination state value (s bit) generate the next address pointer. Based on this address pointer, the converted data (n bits) and the (next) next transition destination state value (s bits) are newly acquired from the table memory 62 of FIG.

At the time of creating the address pointer, it goes through the first selector 64 and the second selector 66. The first selector 64 selects the required n bits as the pre-conversion data and sets it at an appropriate position (lower in the figure) in the address pointer. The second selector 66 selects an s bit required as an initial state value or a transition destination state value, and sets it at an appropriate position (higher in the figure) in the address pointer. The third selector 68 and the fourth selector 70 are used to output the converted data and obtain the next transition destination state value. Third
Selector 68 selects n bits as post-conversion data from an appropriate position (lower in the figure) in the output data.
The fourth selector 70 selects s bits as the next transition destination state value from an appropriate position (higher in the figure) in the output data.

In setting the address pointer to the table memory 62, the "initial state value" is used for the first time and the "transition destination state value" acquired immediately before is used for the second time and thereafter. Which one is used is selected and controlled by the multiplex 72 in the address generator 60.

Assuming that the number of PEs of the SIMD type microprocessor 2 is “k”, the memory and register file control circuit 52 is used to convert the data stored in (register 34 of) k PEs 3 into a table. The operation of reading the register 34 from the first PE 3 via the, performing table conversion, and writing to the register 34 is sequentially repeated k times. Moreover, it is sufficient to repeat this work k times, and it is not necessary to additionally perform other operations.

After all, for the table conversion of the second and subsequent PEs, it is not necessary to perform the calculation for obtaining the next "state", and therefore the conversion table is automatically changed dynamically.

Further, in the address generator 60 of FIG. 4, if the setting of the first selector 64 is changed, "s + n"
It is possible to change the bit width of the data to be taken out (that is, n of n bits) under the condition of ≦ w ”. Similarly, if the setting of the second selector 66 is changed, "s +
It is possible to change the bit width (that is, s of s bits) of the number of “states” to be taken out under the condition of “n ≦ w”. At that time, if the settings of the third selector 68 and the fourth selector 70 are adjusted, the converted data and the next transition destination state value can be appropriately acquired. That is, s and n
Can be set to any value as long as the following conditional expression is satisfied.

[Equation 1] n ≧ 0 s ≧ 0 s + n ≦ w

<< Second Embodiment >> FIG. 5 shows a detailed configuration of a table conversion unit 50 'according to a second embodiment of a SIMD microprocessor 2'according to the present invention. Since it is substantially the same as the table conversion unit 50 shown in FIG. 4, the same parts are denoted by the same reference numerals, the description thereof will be omitted, and different parts will be mainly described.

Further, the SIMD type microprocessor 2'of FIG. 6 has the table conversion unit 50 'of the second embodiment shown in FIG. 5 as a constituent element. The SIMD type microprocessor 2 ′ of FIG. 6 is different from the SIMD type microprocessor 2 shown in FIG. 2 in that each PE is connected via a memory and register file control circuit 52 ′.
A configuration is added in which any one bit in the condition register 53 of No. 3 is read.

The table conversion operation of the data (pre-conversion data) stored in the register 34 of each PE 3 in the table conversion unit 50 'of the second embodiment shown in FIG. 5 will be described. In the address generator 60 ′, the address pointer is set, and the “next transition destination state value” obtained from the table conversion immediately before that is fed back and set as the transition destination state value at that time. (Or whether an "initial value" is set) or a preset "set value" is set. This "next transition destination state value" or "setting value" is selected according to the condition flag in the first multiplex 72 ', that is, the setting content of 1 bit in the condition register 53 of each PE3. Is done. For example,
If the condition flag is set to "1", a preset "setting value" is set as the transition destination state value. This "set value"
The selection of means that the conversion table used is fixed. In other words, it means that hysteresis is not temporarily taken.

[0053]

By utilizing the present invention, the following effects can be obtained.

When the table conversion unit and the SIMD type microprocessor including the table conversion unit according to the first embodiment of the present invention are used, the table conversion processing for changing the table to be applied according to the hysteresis of the input value is realized. , It is not necessary to calculate the transition of the table to be applied by each PE or GP, and it is possible to realize it in the same number of cycles as the normal table conversion processing.

Further, the number of bits of the value fed back as the transition destination state value in the output data after table conversion can be made variable. Therefore, a more flexible state machine can be configured.

In the table conversion unit and the SIMD microprocessor including the table conversion unit according to the second embodiment of the present invention, not only the conversion table is dynamically selected by the hysteresis of the input value, but also the conversion table is fixed. The route to be selected is secured. Therefore, it is possible to mix the table conversion process corresponding to the hysteresis and the normal table conversion process for the fixed table that does not need to be dynamically changed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a SIMD type microprocessor according to the present invention.

FIG. 2 is a SIM as a preferred embodiment according to the present invention.
It is a block diagram which shows a detailed structure of a D-type microprocessor.

FIG. 3 shows a table memory configuration for realizing a table conversion process according to the present invention.

FIG. 4 shows a detailed configuration of a table conversion unit according to the first embodiment in a SIMD microprocessor according to the present invention.

FIG. 5 shows a detailed configuration of a table conversion unit according to a second embodiment in a SIMD microprocessor according to the present invention.

FIG. 6 is a preferred embodiment SIM according to the present invention.
FIG. 6 is a block diagram showing a detailed configuration of a D-type microprocessor, which has the table conversion unit of the second embodiment shown in FIG. 5 as a component.

[Explanation of symbols]

2, 2 '... SIMD type microprocessor, 3 ...
・ Processor element, 4 ... Global processor, 6 ... Register file, 8 ... Arithmetic array,
34 ... Registers, 50, 50 '... Table conversion unit, 52, 52' ... Memory and register file control circuit, 53 ... Condition register, 54 ... Table memory, 60, 60 '. ..Address generation unit, 62 ...
Table memory, 64 ... first selector, 66
.... Second selector, 68 ... Third selector, 70
... Fourth selector, 72, 72 '... First multiplex

Claims (4)

[Claims] 1. A processor comprising a plurality of processor elements, wherein a predetermined operation in the processor element, wherein output data for input data is prepared in advance by a predetermined table, is defined, and the plurality of processor elements are provided. In a SIMD microprocessor in which the above operations are continuously performed in a predetermined order, the input data is state data and pre-conversion data, and the output data is post-conversion data and next-state data. A table converter in which the next state data in the data becomes the state data of the input data in the operation on the next processor element performed successively. 2. The table converter according to claim 1, wherein the bit lengths of the state data and the next state data can be changed and set. 3. The state data of the input data is either the next state data of the output data, or a fixed set value, immediately before the operation on the processor element that is continuously performed. The table converter according to claim 1 or 2, wherein the presence or absence is determined by a condition flag included in each processor element. 4. A SIMD type microprocessor equipped with the table converter according to any one of claims 1 to 3, wherein a plurality of processor elements continuously perform the operation in a predetermined order.