JP2003067182A - Arithmetic unit and operation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high-speed processing by dispensing with floating-point operation to reduce the number of steps required for operation in operation including point number operation. SOLUTION: This arithmetic unit is provided with a multiplier 31a for performing multiplication in which one of two input values is a constant value of point number smaller than 1. The constant is expressed by a binary fixed- point number and a plurality of high order bits are consecutively zero. The multiplier 31a performs multiplication taking low order bits except the high order bits 0 in the constant as integer values. An adder 32a at the next step takes an output value of the multiplier 31a for bit number of the constant from the low order bits as a decimal part, and takes the high order bits except the decimal part in the output value of the multiplier 31a as an integer part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit and an arithmetic method used for an arithmetic operation when extracting a pixel of a designated color from a color image obtained by imaging an object in a production line or the like.

[0002]

2. Description of the Related Art Generally, in order to extract a pixel of a designated color from a color image, a technique for obtaining a color difference between the color of each pixel of the color image and the designated color is adopted. For example, Japanese Examination 7
In Japanese Patent Publication No. 92401, red (R) green (G) blue (B) tristimulus values obtained from a color image are converted into hue, saturation, lightness, hue angle, and hue length, and these five components are There is described a technique of determining a color within the range as the same color by setting a range for at least three components including a hue and a hue angle. In this publication, it is described that the L ^* a ^* b ^* color system can be adopted in order to express hue, saturation, and lightness.

However, when the color difference is obtained based on the L ^* a ^* b ^* color system, there is a slight deviation from the human sensation scale with respect to the human color. Therefore, in order to represent the color difference closer to the human sensation scale with respect to the human color, The present inventor previously used a color system in which tristimulus values of the XYZ color system are corrected, and the hue, lightness,
We proposed to obtain the color difference by obtaining the saturation (Japanese Patent Application 200
0-327738).

A configuration shown in FIG. 11, for example, is conceivable as a configuration for obtaining the color difference between each pixel of the color image and the designated color and extracting the pixels in the range that can be regarded as the same color as the designated color as described above. In the configuration shown in the figure, the color TV camera 11 captures an image of a spatial area including an object, and the color image captured by the color TV camera 11 is temporarily stored in the capture image memories 12R, 12G, and 12B for each RGB stimulus value. The image memories 12R, 12G for storing are stored.
By inputting a color image to the CPU 10 connected to the 12B via the bus B, the CPU 10 obtains the color difference from the designated color given from the input device 13.
The CPU 10 refers to the lookup table 14 connected via the bus B in order to speed up the calculation. That is, when converting the RGB tristimulus values into the colorimetric values of different color systems, by registering the correspondence relationship between the combination of the RGB tristimulus values and the colorimetric values in the lookup table 14, It is possible to convert the color system instantly. When the CPU 10 extracts the pixels of the specified color from the color image by calculating the color difference, the result is displayed in the image memory 1 for display.
5, and the contents of the display image memory 15 are displayed on a display device such as a CRT or a liquid crystal display.

[0005]

By the way, the CPU 10
Is an ALU 10a for integer and logical operations,
Equipped with an FPU 10b for floating point arithmetic,
The FPU 10b is used in the calculation of the number of decimal points required when obtaining the color difference. However, although the floating-point arithmetic has high arithmetic precision, it requires three kinds of arithmetic operations of a sign, a mantissa part, and an exponent part and a process of normalizing the result when compared with a fixed-point arithmetic which applies the integer arithmetic or the integer arithmetic. The number of steps required for arithmetic processing is significantly increased as compared with integer arithmetic and fixed-point arithmetic. For example, if the color image to be processed is a moving image of 640 × 480 pixels and full-motion processing (30 frames / s) is to be performed, the CPU 10 having an extremely high speed is required.

The present invention has been made in view of the above reasons, and an object thereof is to eliminate the need for floating point arithmetic in arithmetic including decimal point arithmetic such as arithmetic for extracting pixels of the same color as a designated color from a color image. An object of the present invention is to provide an arithmetic device and an arithmetic method that reduce the number of steps required for arithmetic operation and thereby realize high-speed arithmetic processing.

[0007]

According to a first aspect of the present invention, there is provided a multiplier for performing multiplication in which one of two input values is a constant value of a decimal point number smaller than 1, and the constant is a fixed binary number. When a plurality of high-order bits are represented by a decimal point and are consecutively 0, the lower bits of the constant except for the high-order bits that are 0 are regarded as integer values, and multiplication by a multiplier is performed. The number of bits of the constant from the lower bit of the output value of the multiplier is set as the decimal part, and the upper bit of the output value of the multiplier excluding the decimal part is passed as the integer part to the next process.

According to a second aspect of the invention, in the first aspect of the invention, a first number which is an integer value obtained from the pixel values of the image,
An arithmetic unit for obtaining a value used for comparison with a second number which is an integer value given as a designated value, the first arithmetic unit having a square of a difference between the first number and the second number as an arithmetic result. A second arithmetic unit that obtains an arithmetic result of an arithmetic operation including multiplication of a constant value of a decimal point number smaller than 1 by the multiplier and a first number;
And a divider that divides the calculation result of the calculation unit by the calculation result of the second calculation unit.

According to a third aspect of the present invention, in the second aspect of the present invention, the arithmetic result of the second arithmetic unit is a fixed point number, and the integer part of the arithmetic result of the second arithmetic unit in the divider. It is characterized by using only.

According to a fourth aspect of the present invention, in the second or third aspect of the invention, the dividing means for dividing the two input values of the divider by the power of 2 is used as the first arithmetic unit and the second arithmetic unit. It is characterized in that it is provided between the arithmetic unit and the divider.

A fifth aspect of the present invention is an arithmetic device for obtaining a value used for comparison between a first number, which is an integer value obtained from pixel values of an image, and a second number, which is an integer value given as a designated value. Of the calculation result of the calculation including the multiplication of the first number by the constant value of the decimal point number smaller than 1 and the first calculation unit that calculates the square of the difference between the first number and the second number. A lookup table in which a value corresponding to the reciprocal number is associated with the first number;
A multiplier for multiplying the calculation result of the first calculation unit by a value extracted from the lookup table as a value corresponding to the number.

The invention of claim 6 is characterized in that, in the inventions of claims 2 to 4, at least a pipeline register is inserted in the division process by the divider to perform pipeline processing.

The invention of claim 7 is characterized in that, in the invention of claims 1 to 6, it is constituted by an FPGA.

According to the eighth aspect of the present invention, when performing multiplication in which one of the two input values is a constant value of a decimal number smaller than 1, the constant is represented by a binary fixed point number and a plurality of constant values are expressed. When the upper bits are 0 in succession,
Of the constants, the lower bits excluding the upper bits, which are 0, are regarded as integer values, and multiplication is performed. From the lower bits of the multiplication result, the number of bits of the constant is set as a decimal part, and the decimal part of the multiplication result is excluded. It is characterized in that the upper bits are passed to the next process as an integer part.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) In the present embodiment, in comparison with the configuration shown in FIG. By using the calculation, the number of steps for calculating the color difference is reduced. Further, in the configuration shown in FIG. 11, the CPU 10, the capture image memories 12R, 12G, 12B, the look-up table 14, and the display image memory 15 share the bus B, so that the capture image memory 12R is used. , 12G, 12
The process of reading the image data from B, the process of collating the image data with the look-up table 14, the process of executing the calculation, and the process of writing the calculation result to the display image memory 15 are sequentially performed. Image memory 12
The image data from R, 12G, and 12B cannot be read at the same time, and the calculation result cannot be written to the display image memory 15, and the bus B becomes a bottleneck. , Image memory for capture 12R,
It is possible to take in the image data from 12G and 12B and write the calculation result to the display image memory 15 at the same time.

That is, as shown in FIG. 2, the capture image memories 12R, 12G, 12B, the look-up table 14, and the display image memory 15 are connected to different parts of the CPU 10, and the CPU 10 converts the color system. And a main calculation unit 10 for performing a calculation for obtaining a color difference in the converted color system.
d and are provided. With this configuration, the sub-calculation unit 10c can simultaneously capture the image data from the capture image memories 12R, 12G, and 12B and write the calculation result to the lookup table 14 by the main calculation unit 10d. Further, rather than using the FPU 10b for performing the floating point operation in the color difference calculation, by performing the fixed point operation, the decimal point operation is performed in the same procedure as the integer operation, and as a result, the floating point operation is performed. Also, the circuit scale is reduced by omitting the FPU 10b for performing the floating-point calculation.

In this embodiment, the capturing image memory 12 is used.
By giving the lookup table 14 the calculation result of the sub-calculation unit 10c for the pixel values (that is, tristimulus values RGB) of the color image input from R, 12G, and 12B, the CIELAB color space (L ^* a ^* b ^The values Lm, am, bm corresponding to L ^* a ^* b ^* in the ^{( *} color space) and the saturation Sm are calculated from the look-up table 14 to the main calculation unit 10d.
It is configured to input to.

FIG. 3 shows the configuration of the main arithmetic unit 10d. As described above, the values Lm, am, bm, and Sm related to the color image are input to the main calculation unit 10d, so the main calculation unit 1
With respect to 0d, the values Li, ai, bi, and Si corresponding to the designated color are input from the input device 13. Main operation unit 10d
Then, these values Lm, am, bm, Sm, Li, a
A color difference is obtained based on i, bi, and Si in the form of the following equation. Color difference = {(ΔH / TH) ² + (ΔS / TS) ² + (Δ
L) ² } ^1/2 where ΔH ² = Δa ² + Δb ² −ΔS ² ΔS = Sm-Si ΔL = Lm-Li Δa = am-ai Δb = bm-bi TH = 1 + 0.015 × Si TS = 1 + 0. 045 × Si where the values Lm, am, bm, Sm, Li, a
i, bi, and Si are all integers, but the values TH and TS
Is a decimal point number, a decimal point operation is required to calculate the color difference.

In the configuration shown in FIG. 3, the values Lm and Li are 9-bit unsigned integers, and the values am, bm, Sm, ai, and
For bi and Si, a 10-bit unsigned integer is used. A set of values am and ai, a set of values bm and bi,
The set of values Sm and Si and the set of values Lm and Li are input to subtractors 21a, 22a, 23a and 24a, respectively, and Δa (=
am-ai), Δb (= bm-bi), ΔS (= Sm-
Si) and ΔL (= Lm-Li) are obtained respectively.
The outputs of the subtractors 21a, 22a, 23a, and 24a are input to the multipliers 21b, 22b, 23b, and 24b, respectively, and squared values Δa ² , Δb ² , ΔS ² , and ΔL ²
Is required. The value Si is below two point unit 25a, is input to 25b, the value TH, with TS are obtained, respectively, each value TH, the value TH ^2, TS ² of the squared TS obtained. Multipliers 21b, 22b,
The output of 23b is input to the adder / subtractor 25c, and the value ΔH ²
(= Δa ² + Δb ² −ΔS ² ) is obtained. The output value ΔH ² of the adder / subtractor 25c and the output value ΔS ² of the multiplier 23b are input to the dividers 26a and 26b, respectively, and are divided by the output values TH ² and TS ² of the decimal point arithmetic units 25a and 25b, respectively. That is, the output value of the divider 26a is (Δ
H / TH) ² , and the output value of the divider 26b is (ΔS /
TS) ² . Outputs of both dividers 26a and 26b (ΔH
/ TH) ² , (ΔS / TS) ² is the output Δ of the multiplier 24b.
The color difference in the above equation is obtained by inputting the output of the adder 27a together with L ² to the square root calculating unit 27b. The output value of the square root calculation unit 27b is input to the normalization unit 27c and normalized, and the normalization unit 27c
The output value of c becomes the output of the main calculation unit 10d. That is,
The value ai, bi or the value Si corresponds to the first number, and the value a
The m, bm or the value Sm corresponds to the second number. Further, the subtractors 22a and 23a, the multipliers 22b and 23b, and the adder / subtractor 25c, or the subtractor 24a and the multiplier 24b constitute a first arithmetic unit. Furthermore, the decimal point calculation unit 25
a and 25b function as a second computing unit.

By the way, one of the features of the present invention is that fixed-point arithmetic is performed in obtaining the above-mentioned values TH ² and TS ² . Below, each value TH in the present embodiment
² and TS ² calculation technology will be described.

First, the calculation for obtaining the value TH ² will be described. The value TH is (1 + 0.015 × S
In the present invention, since the fixed point arithmetic is applied to the arithmetic of the decimal point in the present invention, the arithmetic of the decimal point can be performed in the same procedure as that of the integer arithmetic, which enables high speed arithmetic. 0.015 which is the coefficient of Si
Must use fixed-point notation. However, the coefficient 0.015 of the value Si cannot be accurately represented by a binary fixed point representation. That is, using the fixed-point representation, as shown in Table 1, even if the bit width below the decimal point is increased, it is not possible to exactly match 0.015. In Table 1, the decimal notation is 0.0
Regarding the binary notation so that it does not exceed 15,
The relationship between the bit width below the decimal point of a binary number, the binary number notation, and the decimal number notation is shown.

[0022]

[Table 1]

According to Table 1, 0.015 in decimal notation
For <d> (below, when <b> is added to the numerical value, it means binary notation, and when <d> is added, it means decimal notation), for example, the error is within 1%. If the binary number notation is selected for, it will be understood that the binary number notation requires only 12 bits of data after the decimal point.
On the other hand, an error of about 1% in the calculation for obtaining the color difference does not pose a problem in practical use, so the value Si when the value TH is obtained is
0.000000011101 <b> will be adopted as the binary notation corresponding to the coefficient of 0.015 <d>.

A configuration shown in FIG. 4 is conceivable as a configuration for obtaining the value TH ² . The value Si is a 10-bit unsigned integer, and as described above, the coefficient of the value Si is a 12-bit unsigned decimal point number expressed in fixed point representation. In FIG. 4, the numerical values are represented by rectangles, and the dots added below the rectangles indicate the positions of decimal points. Also, the numerical value above the rectangle indicates the bit width of the value. Both values are multiplier 3
0.015 × S by being input to 1a and being multiplied
A value corresponding to i is obtained. This value is 22 bits. Next, 1 is added to the output value of the multiplier 31a. Here, in the binary notation of the value 0.015 <d>, it is represented by 12 bits after the decimal point, so that 12 bits after the decimal point is added to 1 as 13 bits. The output value of the multiplier 31a and 1 represented by 13 bits are added by the adder 32a to obtain the value TH, and further squared by the multiplier 33a to obtain the value TH ² . If the value in binary notation is squared, the integer part and the fractional part each have a bit width twice the input value. Therefore, the value TH ² obtained in the above process has an integer part of 20 bits and a decimal part of 24. Thus, an output value having a bit width of 44 bits is obtained. By the way, the value TH ² is calculated by the divider 26a as described above.
If 44-bit data is input to the divider 25a, the scale of the divider 26a becomes large, which hinders high-speed operation.

Therefore, in order to reduce the number of bits input to the divider 26a, the configuration shown in FIG. 1 is adopted. In the configuration shown in FIG. 1, the value TH ^{2 as} the operation result and the bit width of each value in the operation process are reduced. By adopting this configuration, the circuit scale of the main operation unit 10d is reduced and the operation processing is performed. It becomes possible to speed up.

That is, in the configuration shown in FIG.
0.000000011, which is the binary notation of 015 <d>
In 1101 <b>, the upper 6 digits of the decimal part are all 0
Paying attention to this point, a configuration is adopted in which substantial calculation is performed only on 6 bits from the 7th digit to the 12th digit after the decimal point. Therefore, the coefficient is first treated as if the decimal point of the coefficient is moved to the right end by performing a 12-bit left shift, and only the lower 6 bits are input to the multiplier 31a.
A 10-bit value Si is input to the multiplier 31a together with a 6-bit coefficient, and a 16-bit value is output. The output value of the multiplier 31a is treated as a value obtained by shifting one input value to the left by 12 bits and is a value obtained by multiplying the true value by 4096. Therefore, the output value of the multiplier 31a is set to obtain the true value. Thereafter, the subsequent processing is performed in the form of performing a 12-bit right shift. That is, the upper 4 bits of the output of the multiplier 31a are used as the integer part, and the lower 12 bits are treated as the decimal part. As described above, in the configuration shown in FIG.
Since the number of bits of the operation result in 1a is reduced by 6 bits, it becomes possible to use a small scale multiplier 31a. Further, as described above, the left shift and the right shift do not actually perform the shift operation, but only handle the input / output value of the multiplier 31a as the value obtained by the shift operation, and thus the shift operation unit is not necessary. As described above, when the coefficient is expressed in binary notation and there are consecutive 0s from the decimal point, it is possible to reduce the bit width of the value used in the calculation by handling the coefficient in a bit-shifted form. As a result, the scale of the main arithmetic unit 10d can be reduced and the arithmetic speed can be improved.

The output of the multiplier 31a is input to the adder 32a and added with 1, similarly to the configuration shown in FIG. 4, and further input to the multiplier 33a to be squared. In the configuration shown in FIG. 1, the multiplier 33a performs 16-bit multiplication, and since the integer part of the input value to the multiplier 33a is 4 bits and the decimal part is 12 bits, the output value of the multiplier 33a is an integer. 8 bits for the part and 24 bits for the decimal part, for a total of 32
It becomes the output value of the bit. This means that the number of bits handled by the multiplier 33a is reduced as compared with the configuration shown in FIG. 4, but in order to further reduce the number of bits, only the upper 8 bits of the decimal part are used for the subsequent processing. Is used, and the value TH ² is given to the divider 26a in 16 bits. Here, since the influence on the calculation of the color difference is relatively small even if the lower 8 bits of the decimal part are ignored, the divider 26a
By making the number of significant digits given to 16 bits, the scale of the main arithmetic unit 10d is reduced and the processing speed is increased.

The calculation of the value TS ² differs from the calculation of the value TH ² only in the coefficient value of the value Si.
A configuration similar to that shown in FIG. 1 can be employed as shown in FIG. However, the value in binary notation corresponding to the coefficient 0.045 <d> is 0.
0000111111 <b> was adopted. This value is 10
In decimal notation, it is 0.044921875 <d>. That is, since the coefficient is 9 bits and the upper 4 bits below the decimal point are 0, the lower 5 bits below the decimal point are used as valid values. That is, the 10-bit value Si and the lower 5 bits of the coefficient are input to the multiplier 31b that multiplies the value Si by the coefficient, and a 15-bit output value is obtained from the multiplier 31b. Since the output value of the multiplier 31b is handled by shifting it by 9 bits to the left, the lower 9 bits are treated as a decimal part and the upper 6 bits are treated as an integer part.

The output of the multiplier 31b is added with 1 in the adder 32b to obtain the value TS, and the value TS is further obtained.
Is input to the multiplier 33b and squared. Multiplier 33b
Since the output is a 30-bit value in which the upper 12 bits are the integer part and the lower 18 bits are the decimal part, the lower 16 bits are ignored and the upper 16 bits are set in order to match the bit width with value TH.
Only use bits. In other words, the upper 1 of 16 bits
2 bits become the integer part and the remaining 4 bits become the decimal part.

Therefore, in the main arithmetic unit 10d shown in FIG. 2, the configuration shown in FIG. 5 is used as the decimal point arithmetic unit 25b for obtaining the value TS ^2, and the term (ΔS / TS) ² relating to the saturation in the color difference formula is used. When the portion for performing the calculation of is extracted, it becomes as shown in FIG. The values Si and Sm, which are unsigned integers of 10 bits, are input to the subtractor 23a, and 1 is obtained by subtraction.
A 1-bit signed integer is output. In the multiplier 23b, the output value of the subtractor 23a is squared, and this output is 22 bits, but the upper 1 bit is a sign bit and the squared value does not require a sign. Handles 21 bits. However, as described above, since the lower 4 bits of the 16-bit output value of the decimal arithmetic unit 25b are the decimal part, the 22-bit positive value output from the multiplier 23b is also a decimal part for digit alignment. 4 bits are added as. That is, a value of 25 bits (= 22 bits-1 bit + 4 bits) is input from the multiplier 23b to the divider 26b, and a 16-bit value is input from the decimal point calculator 25b to the divider 26b. Therefore, the divider 2
The output of 6b becomes 25 bits.

By the way, as is apparent from the configuration shown in FIG. 6, in the main arithmetic unit 10d, the dividers 26a and 2a are divided.
In 6b, 25-bit data is handled, and the number of bits handled is larger than in other configurations. That is,
The dividers 26a and 26b are the largest in terms of circuit scale, and the processing time required for division is longer than other processing. Therefore, in order to reduce the number of bits handled by the dividers 26a and 26b, the decimal part of the output value of the decimal point calculator 25b is ignored, and the input values to the dividers 26a and 26b are integer values. It is possible to reduce the circuit scale and processing time of 26a and 26b. An example of adopting this configuration is shown in FIG. In the configuration example shown in FIG. 7, the divider 26b treats the output value of the decimal point operation unit 25b as 12 bits by adopting only the upper 12 bits of the output value of the decimal point operation unit 25b and ignoring the fractional part. ing. Since it is not necessary to add the decimal part to the output value of the multiplier 23b by ignoring the decimal part of the decimal point operation part 25b in this way, the multiplier 23b to the divider 26b
The input value to is 21 bits excluding the upper 1 bit. As a result, the output value of the divider 26b also becomes 21 bits, the number of bits is further reduced as compared with the configuration example shown in FIG. 6, the circuit scale of the divider 26b is reduced as compared with the configuration of FIG. The time required for is also reduced.

In order to further reduce the circuit scale of the dividers 26a and 26b, it is possible to employ a technique of previously dividing the two values respectively inputted to the dividers 26a and 26b by the same value. For example, as shown in FIG. 8, if the two values input to the divider 26b are each divided by 2 and then input to the divider 26b, the value handled by the divider 26b is reduced by one bit, and the divider 26b Output value of 20
Can be a bit. The value to be divided does not necessarily have to be 2, but division by a power of 2 makes it possible to reduce the number of bits in 1-bit units. For example, dividing by 4 reduces 2 bits, and dividing by 8 reduces 3 bits.

The divider 26 is adopted by using the above-mentioned method.
If the number of bits of the input values to a and 26b is reduced, the calculation accuracy may decrease, but the calculation result in the main calculation unit 10d when the configuration shown in FIG. There is only a comparatively small error compared with the calculation result when the calculation is performed, and such an error does not cause a practical problem in the calculation for obtaining the color difference. By the way, the color difference obtained by the main calculation unit 10d is 0
If it changes in the range of about 260, the operation result adopting the configuration shown in FIG. 8 has an error of about 1 to 2 as compared with the case of performing the floating point operation, and the error is of a level that is practically acceptable. Met.

(Second Embodiment) In the first embodiment, a configuration in which the dividers 26a and 26b are used to obtain the color difference is adopted, but in the present embodiment, as shown in FIG. , A multiplier 26 is used instead of the dividers 26a and 26b,
A configuration is adopted in which the output value of the multiplier 23b is multiplied by the reciprocal of the values TH ² and TS ² that are divisors.

In this configuration, the main calculation unit 10d has the value TH.
^2, without operation of the TS ^2, it is necessary to obtain the inverse of these values TH ^2, TS ² outside the main operation portion 10d. However, the values TH ² and TS ² are operations for multiplying and adding a constant to the value Si and are values uniquely determined for the value Si. The values TH ² and TS ² can be calculated in advance, and if the value Si is associated with the reciprocal of the values TH ² and TS ² and stored in the lookup table 14,
This is a process of reading the corresponding value from the lookup table 14 without performing a special calculation.

If the above-mentioned configuration is adopted, the divider 26
a and 26b are no longer necessary, and the multiplier 26 is a divider 26a,
Since the circuit configuration is simple as compared with 26b, it is possible to reduce the circuit scale of the main calculation unit 10d as a result. Further, by providing the look-up table 14, the calculation for obtaining the values TH ² and TS ² from the value Si becomes unnecessary, so that the look-up table 14 becomes relatively large in scale, but a part of the calculation processing becomes unnecessary. As a result, the processing speed is increased. Other configurations and operations are similar to those of the first embodiment.

(Third Embodiment) In the above-described embodiment, the explanation has been made on the assumption that the arithmetic operation of the main arithmetic unit 10d is completed within a necessary time. There is a possibility that it will not be in time. Therefore, this kind of problem can be avoided by dividing the main arithmetic unit 10d into a plurality of blocks and pipelining them so that the required throughput can be realized.

For example, in the configuration in which the dividers 26a and 26b are provided, there is a case in which the operation time allowed for executing only the division is almost spent, and the division accounts for a large proportion of the entire operation time. . In such a case, as shown in FIG. 10, the main operation unit 10d shown in FIG. 2 is divided into three blocks of division, operation before division, and operation after division, and each block is divided into three blocks. A desired arithmetic speed can be achieved by inserting the pipeline register 28 and adopting a three-stage pipeline configuration. Note that the number of divisions and division positions for forming a pipeline configuration are not limited to the configuration of FIG. 10. For example, when the operation time required for division is too long, a divider with a pipeline configuration is used. It is also possible to adopt the configuration used. Other configurations and operations are the same as those of the first embodiment, and it is possible to adopt the same configuration as that of the second embodiment also in this configuration.

The above-mentioned various configurations may be adopted as needed. For example, FPGA (Field Programmable)
If the main operation unit 10d is configured by using Gate Allay), the function can be changed as necessary even after the main operation unit 10d is mounted, and the various configurations described above can be appropriately adopted. It becomes possible to change the function of the main arithmetic unit 10d so that.

[0040]

According to the invention of claim 1, one of the two input values is provided with a multiplier for performing multiplication, which is a constant value of a decimal point number smaller than 1, and the constant is represented by a binary fixed point number. When a plurality of high-order bits are continuously 0, the low-order bits other than the high-order bit that is 0 in the constant are regarded as an integer value for multiplication by the multiplier, and the output value of the multiplier The number of bits of the constant from the lower bits of the above is set as the decimal part, and the upper bits of the output value of the multiplier excluding the decimal part are passed to the next process as the integer part, and the multiplication of the decimal point number is performed in the multiplier. Nevertheless, floating-point arithmetic is unnecessary, and high-speed arithmetic processing is possible with a small circuit configuration.

According to a second aspect of the invention, in the first aspect of the invention, a first number which is an integer value obtained from the pixel values of the image,
An arithmetic unit for obtaining a value used for comparison with a second number which is an integer value given as a designated value, the first arithmetic unit having a square of a difference between the first number and the second number as an arithmetic result. A second arithmetic unit that obtains an arithmetic result of an arithmetic operation including multiplication of a constant value of a decimal point number smaller than 1 by the multiplier and a first number;
And a divider that divides the calculation result of the calculation unit of the second calculation unit by the calculation result of the second calculation unit. Since it is not necessary to perform floating point calculation, the circuit scale can be reduced and Since a complicated procedure is not required as compared with the decimal point calculation, the processing time can be shortened.

According to a third aspect of the present invention, in the second aspect of the present invention, the arithmetic result of the second arithmetic unit is a fixed-point number, and the integer part of the arithmetic result of the second arithmetic unit in the divider. Since only the decimal point number is used as the input value of the divider, it is possible to reduce the circuit scale.
Moreover, since no complicated calculation is required, the calculation speed is also improved. That is, it is possible to reduce the circuit scale and the calculation time by lowering the calculation accuracy as long as the accuracy of the final calculation result is within a practically acceptable range.

According to a fourth aspect of the present invention, in the second or third aspect of the invention, the dividing means for dividing the two input values of the divider by the power of 2 is used as the first arithmetic unit and the second arithmetic unit. The number of digits of the input value to the divider can be reduced because it is provided between the arithmetic unit and the divider.
As a result, the circuit scale can be reduced.

The invention of claim 5 is an arithmetic device for obtaining a value used for comparison between a first number which is an integer value obtained from pixel values of an image and a second number which is an integer value given as a designated value. Of the calculation result of the calculation including the multiplication of the first number by the constant value of the decimal point number smaller than 1 and the first calculation unit that calculates the square of the difference between the first number and the second number. A lookup table in which a value corresponding to the reciprocal number is associated with the first number;
And a multiplier that multiplies the calculation result of the first calculation unit by the value extracted from the look-up table as a value corresponding to the number. High-speed processing can be expected because an operation for one number is unnecessary.

According to a sixth aspect of the invention, in the second to fourth aspects of the invention, at least the pipeline register is inserted in the division process by the divider to perform pipeline processing, so that a desired operation time is achieved. Only the effective calculation speed can be increased.

Since the invention of claim 7 is the same as the invention of claims 1 to 6 and is constituted by an FPGA, the specification can be easily changed.

According to the eighth aspect of the present invention, when one of the two input values is a constant value of a decimal point number smaller than 1, the constant is represented by a binary fixed point number and a plurality of constant values are expressed. When the upper bits are 0 in succession,
Of the constants, the lower bits excluding the upper bits, which are 0, are regarded as integer values, and multiplication is performed. From the lower bits of the multiplication result, the number of bits of the constant is set as a decimal part, and the decimal part of the multiplication result is excluded. It is characterized in that the high-order bits are passed to the next process as an integer part. Floating-point arithmetic is not required even though the decimal point is multiplied, and high-speed arithmetic processing is possible with a small-scale circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a main arithmetic unit used in a first embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of the above.

FIG. 3 is a block diagram showing a main calculation unit used in the above.

FIG. 4 is a block diagram of a main part of a main calculation unit used in a comparative example.

FIG. 5 is a block diagram of a main part of a main arithmetic unit used in the first embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the above.

FIG. 7 is an operation explanatory diagram of the above.

FIG. 8 is an operation explanatory diagram of the above.

FIG. 9 is a principal block diagram showing a second embodiment of the present invention.

FIG. 10 is a block diagram showing a third embodiment of the present invention.

FIG. 11 is a block diagram showing a conventional example.

[Explanation of symbols]

21a, 22a, 23a, 24a Subtractor 21b, 22b, 23b, 24b Multiplier 25c adder / subtractor 26a, 26b divider 31a multiplier 31b multiplier

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Claims (8)

[Claims] 1. A multiplier for performing multiplication, wherein one of two input values is a constant value of a decimal point number smaller than 1, wherein the constant is represented by a binary fixed point number, and a plurality of upper bits are provided. Is consecutively 0, the lower bits of the constant except for the upper bits that are 0 are regarded as integer values, and multiplication is performed by the multiplier. An arithmetic unit, wherein the number of bits is a fractional part, and the upper bits of the output value of the multiplier excluding the fractional part are passed to the next process as an integer part. 2. An arithmetic unit for calculating a value used for comparison between a first number, which is an integer value obtained from pixel values of an image, and a second number, which is an integer value given as a designated value, which is a first number. And a second number as a calculation result, and a calculation result including a multiplication of a constant value of a decimal point number smaller than 1 by the multiplier and the first number. The arithmetic unit according to claim 1, further comprising a second arithmetic unit and a divider that divides the arithmetic result of the first arithmetic unit by the arithmetic result of the second arithmetic unit. 3. The calculation result of the second calculation unit is a fixed point number, and the divider uses only the integer part of the calculation result of the second calculation unit. Computing device. 4. The two input values of the divider are respectively 2
4. The arithmetic unit according to claim 2 or 3, characterized in that division means for dividing by the power of is provided between the first arithmetic unit and the second arithmetic unit and the divider, respectively. 5. An arithmetic unit for calculating a value used for comparing a first number, which is an integer value obtained from pixel values of an image, with a second number, which is an integer value given as a designated value, and which is a first number. And a value corresponding to the reciprocal of the calculation result of the calculation including the multiplication of the first number and the constant value of the decimal point number smaller than 1 And a multiplier that multiplies the calculation result of the first calculation unit by the value extracted from the lookup table as the value corresponding to the first number. Arithmetic unit. 6. The arithmetic unit according to claim 2, wherein a pipeline register is inserted at least in the division process by the divider to perform pipeline processing. 7. The arithmetic unit according to claim 1, wherein the arithmetic unit comprises an FPGA. 8. When performing multiplication in which one of two input values is a constant value of a decimal point number smaller than 1, the constant is represented by a binary fixed point number and a plurality of high-order bits are consecutive. Is 0, among the above constants,
The lower bits other than the upper bits are regarded as integer values and the multiplication is performed. From the lower bits of the multiplication result, the number of bits of the constant is set as the decimal part, and the upper bits of the multiplication result excluding the decimal part are the integer parts. The calculation method is characterized in that it is handed over to the next process as.