JP2003060611A - Digital broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital broadcast receiver that can perform demapping processing at an OFDM demodulation section by a simple configuration at a high speed. SOLUTION: When I and Q data that are subjected to A/D conversion, FFT, frequency deinterleave, and time deinterleave from a tuner are mapped, different processing is made depending on whether a coordinate point on an IQ plane of an input signal exists near an axis or not. When the coordinate point does not exist near the axis, the coordinate point is projected to a first quadrant of the IQ plane for processing. Contrarily, when the coordinate point exists near the axis, the coordinate point is projected to the positive region of I and Q axes for processing. For example, in the case of 64 QAM, the symmetry properties of constellation are utilized, and the size of a demapping circuit is reduced even if soft judgement for expressing the accuracy of each bit of six bits corresponding to 64 points by three bits is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiving apparatus, and more specifically, to orthogonal frequency division multiplexing (OFDM).
x) The present invention relates to a terrestrial digital broadcast receiving device that receives a signal modulated by a transmission method.

[0002]

2. Description of the Related Art In recent years, in a system for transmitting a video signal or an audio signal, an OFDM system has been proposed as a system excellent in high quality transmission and improvement in frequency utilization efficiency. The OFDM system is a system for multiplexing and transmitting modulated waves of a large number of subcarriers (hereinafter referred to as subcarriers) within a band of one channel. For example, after converting an analog TV signal into a digital signal, MPEG (Moving Pictu)
re Experts Group) data compression. Byte interleaving and bit interleaving are performed to disperse the cause of error occurrence in the transmission line such as noise in this data signal, and QPSK (quadrature phase modulation
Mapping according to a modulation method such as ture phase shift keying) or 16QAM (quadrature amplitude modulation).

The mapped data is subjected to time interleaving and frequency interleaving to disperse the cause of error occurrence in the transmission path such as fading, and then subjected to inverse Fourier transform (IFFT) and orthogonally modulated, and then frequency-converted to an RF frequency. It is converted and transmitted.

On the receiving side, the operation is completely reversed after the transmission. First, the RF input signal input from the antenna is
Input to the tuner. In the tuner, the input signal is down-converted into a baseband signal and input to the OFDM demodulation circuit.

In the OFDM demodulation circuit, an input signal is first converted from analog to digital and converted into a digital signal, and then converted into an in-phase detection axis signal (hereinafter referred to as I signal) and a quadrature detection axis signal (hereinafter referred to as Q signal). To be done. Then, the I signal and the Q signal are demapped.

Demapping will be briefly described. Demapping refers to associating an I signal and a Q signal which are orthogonal to each other with one of a predetermined number of signal points of the constellation and associating them.

FIG. 15 is a diagram for explaining simple demapping of 64QAM. Referring to FIG. 15, the I signal and the Q signal each take a value in the range of -8 to +8. When the I signal and the Q signal are digitally converted by the A / D converter, they each become a 10-bit digital signal. The I signal and the Q signal are plotted on a plane whose axes are the I axis and the Q axis, respectively, and the closest signal point among the 64 signal points is obtained. The 6-bit value corresponding to the obtained signal point is the result of demapping.

The 6-bit values respectively assigned to the 64 points are (b0, b1, b2, b3, b4,
b5).

The I signal is reflected in bits b0, b2 and b4. The Q signal is reflected in bits b1, b3 and b5.
Gray code is used to reduce the error at the boundary between adjacent areas. Gray code,
Two consecutive numbers are represented so that only one bit is different to reduce errors.

As shown in the left and lower parts of FIG. 15, in the Gray code, 7 is (0, 0, 0) and 5 is (0, 0,
0, 1), 3 correspond to (0, 1, 1), 1 corresponds to (0, 1, 0), respectively. -1 is (1,1,0), -3 is (1,1,1), -5 is (1,0,1), and -7 is (1,1).
0, 0) respectively. For example, if the I signal is +7
When the Q signal is +7, the obtained data is (00
0000). When the I signal is +7 and the Q signal is +5, the obtained data is (000001).

FIG. 16 is a block diagram showing a configuration of a circuit for performing conventional demapping processing.

Referring to FIG. 16, a circuit for demapping receives an I signal and a Q signal and receives 6-bit data b0.
A 64QAM demapping unit 502 that outputs ~ b5,
And a parallel-serial conversion circuit 504 that receives data b0 to b5 input in parallel and outputs the data serially.

When such a simple demapping process is performed, if there is a circuit for performing the demapping process in the first quadrant, the symmetry of the arrangement of signal points in FIG. Demapping in the third, fourth quadrant can also be performed.

FIG. 17 is a block diagram showing the configuration of the 64QAM demapping section 502 in FIG.

Referring to FIG. 17, the 64QAM demapping unit 502 receives the I signal and the Q signal from the time deinterleaving unit and determines which quadrant of the IQ plane the coordinate point is located in. And a coordinate projection unit 514 that receives the output of the quadrant determination unit 512 and projects the coordinates onto the corresponding coordinates in the first quadrant, and a demapping processing unit that demaps the coordinate points projected by the coordinate projection unit 514 into the first quadrant. 516, and a data conversion unit 518 that receives the output of the demapping processing unit 516 and converts it into the original quadrant demapping data. The data conversion unit 518 uses the I signal and the Q signal.
6-bit data b0, b1, b2, b corresponding to the signal
3, b4 and b5 are output in parallel.

Since the demapping processing unit 516 only needs to handle the first quadrant of FIG. 15, that is, the range of the I signal of 0 to +7 and the Q signal of 0 to +7, it performs the processing of the first to fourth quadrants. It is possible to handle a smaller number of bits than a circuit. For example, since the I signal and the Q signal may each have a range of ½, the demapping processing unit 516 may be used when the I signal and the Q signal are converted into digital signals of 10 bits each.
Would need to process the I signal and the Q signal for each 9 bits. This is effective in reducing the circuit scale.

FIG. 18 is a flowchart showing the processing of the 64QAM demapping unit 502 in FIG.

Referring to FIG. 18, first, step S101.
At, it is determined whether the I signal is 0 or more. I
If the signal is 0 or more, the process proceeds to step S102. On the other hand, if the I signal is not 0 or more, the process proceeds to step S103.

In steps S102 and S103, it is determined whether the Q signal is 0 or more. Step S102
If it is determined that the Q signal is 0 or more in,
Since the coordinate points of the input I signal and Q signal on the IQ plane are in the first quadrant, the process directly proceeds to step S107.

When it is determined in step S102 that the Q signal is not 0 or more, the coordinate point on the plane of the input signal is in the fourth quadrant. Then, the process proceeds to step S104, and after the absolute value of the Q signal is obtained in order to project the negative Q signal into the first quadrant, the process proceeds to step S107.

When it is determined in step S103 that the Q signal is 0 or more, the coordinate point is in the second quadrant. Then, the process proceeds to step S105, and the negative I signal is subjected to absolute value processing and projected to the first quadrant, and then step S1.
Proceed to 07.

If it is determined in step S103 that the Q signal is not 0 or more, there are coordinate points in the third quadrant in which both the I signal and the Q signal are negative. And step S
Proceeding to 106, the absolute value of the I signal and the absolute value of the Q signal are obtained, and then the processing proceeds to step S107.

In step S107, demapping in the first quadrant is performed based on the processing flow described later,
6-bit demapping data in the first quadrant (b
0, b1, b2, b3, b4, b5) are obtained. When it is determined that the coordinate point is in the first quadrant, the obtained demapping data is output as it is in step S111.

On the other hand, when it is determined that the coordinate point is in the fourth quadrant, the bit b1 is inverted in the obtained demapping data and the result is output in step S111.

If it is determined that the coordinate point is in the second quadrant, in step S109, step S10.
The bit b0 of the demapping data obtained in 7 is inverted, and the result is output in step S111.

If it is determined that the coordinate point is in the third quadrant, in step S110, step S10.
Both the bits b0 and b1 of the demapping data obtained in step 7 are inverted, and the result is step S111.
Is output with.

FIG. 19 shows a step S10 in FIG.
7 is a flowchart showing details of demapping processing in the first quadrant of FIG.

Referring to FIG. 19, since data is projected in the first quadrant, bit b in step S121.
Both 0 and b1 are set to 0.

Then, in steps S122 to S128, the values of the bits b2 and b4 corresponding to the I signal are obtained. Then, in steps S129 to S135, the values of the bits b3 and b5 corresponding to the Q signal are obtained.

First, in step S122, it is determined whether the I signal is 6 or more. When it is determined that the number is 6 or more, the process proceeds to step S123, and bit b2,
Both bits b4 are set to 0.

If it is determined in step S122 that the I signal is not 6 or more, the process proceeds to step S124.
In step S124, it is determined whether the I signal is 4 or more.

If it is determined in step S124 that the I signal is 4 or more, the flow advances to step S125 to set bit b2 to 0 and bit b4 to 1. On the other hand, if it is determined in step S124 that the I signal is not 4 or more, the process proceeds to step S126. In step S126, it is determined whether the I signal is 2 or more.

If it is determined in step S126 that the I signal is 2 or more, the process proceeds to step S127, in which both bits b2 and b4 are set to 1. On the other hand, if it is determined in step S126 that the I signal is not 2 or more, the process proceeds to step S128. Step S128
, Bit b2 is set to 1 and bit b4 is set to 0.

As described above, the bits b2 and b4 corresponding to the I signal
Then, the process for obtaining Subsequently, the bits b3 and b5 corresponding to the Q signal are obtained. Steps S123 and S12
When any one of S5, S127, and S128 is completed, the process proceeds to step S129, and it is determined whether the Q signal is 6 or more.

If it is determined in step S129 that the Q signal is 6 or more, the process proceeds to step S130.
Bits b3 and b5 are both set to 0. On the other hand, if it is determined in step S129 that the Q signal is not 6 or more, the process proceeds to step S131. Step S131
Then, it is determined whether the Q signal is 4 or more.

When it is determined in step S131 that the Q signal is 4 or more, the process proceeds to step S132,
Bit b3 is set to 0 and bit b5 is set to 1. On the other hand, if it is determined in step S131 that the Q signal is not 4 or more, the process proceeds to step S133. In step S133, it is determined whether the Q signal is 2 or more.

If it is determined in step S133 that the Q signal is 2 or more, the process proceeds to step S134.
Bits b3 and b5 are both set to 1.

On the other hand, if it is determined in step S133 that the Q signal is not 2 or more, the process proceeds to step S135. In step S135, bit b3 is set to 1 and bit b5 is set to 0. Thus, the process of obtaining the bits b3 and b5 corresponding to the Q signal is completed. When any one of steps S130, S132, S134 and S135 is completed, the process proceeds to step S136, and the obtained b0, b1, b2, b3, b4 and b5 are output. Then, the process ends.

In the data obtained by the demapping process in the first quadrant, corresponding bits are inverted according to the first to fourth quadrants based on the flow shown in FIG.

[0040]

As described above,
If it is a simple demapping, the number of bits to be processed is reduced by performing the projection process in the first quadrant by utilizing the symmetry of the data arrangement and performing the demapping in the first quadrant.
It was possible to reduce the circuit scale.

However, in digital broadcasting,
Error correction is strengthened to remove noise mixed in the transmission path, and processing such as Viterbi decoding is performed. In such decoding processing, it is necessary to transmit data accuracy information (distance between adjacent data in the I-axis direction and Q-axis direction) to the demapping data to the Viterbi decoding circuit or the like. Therefore, each bit of the demapping result is not a hard decision that is made based on a binary value of 0 or 1 but a soft decision that is made based on a multi-valued decision that reflects the reliability of the decision data.

FIG. 20 is a block diagram of a circuit for performing demapping in the digital broadcast receiving apparatus.

Referring to FIG. 20, the circuit for this demapping receives a 6-bit signal b upon receiving an I signal and a Q signal.
64QAM demapping unit 522 that outputs a signal of 18 bits in which each of 0 to b5 is represented by a weight of 3 bits
And a parallel-serial conversion circuit 524 that receives the output of the 18-bit 64QAM demapping unit 522 and performs parallel-serial conversion.

Here, the data accuracy information will be described. FIG. 21 is a schematic diagram for explaining accuracy information of data.

Referring to FIG. 21, the n-th bit data of the 6-bit demapping data shown in FIG.
If the position of the I signal or the Q signal on the plane is close to 0, the 3-bit data (bn
0, bn1, bn2) becomes (000), and when it is close to 1, it becomes (111).

For example, assume that the I signal is between +1 and +3. As can be seen from FIG. 15, when the I signal is +1 (b0, b2, b4) is (0, 1, 0),
When the I signal is +3, it is (0, 1, 1).

At this time, the bits b0 = 0 and b2 = 1 are established regardless of whether the I signal is +1 or +3. That is, it is certain that bit b0 is 0. In this case,
(B00, b01, b02) is (000). Also, it is certain that bit b2 is 1. Therefore, the bits (b20, b21, b22) are (111).

Regarding the bit b4 between 0 and 1, the bit (b40, b41, b42) approaches (000) when the I signal is close to +1 and (111) when the I signal is close to +3. Get closer.

That is, when 1-bit data is represented by 3 bits of data accuracy information, the result of demapping becomes 6 bits in the case of QPSK and 12 bits in the case of 16QAM, depending on the modulation system. 64QA
In the case of M, it becomes 18 bits as shown in FIG.

FIG. 22 is a diagram for explaining soft decision demapping performed in digital broadcasting using 64QAM.

Referring to FIG. 22, input I signal, Q
Consider the case where the coordinate point corresponding to the signal is point E.

The closest reference signal point where the I signal is smaller than the point E and the Q signal is smaller than the point E is selected as the reference point F. The accuracy information is determined by the distance LIE on the I axis from the reference point F and the distance LQE on the Q axis from the reference point F. Since the point E is a point between the points H, J, G, and F, this accuracy information is reflected in the bits b3 and b4 of the 6-bit demapping data.

FIG. 23 is a block diagram showing the configuration of the 64QAM demapping section 522 in FIG.

Referring to FIG. 23, 64QAM demapping section 522 detects reference points corresponding to the I and Q signals received from the time deinterleave section.
32, and a probability information calculation unit 534 for obtaining accuracy information with respect to the reference point detected by the reference point detection unit 532.
And a data synthesizing output unit 536 that receives the output of the certainty information calculation unit 534 and outputs 18-bit data.

When the data (IE, QE) corresponding to the point E in FIG. 22 is input, the reference point detection unit 532 detects the closest point F having smaller I and Q values than the point E.

When the reference point F is obtained, the probability information calculation section 534 calculates the accuracy information based on the distance from the reference point shown in FIG. For example, in the case of point E in FIG. 22, bits b3 and b4 are represented by 3-bit accuracy information. The bits other than bits b3 and b4 are represented by either 000 or 111 by the data synthesizing output unit 536. And the demapping data is
It is output as a total of 18 bits of data.

24 and 25 are 64Q in FIG.
9 is a flowchart showing a process of an AM demapping unit 522.

Referring to FIG. 24, when the process is started, first, in order to obtain the closest point F in FIG. 22, step S14
In 1 to S157, the I signal is successively compared with a predetermined value to determine bits b0, b2 and b4.

First, in step S141, it is determined whether the signal IE is 7 or more. If it is determined that the signal IE is 7 or more, the process proceeds to step S142 and the bit b
0, b2, b4 are all set to 0. If the bit on which the accuracy information is reflected is bit bn, then bit bn is "none" for the I signal in this case.

If it is determined in step S141 that the signal IE is not 7 or more, the process proceeds to step S143. In step S143, it is determined whether the signal IE is 5 or more.

When it is determined in step S143 that the signal IE is 5 or more, the process proceeds to step S144. In step S144, bits b0, b2 and b4 are set to 0, 0 and 1, respectively. The bit bn to which the accuracy information is reflected is set to b4.

That is, when the process reaches step S144, the signal IE is 5 or more and less than 7. Now, consider the case where the I signal is between +5 and +7 in FIG. Bits (b0, b2) are common (0, 0) regardless of whether the I signal is +5 or +7. Bit b4 is 1 when the I signal is +5, and I
It is 0 when the signal is +7. In other words, I signal is +5 and +
7 is a case where the bit b4 is 1 or 0, and the accuracy information is reflected in the bit b4 according to the distance from the reference point.

In step S143, the signal IE is 5
If it is determined that the above is not the case, the process proceeds to step S145. In step S145, it is determined whether the signal IE is 3 or more.

If it is determined in step S145 that the signal IE is 3 or more, the process proceeds to step S146. In step S146, the bits b0, b2, b4 are set to 0, 1, 1 respectively, and the bit bn is judged to be b2.

When it is determined in step S145 that the signal IE is not 3 or more, the process proceeds to step S147. In step S147, it is determined whether the signal IE is 1 or more.

If it is determined in step S147 that the signal IE is 1 or more, the process proceeds to step S148. In step S148, bits b0, b2, b4 are set to 0, 1, 0, respectively, and it is determined that bit bn is b4.

On the other hand, in step S147, the signal IE
If it is determined that is not 1 or more, step S149
Proceed to. In step S149, it is determined whether the signal IE is -1 or more.

In step S149, the signal IE is -1.
When it is determined that the above is the case, the process proceeds to step S150. In step S150, bits b0, b2, b4 are set to 1, 1, 0, respectively, and bit bn is determined to be b0.

On the other hand, in step S149, the signal IE
If it is determined that is not -1 or more, step S1
Proceed to 51. In step S151, it is determined whether the signal IE is -3 or more.

In step S151, the signal IE is -3.
If it is determined that the above is the case, the process proceeds to step S152. In step S152, bits b0, b2, b4 are set to 1, 1, 1 respectively, and it is determined that bit bn is b4.

On the other hand, in step S151, the signal IE
If it is determined that is not -3 or more, step S15
Go to 3. In step S153, it is determined whether the signal IE is -5 or more.

In step S153, the signal IE is -5.
If it is determined that the above is the case, the process proceeds to step S154. In step S154, bits b0, b2 and b4 are set to 1, 0 and 1, respectively, and it is determined that bit bn is b2.

On the other hand, in step S153, the signal IE
If it is determined that is not -5 or more, step S1
Proceed to 55. In step S155, it is determined whether the signal IE is -7 or more.

In step S155, the signal IE is -7.
When it is determined that the above is the case, the process proceeds to step S156. In step S156, bits b0, b2, b4 are set to 1, 0, 0, respectively, and it is determined that bit bn is b4.

On the other hand, in step S155, the signal IE
If it is determined that is not -7 or more, step S15
Proceed to 7. In step S157, bits b0, b2, b
4 are set to 1, 0 and 0, respectively, and it is determined that there is no bit bn.

The above steps S141 to S157
When the processing of (1) is completed, the Q signal is determined in steps S158 to S174.

Referring to FIG. 25, first, step S158.
At, it is determined whether the data QE is 7 or more.

When it is determined in step S158 that the signal QE is 7 or more, the process proceeds to step S159 and all bits b1, b3 and b5 are set to 0. If the bit on which the accuracy information is reflected is bit bm, then bit bm is "none" for the I signal in this case.

If it is determined in step S158 that the signal QE is not 7 or more, the process proceeds to step S160. In step S160, it is determined whether the signal QE is 5 or more.

If it is determined in step S160 that the signal QE is 5 or more, the process proceeds to step S161. In step S161, bits b1, b3 and b5 are set to 0, 0 and 1, respectively. Further, the bit bm to which the accuracy information is reflected is set to be b5.

That is, when the step S161 is reached, the signal QE is 5 or more and less than 7. Here, consider the case where the Q signal is between +5 and +7 in FIG. The bits (b1, b3) are common (0, 0) regardless of whether the Q signal is +5 or +7. Bit b5 is 1 when the Q signal is +5, and Q
It is 0 when the signal is +7. That is, the Q signal is +5 and +
7 is a case where the bit b5 is 1 or 0, and the accuracy information is reflected in the bit b5 according to the distance from the reference point.

In step S160, the signal QE is 5
If it is determined that the above is not the case, the process proceeds to step S162. In step S162, it is determined whether the signal QE is 3 or more.

If it is determined in step S162 that the signal QE is 3 or more, the process proceeds to step S163. In step S163, the bits b1, b3, b5 are set to 0, 1, 1 respectively, and it is determined that the bit bm is b3.

If it is determined in step S162 that the signal QE is not 3 or more, the process proceeds to step S164. In step S164, it is determined whether the signal QE is 1 or more.

If it is determined in step S164 that the signal QE is 1 or more, the process proceeds to step S165. In step S165, the bits b1, b3, b5 are set to 0, 1, 0, respectively, and it is determined that the bit bm is b5.

On the other hand, in step S164, the signal QE
If it is determined that is not 1 or more, step S166
Proceed to. In step S166, it is determined whether the signal QE is -1 or more.

In step S166, the signal QE is -1.
When it is determined that the above is the case, the process proceeds to step S167. In step S167, the bits b1, b3, b5 are set to 1, 1, 0, respectively, and the bit bm is judged to be b1.

On the other hand, in step S166, the signal QE
If it is determined that is not -1 or more, step S1
Proceed to 68. In step S168, it is determined whether the signal QE is -3 or more.

In step S168, the signal QE is -3.
When it is determined that the above is the case, the process proceeds to step S169. In step S169, the bits b1, b3, b5 are set to 1, 1, 1 respectively, and the bit bm is determined to be b5.

On the other hand, in step S168, the signal QE
If it is determined that is not -3 or more, step S17
Go to 0. In step S170, it is determined whether the signal QE is -5 or more.

In step S170, the signal QE is -5.
When it is determined that the above is the case, the process proceeds to step S171. In step S171, the bits b1, b3 and b5 are set to 1, 0 and 1, respectively, and the bit bm is determined to be b3.

On the other hand, in step S170, the signal QE
If it is determined that is not -5 or more, step S1
Proceed to 72. In step S172, it is determined whether the signal QE is -7 or more.

In step S172, the signal QE is -7.
If it is determined that the above is the case, the process proceeds to step S173. In step S173, the bits b1, b3 and b5 are set to 1, 0 and 0, respectively, and the bit bm is determined to be b5.

On the other hand, in step S172, the signal QE
If it is determined that is not -7 or more, step S17
Go to 4. In step S174, bits b1, b3, b
5 are set to 1, 0 and 0, respectively, and it is judged that there is no bit bm.

When the processing of steps S158 to S174 is completed, the bit b for which the reference point and accuracy information should be calculated.
Since n and bm have been determined, step S17
Then, the process proceeds to step 5 to calculate the accuracy information of the bits bn and bm.

Then, in step S176, bit b
The bits other than n and bm are also set to 000 or 111, the result is combined and output, and the process is completed.

As described above, in the case of the simple hard decision demapping as shown in FIG. 16, the symmetry of the constellation in FIG.
By projecting the operation in the first quadrant and processing it as shown in 9, it was possible to reduce the number of processing bits and circuits. However, as described with reference to FIGS. 22 to 25, at the time of demapping in the terrestrial digital broadcast receiving apparatus, first, the reference values (+7, +5, +) of the I axis and the Q axis, respectively.
3, +1, -1, -3, -5, -7) is calculated, the distance is calculated from the reference value using a large number of reference points (64 points), and demapping is performed for each bit. Since it was necessary, there was a problem that the circuit scale of the demapping section became large.

An object of the present invention is to provide a digital broadcast receiving apparatus in which the circuit scale is reduced even in the case of soft decision demapping used in the digital broadcast receiving apparatus.

[0099]

According to the present invention, there is provided a digital broadcast receiving apparatus for receiving a signal modulated by an orthogonal frequency division multiplex transmission system, which receives an I signal and a Q signal and which is on an IQ plane. A demapping means for associating with the signal point is provided. The demapping means determines whether the coordinate points obtained by projecting the received I signal and Q signal on the IQ plane are in the vicinity of the axis depending on whether the distance from the I axis or the Q axis is less than or equal to a predetermined distance. A near-axis determining means for determining whether or not there is a quadrant determining means for determining which quadrant on the IQ plane the coordinate point is in when the coordinate point is not near the axis;
According to the output of the quadrant determining means, the coordinate point is set to the first on the IQ plane.
The first coordinate projection means for obtaining the first transformed coordinate point projected in the quadrant and the first transformed coordinate point are associated with any one of the first signal points in the first quadrant to obtain the first signal. First soft decision processing means for obtaining accuracy information according to the distance between the signal point adjacent to the point and the first transformed coordinate point, and generating the first quadrant demapping data, and the first quadrant demapping data. First data conversion means for converting and outputting demapping data corresponding to the coordinate points before being projected in the first quadrant;
When the coordinate point is near the axis, the coordinate point is associated with any of the second signal points near the axis, and the second point
And a near-axis demapping means for obtaining accuracy information according to the distance between the signal point adjacent to the signal point and the coordinate point and generating demapping data.

[0100] Preferably, the demapping means around the axis is
Axis determining means for determining which of the I-axis and Q-axis the coordinate point is, and positive / negative determining means for determining whether the coordinate point exists in the positive / negative area of the axis determined by the axis determining means. , A second coordinate projecting means for projecting a coordinate value to a positive area in accordance with the output of the positive / negative determining means to obtain a second transformed coordinate point, and a second transformed coordinate point for either of the positive areas. A positive region for which correspondence is made to three signal points, accuracy information is obtained according to the distance between the signal point adjacent to the third signal point and the second conversion coordinate point, and positive region demapping data is generated. It includes demapping means and second data converting means for converting the positive area demapping data and outputting the demapping data corresponding to the coordinate values before being projected onto the positive area.

Preferably, the positive area demapping means is
Second soft decision processing means for performing processing when the second transformed coordinate point is near the I axis of the positive region, and second soft decision processing means for performing processing when the second transformed coordinate point is near the Q axis of the positive region. 3 soft decision processing means.

More preferably, when the second transformed coordinate point is near the Q axis of the positive region, the positive region demapping means transforms it into the third transformed coordinate point near the I axis of the corresponding positive region. Symmetric point detection means, second soft decision processing means for performing processing when the second conversion coordinate point is near the I axis of the positive region and processing for the third conversion coordinate point, and second conversion coordinate point Is near the Q axis of the positive region, the data calculation unit receives the output of the second soft decision processing means and calculates data corresponding to the result of processing the second conversion coordinate point.

[0103]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same reference numerals in the drawings indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving apparatus 1000 according to a first embodiment of the present invention.

Referring to FIG. 1, digital broadcast receiving apparatus 1
At 000, the RF signal received from the antenna (not shown) is tuned by the tuner 100, and the
It is given to each demodulation section 102.

The demodulated signal from the OFDM demodulator 102 is
The MPEG decoding unit 11 is provided to the transport stream decoder (hereinafter, referred to as TS decoder) 104.
Given to 0. That is, in the TS decoder 104,
The baseband signal is extracted from the selected channel.

The MPEG decoding unit 110 receives the data stream supplied from the TS decoder 104 and uses a random access memory (hereinafter referred to as RAM) 112 as a buffer for temporarily storing data, thereby generating a video signal and an audio signal. Convert to.

Digital broadcast receiving apparatus 1000 further has a built-in storage device 1 for receiving and storing a signal from TS decoder 104 via data bus BS1.
48, an arithmetic processing unit 144 for performing a predetermined process on the data accumulated in the built-in storage device 148 via the data bus BS1, and outputting the data.
R for recording the program in 44 arithmetic processing
It includes an OM 140, a RAM 142 that provides a memory area for the operation of the arithmetic processing unit 144, and a high-speed digital interface 146 for inputting / outputting data between the data bus BS1 and the outside. Although not particularly limited, as the built-in storage device 148 and the ROM 140, for example, a flash memory capable of electrically writing / reading data can be used.

The data after the arithmetic processing unit 144 processes the data stored in the built-in storage device 148 in accordance with the instruction given from the outside is combined by the on-screen display processing unit 130. To the vessel 160.2.

The synthesizer 160.2 synthesizes the output from the MPEG decoding unit 110 and the output from the on-screen display processing unit 130, and then outputs the video output terminal 16
Give to 4. The output from the video output terminal 164 is given to the display unit 1004.

Digital broadcast receiving apparatus 1000 further receives the result data processed by arithmetic processing unit 144 based on the data stored in built-in storage device 148, and outputs the sound effect to the video output on the display unit. Etc. and receives the data processed by the arithmetic processing unit 144 based on the data accumulated in the built-in storage device 148 and the additional sound generator 120 for giving to the synthesizer 160.1. A PCM decoder 122 is provided which is generated and provided to the combiner 160.1.

The synthesizer 160.1 outputs the output from the MPEG decoding unit 110, the additional sound generator 120 and the PCM.
Upon receiving the output from the decoder 122, the synthesis result is given to the audio output terminal 162. The audio signal given to the audio output terminal 162 is output from the audio output unit 1002 as an audio signal.

The digital broadcast receiving apparatus 1000 is
A modem 150 for exchanging data with the outside and an IC card interface 152 for receiving information from an IC card may be provided as necessary.

Through the high-speed digital interface 146, for example, the external storage device 180 such as the HDD device for the home server and the remote controller (or keyboard) 182 which is an external input device are connected to the data bus BS1.
Connected with.

Further, the digital broadcast receiving apparatus 1000 is
Display unit 100 that receives a video output and displays it on a display
4 or a voice output unit 1002 such as a speaker that receives a voice output signal and outputs a voice may be integrated.

FIG. 2 is a block diagram of the OFDM demodulator 10 of FIG.
FIG. 3 is a block diagram showing the configuration of No. 2.

Referring to FIG. 2, OFDM demodulation section 102
Is the RF input from the RF antenna by the tuner
An analog-digital conversion unit 202 that receives an input signal that has been down-converted to a desired frequency and becomes a digital signal in the input unit, and an F that performs an FFT by receiving the output of the analog-digital conversion unit 202
FT section 204, frequency deinterleave section 206 that receives the output of FFT section 204, and frequency deinterleave section 2
And a time deinterleave unit 208 that receives the output of 06.

In the analog-to-digital conversion unit 202, the analog signal is converted into a digital signal and the I signal and the Q signal are converted into FF by using Hilbert conversion or the like.
Output to T section. The FFT unit 204 performs a fast Fourier transform on the input signal, decomposes the data multiplexed on the time axis into frequency components, and outputs the data as frequency axis data to the frequency deinterleave unit 206. The frequency deinterleave unit 206 restores the frequency interleave performed to compensate for the loss of the specific frequency signal due to the reflection of radio waves.

Time deinterleaving section 208 receives the output signal of frequency deinterleaving section 206 and restores the time interleaving performed for fading resistance and the like.

OFDM demodulation section 102 further receives demapping section 2 which receives the output of time deinterleaving section 208.
10, a bit deinterleave unit 212 that receives the output of the demapping unit 210, and a bit deinterleave unit 21.
2 and the byte deinterleave unit 216 that receives the output of the Viterbi decoding unit 214.
And the TS receiving the output of the byte deinterleave unit 216
Reproduction unit 218 and RS receiving the output of TS reproduction unit 218
And a decoding unit 220.

In demapping section 210, the time-deinterleaved I and Q signals are combined with a data accuracy signal (distance between adjacent data in the I-axis direction and Q-axis direction). Converted to mapping data.

In the demapping data, after the bit interleaving performed for the purpose of increasing error resilience is canceled in the bit deinterleaving section 212, the Viterbi decoding section 214 decodes the convolutional coding processing performed on the transmitting side. Done. The signal subjected to Viterbi decoding is input to the byte deinterleaving unit 216, and the byte interleaving performed for the purpose of increasing error resilience is canceled similarly to the bit interleaving. Then, it is input to the TS reproduction unit 218,
The data is accumulated in the buffer in transport stream packet (TSP) units.

If the data packet is stored in the buffer, the data packet is input to the RS decoding unit 220, and if it is not stored, the null packet is input to the RS decoding unit 220. The RS decoding unit performs Reed Solomon (RS) decoding and error correction.

The error-corrected signal is then input to the MPEG decoder via the TS decoder, the compressed signal is expanded and converted into analog, and converted into analog video and analog audio signals.

FIG. 3 shows the demapping unit 21 in FIG.
It is a block diagram showing the composition of 0.

Referring to FIG. 3, demapping unit 210
Receives 18-bit data (b00, b01, b02, b10, b11, b12, b20, b21, b22, b30, b31, b32,
b40, b41, b42, b50, b51, b52) for outputting a 64QAM demapping unit 222 and a 64QAM demapping unit 222
And a parallel-serial conversion circuit 224 that serially outputs signals given in parallel from.

FIG. 4 is a diagram for explaining the processing reduction by utilizing the symmetry of the constellation in the present invention.

Referring to FIG. 4, a region where both the I signal and the Q signal are 1 or more in the first quadrant is referred to as region A1. A region in which the Q signal is 1 or more and the I signal is -1 or less in the second quadrant is referred to as a region A2. I signal in the third quadrant
A region where the Q signal is 1 or less and the Q signal is -1 or less is A3. A region in which the I signal is 1 or more and the Q signal is -1 or less in the fourth quadrant is referred to as a region A4.

Next, the region near the axis will be described. A region in which the Q signal is between -1 and +1 and the I signal is 1 or more is defined as a region A5. The area A5 is an area A51 where 1 ≦ I <3 and an area A52 where 5 ≦ I <5.
It is divided into an area A53 where <7 and an area A54 where I ≧ 7.

A region in which the Q signal is between -1 and 1 and the I signal is -1 or less is defined as a region A6.

A region where the I signal is between -1 and 1 and the Q signal is 1 or more is defined as a region A7. Area A7
Is divided into a region A71 where 1 ≦ Q <3, a region A72 where 3 ≦ Q <5, a region A73 where 5 ≦ Q <7, and a region A74 where Q ≧ 7.

A region in which the I signal is between -1 and 1 and the Q signal is -1 or less is defined as a region A8.

Finally, the area where the I signal is between -1 and 1 and the Q signal is between -1 and 1 is called area A9.

FIG. 5 is a block diagram showing the configuration of the 64QAM demapping section 222 in FIG.

Referring to FIG. 5, the 64QAM demapping unit 222 determines that the input IQ signal is near the axis, and the near-axis determining unit 232 determines that it is not near the axis. When it is determined, the quadrant determination unit 234 that determines the quadrant of the input data, and the quadrant determination unit 234
A coordinate projection unit 236 for projecting the coordinates of the data input based on the quadrant determined by the first quadrant, and a soft decision processing unit 238 for performing a soft decision process on the data projected in the first quadrant,
The data conversion unit 240 that converts the value obtained by the soft decision processing unit 238 into the demapping data of the original quadrant.

The 64QAM demapping unit 222 further determines whether the axis is the I-axis or the Q-axis when the near-axis determining unit 232 determines that the axis is the I-axis or the Q-axis, and the input signal. If the coordinate point is near the axis, a positive / negative determination unit 244 that determines the positive / negative of the axis close to the coordinate point, and a coordinate projection unit 246 that projects the coordinate point to the positive coordinate according to the output of the positive / negative determination unit 244. An I-axis soft decision processing unit 248 that performs soft-decision demapping near the I-axis of the projected coordinates, a Q-axis soft decision processing unit 250 that performs soft-decision demapping near the Q axis, and processing units 248 and 250. And a data conversion unit 252 that receives the output of the above and converts it into demapping data of the original code.

FIG. 6 is a flow chart showing the processing of the 64QAM demapping section 222 in FIG.

Referring to FIG. 6, first in step S1, it is determined whether or not the absolute value of the I signal is greater than 1.
If the absolute value of the I signal is greater than 1, it is determined that there is no data near the I axis, and the process proceeds to step S2. On the other hand, if it is determined that the absolute value of the I signal is not greater than 1, it is determined that the input data is in the vicinity of the Q axis, and the process proceeds to step S9.

In step S2, it is determined whether the absolute value of the Q signal is 1 or more. If it is judged to be 1 or more, it is judged that the coordinates of the data are not in the vicinity of the I axis, and the process proceeds to step S3 to project the coordinates in the first quadrant to obtain the demapping data.

On the other hand, if it is determined in step S2 that the absolute value of the Q signal is not 1 or more, it is determined that the coordinates of the input data are near the I axis, and the flow advances to step S5.

In step S5, it is determined whether the I signal is 1 or more. When it is determined in step S5 that the I signal is 1 or more, that is, the coordinate point of the input signal exists in the area A5 of FIG. Then, the process proceeds to step S7, and demapping around the I axis (I ≧ 1) is performed.

On the other hand, if it is determined in step S5 that the I signal is not 1 or more, then in step S1 I signal
Since the absolute value of the signal is determined to be 1 or more, the I signal is negative after all. In this case, it turns out that the coordinate point of the input signal is in the area A6 in FIG.
In this case, in order to simplify the processing, in step S6, the absolute value of the I signal is obtained and the coordinates are once projected onto the area A5. Then, the process proceeds to step S7, and demapping near the I axis is performed.

The demapping result obtained in step S7 is used as it is when the I signal is determined to be positive in step S5, and is used in step S8 when the I signal is determined to be negative. Bit b0
A process of inverting 0, b01, b02 is performed. Then, the process proceeds to step S4.

Next, the case where it is determined in step S1 that the absolute value of the I signal is not 1 or more will be described. In this case, the coordinate point of the input signal is near the Q axis. First, in step S9, it is determined whether the absolute value of the Q signal is 1 or more. Q in step S9
When it is determined that the signal is 1 or more, step S1
Go to 0. On the other hand, when it is determined in step S9 that the Q signal is not 1 or more, the coordinate point of the input signal exists in the area A9 in FIG. That is, since the coordinates are near the origin, the demapping process can be easily performed, and the demapping near the origin is performed in step S14.

In step S9, the absolute value of the Q signal is 1
When it is determined that the above is the case, the coordinate point of the input signal exists in either of the areas A7 and A8 in FIG.
In step S10, it is determined whether the Q signal is 1 or more. When it is determined that the Q signal is 1 or more, that is, it is understood that the coordinate point of the input signal exists in the area A7. In this case, the process directly proceeds to step S12.

On the other hand, if it is determined in step S10 that the magnitude of the Q signal is not 1 or more, that is, Q
The signal value is negative and the coordinate point of the input signal is the area A8 in FIG.
It turns out that it exists in. When the coordinate point of the input signal exists in the area A8 of FIG. 4, the absolute value of the Q signal is obtained in step S11 and the coordinates are projected in the area A7. Then, the process proceeds to step S12. In step S12, demapping near the Q axis (Q ≧ 1) is performed. Then, the result is used as it is when the Q signal is determined to be positive in step S10, while the bits b10, b11 and b13 are inverted in step S13 when the Q signal is determined to be negative. Processing is performed.
Then, the process proceeds to step S4.

FIG. 7 is a flow chart showing the processing of step S3 in FIG. Referring to FIG. 7, first, in step S21, it is determined whether the I signal is 1 or more. If the I signal is 1 or more, the process proceeds to step S22. If the I signal is not 1 or more, the process proceeds to step S23.

In step S22, it is determined whether the Q signal is 1 or more. When it is determined in step S22 that the Q signal is 1 or more, the coordinate point of the input signal is in the first quadrant. That is, there are coordinate points of the input signal inside the area A1 in FIG. In this case, the process directly proceeds to step S27.

When it is determined in step S22 that the magnitude of the Q signal is not 1 or more, the coordinate point of the input signal is in the fourth quadrant. That is, it can be seen that the coordinate point of the input signal is in the area A4 of FIG. In that case, step S2
In step 4, the absolute value of the Q signal is obtained, and that value is used as the Q signal, and the process proceeds to step S27.

On the other hand, in step S21, the I signal becomes 1
A case where it is determined that the above is not the case and the process proceeds to step S23 will be described. First, in step S23, it is determined whether the Q signal is 1 or more. When it is determined that the Q signal is 1 or more, the coordinate point of the input signal is in the second quadrant. That is, there are coordinate points of the input signal in the area A2 of FIG. In this case, the process proceeds to step S25, the absolute value of the I signal is obtained, and this is processed as the I signal in step S27.

On the other hand, in step S23, the Q signal becomes 1
If it is determined that the above is not the case, the coordinate point of the input signal is the third point.
In the quadrant. That is, the coordinate point of the input signal is the area A in FIG.
Exists in 3. In this case, the absolute value of the I signal and the absolute value of the Q signal are obtained in step S26, and these are used as the I signal and the Q signal, respectively, and the process of step S27 is performed.

In step S27, the first quadrant soft decision demapping described later is performed. If the coordinate point of the input signal is in the first quadrant, the demapping result obtained in step S27 proceeds directly to step S31,
If it is in the fourth quadrant, inversion processing of bits b10, b11, b12 is performed in step S28.

If the coordinate point of the input signal is in the second quadrant, inversion processing of bits b00, b01, b02 is performed on the result of demapping in step S29. If the coordinate point of the input signal is in the third quadrant, bits b00, b01, b02, b10, b11, b are added to the result of the demapping in step S30.
12 inversion processing is performed.

After the above processing is performed, the result is output in step S31 and the processing ends.

FIG. 8 is a flow chart for explaining the soft decision demapping process of the first quadrant in step S27 in FIG.

Referring to FIG. 8, the process of step S27 is performed with the I signal and the Q signal projected in the first quadrant. That is, the I signal after projection is called an IE signal, and the Q signal after projection is called a QE signal. It should be noted that in the process up to step S27 in FIG. 7, both the IE signal and the QE signal are limited to the case of having a magnitude of 1 or more.

First, in step S41, the IE signal is 7
It is determined whether or not the above. When the IE signal is 7 or more, bits b0,
There is no doubt that b2 and b4 are 0, 0 and 0, respectively. Therefore, in step S42, bits b0, b
2, b4 are set to 0, 0, 0, respectively, and the bit bn on which the accuracy information is reflected is “none”.

On the other hand, if it is determined in step S41 that the IE signal is not 7 or more, the process proceeds to step S43. In step S43, it is determined whether the IE signal is 5 or more. When it is determined that the IE signal is 5 or more, the IE signal is 5 or more and less than 7. In this case, the process proceeds to step S44 and bits b0, b
2, b4 are set to 0, 0, 1 respectively, and it is determined that the bit bn on which the accuracy information is reflected is b4. Then, the process proceeds to step S50.

On the other hand, if it is determined in step S43 that the IE signal is not 5 or more, the process proceeds to step S45. In step S45, it is determined whether the IE signal is 3 or more.

When it is determined in step S45 that the IE signal is 3 or more, the IE signal is 3 or more and less than 5. In this case, step S46
In, the bits b0, b2, b4 are set to 0, 1, 1 and the bit bn on which the accuracy information is reflected is determined to be b2.

On the other hand, when it is determined in step S45 that the IE signal is not 3 or more, that is, the IE signal is 1 or more and less than 3. In this case, in step S48, the bits b0, b2, b4 are set to 0, 1, 0, respectively, and it is determined that the bit bn on which the accuracy information is reflected is b4. Then, the process proceeds to step S50.

After step S50, the QE signal is judged. First, in step S50, it is determined whether the QE signal is 7 or more.

If it is determined in step S50 that the QE signal is 7 or more, the process proceeds to step S51. In this case, as shown in FIG. 15, bits b1, b3, b
There is no doubt that 5 is 0, 0, 0, respectively, and the bit bm on which the accuracy information is reflected is determined to be “none”.

On the other hand, if it is determined in step S50 that the QE signal is not 7 or more, the process proceeds to step S52. In step S52, it is determined whether the QE signal is 5 or more.

If it is determined that the QE signal is 5 or more, the process proceeds to step S53. In this case, the QE signal is 5
Since it is above and smaller than 7, bit b1,
b3 and b5 are set to 0, 0 and 1, respectively, and the bit bm on which the accuracy information is reflected is determined to be b5.

On the other hand, if it is determined in step S52 that the QE signal is not 5 or more, the process proceeds to step S54. In step S54, it is determined whether the QE signal is 3 or more. When it is determined that the QE signal is 3 or more, the process proceeds to step S55. In this case, since the QE signal is 3 or more and less than 5, bit b
1, b3, b5 are set to 0, 0, 1 respectively, and the bit bm on which the accuracy information is reflected is determined to be B3.

On the other hand, if it is determined in step S54 that the QE signal is not 3 or more, the process proceeds to step S57. In this case, since the QE signal is 1 or more and less than 3, the bits b1, b3, b5 are 0,
Bit bm set to 1,0 and reflecting accuracy information
Is determined to be b5.

Steps S51, S53, S55, S57
When any one of the processes is finished, the process proceeds to step S59. In step S59, bits bn and bm, which will be described later, are set.
The calculation process of the accuracy information is performed. Then, in step S60, the bits bn and bm for which the accuracy information has been calculated.
The demapping result is output as 18 bits including the other bits. With the above, step S27 in FIG.
The processing of the first quadrant soft decision demapping is completed.

FIG. 9 is a flow chart for explaining the calculation processing of the probability information of the bits bn and bm in step S59 in FIG.

In step S59, the bits bn and b on which the accuracy information is reflected in the 6-bit demapping result.
The calculation process of the accuracy information is performed on m. In addition,
For the other 4 bits, if it is 0, it is bit-extended to 000, and if it is 1, it is bit-extended to 111, resulting in a demapping result of a total of 18 bits.

For simplification of description, a case where signals IE and QE corresponding to point E in FIG. 22 are given as inputs will be described as an example.

Referring to FIGS. 9 and 22, in the case of data corresponding to point E, the IE signal is 1 or more and less than 3, and the QE signal is 3 or more and less than 5. In this case,
In step S48 and step S55, the process proceeds to step S59, so that bit bn is b4 and bit bm is b3.

First, in step S71, the distance (LIE) between EFs in the I-axis direction is obtained.

If IE = 1.8, then LIE = IE-1 = 1.8-1 = 0.8, that is, LIE = 0.8. Next in step S72
In order to represent the bit b4 by a 3-bit number, the distance LFG between adjacent points is calculated. The LFG is calculated as LFG = 3-1 = 2.

Subsequently, in step S73, what is the value when the accuracy information is 7 at maximum is calculated. Note that 7 is the maximum number that can be represented by 3 bits.

[0176] (LIE / LFG) × 7 = 0.8 / 2 × 7 = 2.8 The accuracy information is required to be about 3.

Next, in step S74, this is converted into a binary number. In step S48 of FIG.
Since 4 is obtained as 0, it is the accuracy information for 0, so 3 is directly converted to a binary number and bit b4 is set to 0.
It is extended to 3 bits of 11.

Subsequently, after step S75, the accuracy information of QE is obtained. When the QE signal is 3.6 in step S75, LQE = QE-3 = 3.6-3 = 0.6 That is, LQE = 0.6.

Then, in step S76, the distance between FHs is obtained. LFH = 5-3 = 2 Therefore, LFH is calculated to be 2. Then, in step S77, accuracy information for the QE signal is calculated.

[0180] (LQE / LFH) × 7 = 0.6 / 2 × 7 = 2.1 That is, the accuracy information is required to be about 2.

Then, in step S78, the accuracy information is converted into a binary number. However, step S55 in FIG.
Since bit b3 is required to be 1 in
This accuracy information is the likelihood of being 1. That is, it is necessary to subtract the accuracy information obtained from the maximum value 7 and convert it into a binary number before converting it into a binary number.

B3 = 7-2 = 5 By converting this into a binary number, b3 is obtained as 101.

From the coordinates of points F, G, H, and J, the 1st, 2nd, 3rd, and 6th bits of point E before expansion are "00".
0 "," 000 "," 111 "," 111 ". The data of b4 and b5 thus obtained are combined, and the demapping value at the point E is (000000,111,101,01).
0,111) is calculated.

Next, the demapping process near the I axis performed in step S7 in FIG. 6 will be described.

FIG. 10 is a flow chart for explaining the demapping processing near the I axis.

FIG. 11 is a diagram for explaining an example of demapping near the axis. Referring to FIGS. 10 and 11, it is assumed that a signal corresponding to point K (IK, QK) is given as an input signal. IK> 1, | QK | ≦ 1, and prior to the processing, the closest M point is searched for in the direction in which both the I signal and the Q signal have smaller values than the point K. The point M has a coordinate of 1 on the I axis and a coordinate of -1 on the Q axis. First, in step S81, the distance (LIK) between KMs in the I-axis direction is obtained.

LIK = IK-1 = 1.8-1 = 0.8
(When IK = 1.8) Next, in step S82, the distance (LMN) between MNs in the I-axis direction is obtained.

LMN = 3-1 = 2 Subsequently, in step S83, accuracy information in the I-axis direction is obtained.

(LIK / LMN) × 7 = 0.8 / 2 × 7 = 2.8 That is, the accuracy information is determined to be about 3. Then, in step S84, conversion into a 3-bit binary number is performed. In this case, since the correctness information is the correctness information for 0, it is directly converted to a binary number and bit b4
Is converted to 011.

Subsequently, in step S85, the distance (LQK) between the KMs in the Q-axis direction is obtained.

LQK = QK + LQ1 = 0.8 + 1 = 1.
8 (when QK = 0.8) Subsequently, in step S86, the distance between the MPs (LMP)
Is required.

LMP = 1-(-1) = 2 Then, in step S87, accuracy information in the Q-axis direction is obtained.

[0193] (LQK / LMP) × 7 = 1.8 / 2 × 7 = 6.3 That is, the accuracy information is determined to be about 6.

Subsequently, in step S88, conversion into a binary number is performed. However, in this case, in consideration of the fact that the bit b1 is 1, the accuracy information is converted into a binary value by subtracting the value obtained from the maximum value 7 of the 3-bit binary number as the accuracy information for 1.

B1 = 7-6 = 1 That is, the bit b1 is converted into 001.

As described above, the demapping value (00
0,001,111,111,011,000) is calculated.

By the above description, the demapping when the coordinates of the input data exist in the area A5 of FIG. 4 has been described.

Here, if the data 000 corresponding to the bit b0 of the demapping result of the area A5 is changed to 111, it can be converted into the demapping data when the data exists in the area A6. Further, the area A7 is demapped in the same manner as the area A5, and if the data 000 corresponding to the bit b1 of the demapping result of the data having the coordinates in the area A7 is changed to 111, the coordinates of the input data are input to the area A8. Can be converted to the demapping result when exists.

Finally, when data exists in the area A9 near the origin, | IK | <1, | QK | <1 and the demapping values are (* 1, * 2,111,111,00).
10,000). Depending on | IK | and | QK |
If K> 0 and QK> 0, * 1 and * 2 are both accuracy information regarding "0". If IK <0, QK> 0 * 1,
* 2 is accuracy information regarding "1" and "0", respectively. When IK <0 and QK <0, * 1 and * 2 are both accuracy information regarding "1" and "1".

If IK> 0 and QK <0, * 1 and * 2 are accuracy information regarding "0" and "1", respectively.

In this way, the areas A1, A5, A7,
All demapping can be performed by creating a demapping circuit corresponding to the section A9 and utilizing symmetry. Since each demapping circuit has a small number of processing bits, the circuit scale can be reduced as a whole.

[Second Embodiment] FIG. 12 shows a second embodiment.
3 is a block diagram showing a configuration of a demapping unit 222a of FIG.

Referring to FIG. 12, demapping unit 222
In the configuration of the demapping unit 222 illustrated in FIG. 5, a is a symmetry point detection unit 262 that detects a symmetry point of data corresponding to the Q axis, instead of the Q axis soft decision processing unit 250, and a position of the symmetry point. And a data calculation unit 264 that calculates a corresponding demapping value. Other configurations are similar to those of demapping unit 222, and description thereof will not be repeated.

In the second embodiment, the areas A1 and A shown in FIG.
When the coordinates of the input data are in A2, A3, A4 and area A9, the same processing as in the first embodiment is performed.

Next, regarding the areas A5 to A8, the area A6 is the area A5 as described in the first embodiment.
Since it is symmetric with, it can be obtained in the same manner.

Regarding the area A7, the area A5 and the area A7 in FIG. 4 are symmetrical with respect to the dotted line Q = I. Processing may be performed by utilizing this.

Referring again to FIG. 11, point X of area A7,
Y, Z, Z ', F, H, and H'are symmetrical to the points M, N, T, U, R, V, and W of the area A5, respectively.

Next, considering the point K (IK, QK) in the area 5, the demapping value of the point K inside the area A51 in FIG. 4 is (000, 001, 0) as found in the first embodiment.
00,111,011,000), and similarly, the demapping values of the point K ′ inside the area A52, the point K ″ inside the area A53, and the point K ″ ′ inside the area A54 of FIG. , 010, 010, 111, 111, 00
0), (000, 101.000, 111, 101,
000), (000, 010,000, 111, 00)
10,000).

Next, consider the demapping of the point Q in the area A71 in the area A7, the point Q'in the area A72, the point Q "in the area A73, and the point Q '''in the area A74. ，
The points symmetric with respect to the straight line Q = I of Q ′, Q ″, Q ′ ″ are points K, K ′, K ″, K ″ ′, respectively.

The points closest to the points K, K ', K ", K'" are points P, V, U, W, respectively, and the symmetrical points are points P, H, Z ', H', respectively. Is.

From these, for the demapping in the area A7, the bit b0 of the points P, H, Z ', H'is replaced with the bit b1 of the points K, K', K ", K"', respectively.
The point Q ″ in the area A4 remains unchanged, and the point Q ′ in the area A72 remains.
Replaces the 4th bit with the 3rd bit of point K ',
For the point Q in 71 and the point Q ″ in the area A73, the demapping values are obtained by replacing the sixth bit with the fifth bits of points K and K ″, respectively. The demapping result is the point Q (001, 1,000, 111, 111,000, 01).
1), Q '(010,000,111,010,00
0,111), Q ″ (101,000,111,00)
, 000,000,010), Q '''(011,000,11
1,000,000).

Next, regarding the area A8, the area A7
The second bit "000" of the demapping data of "11"
If it is changed to 1 ″, it can be converted into the demapping data of the area A8.
Demapping is possible with 5 parts. Therefore area A
Create a circuit for demapping 1, A5, A9,
All demapping can be done by using symmetry.

FIG. 13 is a flow chart showing the demapping processing according to the second embodiment. In the flowchart shown in FIG. 13, in the configuration of the flowchart described in FIG. 6, instead of the demapping process in the vicinity of the Q axis in step S12, the symmetric point conversion process in step S91 is performed, and then the demapping process in the vicinity of the I axis in step S7. By performing the mapping and subjecting the obtained result to the inverse symmetric point conversion in step S92, the processing in step S12 is eliminated to simplify the processing. Other structures are similar to those described with reference to FIG. 6, and therefore description will not be repeated.

In the symmetry point conversion process of step S91, the symmetry point with respect to the straight line Q = I is detected on the coordinate plane. That is, when the data corresponding to the point Q in FIG. 11 is obtained, the value of the point K is detected as this symmetrical point. This is subjected to demapping processing near the I axis in step S7. Then, the obtained result is subjected to the symmetric point inverse transformation process of step S92.

In step S92, the demapping value of the point Q is calculated based on the demapping value of the point K according to the position of the symmetric point (point K).

FIG. 14 is a diagram for explaining a process of converting the demapping result of the symmetric point K into the demapping result of the original point Q.

Referring to FIG. 14, the demapping result obtained in step S7 is K (000,001,11).
1,111,011,000). In this result, "001" which is the result of the bits b10, b11, b12 is set as the value of the bits b00, b01, b02,
"011", which is the result of bits b40, b41, and b42
To the values of bits b50, b51, b52. By performing such a process, the demapping result of the Q point is Q (001, 1,000, 111, 111,000, 0).
The result is obtained as 11).

As described above, in the second embodiment, the demapping circuit or the demapping process of the areas A1, A5 and A9 is performed, and the other parts are all demapped by using the symmetry. Can be done.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0220]

As described above, according to the present invention,
The number of bits for processing in the demapping unit of the terrestrial digital broadcast receiving apparatus can be reduced, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving apparatus 1000 according to a first embodiment of the present invention.

2 is a block diagram showing a configuration of an OFDM demodulation unit 102 in FIG.

3 is a block diagram showing a configuration of a demapping unit 210 in FIG.

FIG. 4 is a diagram for explaining reduction of processing by utilizing symmetry of constellation in the present invention.

FIG. 5 is a 64QAM demapping unit 22 in FIG.
FIG. 3 is a block diagram showing the configuration of No. 2.

FIG. 6 is a 64QAM demapping unit 22 in FIG.
6 is a flowchart showing the processing of No. 2.

FIG. 7 is a flowchart showing a process of step S3 in FIG.

8 is a flowchart for explaining the processing of soft decision demapping in the first quadrant in step S27 in FIG.

FIG. 9 shows the bit bn of step S59 in FIG.
It is a flowchart for demonstrating the calculation process of the probability information of bm.

FIG. 10 is a flowchart for explaining demapping processing near the I axis.

FIG. 11 is a diagram for explaining an example of demapping in the vicinity of an axis.

FIG. 12 is a block diagram showing a configuration of a demapping unit 222a according to the second embodiment.

FIG. 13 is a flowchart showing a demapping process according to the second embodiment.

FIG. 14 is a diagram for explaining a process of converting the demapping result of the symmetric point K into the demapping result of the original point Q.

FIG. 15 is a diagram for explaining simple demapping in 64QAM.

FIG. 16 is a block diagram showing a configuration of a circuit that performs conventional demapping processing.

17 is a block diagram showing a configuration of a 64QAM demapping unit 502 in FIG.

FIG. 18 is a flowchart showing a process of a 64QAM demapping unit 502 in FIG.

FIG. 19 is a flowchart showing details of demapping processing in the first quadrant in step S107 in FIG.

FIG. 20 is a block diagram of a circuit that performs demapping in the digital broadcast receiving device.

FIG. 21 is a schematic diagram for explaining accuracy information of data.

FIG. 22 is a diagram for explaining soft decision demapping performed in digital broadcasting using 64QAM.

23 is a block diagram showing a configuration of a 64QAM demapping unit 522 in FIG.

FIG. 24 is the first half of the flowchart showing the processing of the 64QAM demapping unit 522 in FIG.

FIG. 25 is the second half of the flowchart showing the processing of the 64QAM demapping unit 522 in FIG.

[Explanation of symbols]

100 tuner, 102 demodulation unit, 104 decoder, 110 decoding unit, 120 additional sound generator, 12
2 PCM decoder, 130 on-screen display processing unit, 144 arithmetic processing unit, 146 high-speed digital interface, 148 built-in storage device, 15
0 modem, 152 card interface, 16
0.1, 160.2 synthesizer, 162 audio output terminal,
164 video output terminals, 180 external storage devices, 2
02 analog-digital conversion unit, 204 FFT unit, 2
06 frequency deinterleave section, 208 time deinterleave section, 210 demapping section, 212 bit deinterleave section, 214 Viterbi decoding section, 216 byte deinterleave section, 218 TS reproducing section, 220 R
S decoding unit, 222, 222a demapping circuit, 22
4 parallel-serial conversion circuit, 232 axis vicinity determination unit, 234 quadrant determination unit, 236 coordinate projection unit, 238
Soft decision processing section, 240 Data conversion section, 242 Axis decision section, 244 Positive / negative decision section, 246 Coordinate projection section, 24
8 I-axis soft decision processing unit, 250 Q-axis soft decision processing unit, 2
52 data converter, 262 symmetry point detector, 264
Symmetry point data calculation unit, 1000 digital broadcast receiving device, 1002 audio output unit, 1004 display unit.

Claims (4)

[Claims] 1. A digital broadcast receiving apparatus for receiving a signal modulated by an orthogonal frequency division multiplex transmission system, wherein an in-phase detection axis signal and an in-phase detection axis signal are referred to as an I axis and an I signal, respectively. The detection axis signal is Q axis, Q
When referred to as a signal, a demapping unit that receives the I signal and the Q signal and associates the I signal and the Q signal with a signal point on the IQ plane is provided, and the demapping unit receives the received I signal and Q signal on the IQ plane. An axis-near axis determining unit that determines whether or not the projected coordinate point is near the axis depending on whether the distance from the I axis or the Q axis is less than or equal to a predetermined distance; If not in the vicinity, a quadrant determining means for determining which quadrant on the IQ plane the coordinate point is in, and the coordinate point is projected in the first quadrant on the IQ plane according to the output of the quadrant determining means First to obtain the first transformed coordinate point
Coordinate projection means, and the first conversion coordinate point is set to one of the first quadrants.
Corresponding to the first signal point, accuracy information is obtained according to the distance between the signal point adjacent to the first signal point and the first conversion coordinate point, and first quadrant demapping data is generated. A first soft decision processing means; a first data conversion means for converting the first quadrant demapping data and outputting demapping data corresponding to a coordinate point before being projected in the first quadrant; When the coordinate point is near the axis, the coordinate point is associated with any of the second signal points near the axis corresponding to the coordinate point, and the signal point adjacent to the second signal point and the coordinate point are A near-axis demapping means for obtaining accuracy information according to the distance and generating demapping data. 2. The axis vicinity demapping means determines whether the coordinate point is near the I axis or the Q axis, and whether the coordinate determination point is positive or negative. A positive / negative determining means for determining whether or not the coordinate point exists in the area, and a second coordinate projection for projecting the coordinate value on the positive area according to the output of the positive / negative determining means to obtain a second converted coordinate point. Means, and the second conversion coordinate point to the third of any of the positive region
Of the signal points adjacent to the third signal point and the accuracy information corresponding to the distance between the second conversion coordinate point and the signal point adjacent to the third signal point to obtain correct area demapping data. The method according to claim 1, further comprising area demapping means and second data conversion means for converting the positive area demapping data and outputting demapping data corresponding to coordinate values before being projected on the positive area. The digital broadcast receiving device according to. 3. The positive region demapping means, second soft decision processing means for performing processing when the second transformed coordinate point is near the I axis of the positive region, and the second transformed coordinate point. 3. The digital broadcast receiving apparatus according to claim 2, further comprising a third soft decision processing unit that performs processing when is near the Q axis of the positive region. 4. The positive area demapping means converts the second converted coordinate point to a third converted coordinate point near the I axis of the corresponding positive area when the second converted coordinate point is near the Q axis of the positive area. Symmetry point detection means, second soft decision processing means for performing processing when the second conversion coordinate point is near the I axis of the positive region and processing for the third conversion coordinate point, and the second soft decision processing means When the transformed coordinate point is in the vicinity of the Q axis of the positive region, the second soft decision processing means receives the output and the second
The digital broadcast receiving apparatus according to claim 2, further comprising: a data calculation unit that calculates data corresponding to a result of processing the converted coordinate point.