JP2003060502A - Control voltage generating circuit, pll circuit and clock synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control voltage generating circuit, a PLL circuit and a clock synchronizing circuit which are superior in following property and stability, with respect to sharp change of an input. SOLUTION: The control voltage generating circuit which forms a control voltage to be supplied to a voltage controlled oscillator is provided with at least a phase amount control unit for forming a pulse type control voltage whose width is controlled, and establishes the control as the amount of phase to an oscillation output from the voltage controlled oscillator. The PLL circuit employs the control voltage generating circuit. The clock synchronizing circuit employs the PLL circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control voltage generating circuit, a PLL circuit and a clock synchronizing circuit. INDUSTRIAL APPLICABILITY The present invention can be applied to, for example, a clock synchronization circuit with another device to which a PLL (Phase Locked Loop) circuit is applied in a device that performs digital data communication with another device, and in particular, a device having a PLL circuit. This is effective in the case of cascade connection of multiple stages.

[0002]

2. Description of the Related Art In digital data communication equipment, a PLL circuit is applied as a clock synchronizing circuit for synchronizing an internal clock of its own device with an external clock supplied from another device. For example, in the case of an electronic exchange, in order to synchronize with the clock of the network, a 64k + 8k clock is extracted from the network, INS (registered trademark) line, digital leased line, etc., and the communication clock in the electronic exchange is synchronously established with the extracted clock. Therefore, a PLL circuit is used.

FIG. 2 shows the basic structure of a PLL circuit. The PLL circuit 1 includes a phase comparator 2, a charge pump circuit (LPF) 3 and a VCO (voltage controlled oscillator) 4.

The phase comparator 2 inputs an input clock (input CL
K) and the phase difference between the output clock (output CLK), the charge pump circuit 3 forms a control voltage according to this phase difference and supplies it to the VCO 4, and the VCO 4 outputs an output clock having a frequency according to the control voltage. The output clock is formed and fed back to the phase comparator 2 to obtain an output clock synchronized with the input clock.

Here, according to the information from the phase comparator 2, the charge pump circuit 3 sends to the VCO 4 when the phase of its own device clock (output clock) is delayed with respect to the external clock (input clock). The control voltage is increased to increase the frequency, and conversely, when the phase of the own device clock leads the external clock, the control voltage to the VCO 4 is decreased to decrease the frequency. That is, in the past, it was a method of controlling the frequency by the phase difference.

[0006]

When the frequency is controlled by the phase difference, there is a problem that phase overshoot occurs. Further, there is a problem that the cascade connection becomes more difficult as the number of stages of the PLL circuit 1 increases due to the excessive phase.

Regarding the mechanism of generating the overshooting amount, consider the case where the frequency of the external clock input to the PLL circuit 1 rises stepwise as shown in FIG.

That is, consider the case where the frequency of the external clock increases stepwise at time A from the state where the internal clock is synchronized with the external clock. At this time, since the external clock has a higher frequency than the internal clock, the phase of the external clock gradually advances with respect to the internal clock. Due to the occurrence of the phase difference, the control voltage from the charge pump circuit 3 rises to raise the frequency of the internal clock.

Due to the rise of the frequency of the internal clock, at time B, the frequency of the internal clock matches the frequency of the external clock. At this stage, however, the phase of the external clock has advanced by the phase difference that has already occurred. The pump circuit 3 further functions to raise the frequency of the internal clock.

At time C, when the phase of the internal clock catches up with the phase of the external clock, the phase difference becomes 0.
At this time, the frequency of the internal clock has become high, and this time, the external clock starts to lag the internal clock (here, an overshoot occurs).

As described above, in terms of frequency, the internal clock repeatedly overshoots and undershoots with respect to the constant frequency of the external clock, and the overshoot amount and the undershoot amount gradually decrease, and eventually, , The internal clock matches the external clock in both frequency and phase.

Here, when the PLL circuits 1 are connected in multiple stages, the phase fluctuation is amplified toward the subsequent stage due to the overshoot amount described above, and when the variable range of the VCO 4 is saturated, it becomes impossible to follow up at that point. , The operation of the system becomes unstable.

The phenomenon in which the frequency of the external clock rapidly changes as described above is caused by the jitter contained in the external clock, the system switching of the host device in the duplex system,
It can be easily generated by switching between external synchronization and self-propelling. In the case of switching the system of the host device, the phase changes stepwise. In this case, it is sufficient to consider after time B in FIG.

In addition to the occurrence of the phase difference, the above-mentioned frequency waviness phenomenon is caused by adding an element for bringing the frequency closer to the center (charge loss of the charge pump circuit 3, lowering the sensitivity of the phase comparator 2, etc.). Although it can be reduced to some extent, the basic performance of the PLL circuit 1 such as followability and stability is deteriorated, which makes balance difficult, and it is very difficult to perform optimization design in the conventional method.

Therefore, there is a demand for a control voltage generating circuit, a PLL circuit, and a clock synchronizing circuit which have good followability and stability even with a sudden change in input.

[0016]

In order to solve such a problem, the first aspect of the present invention is to control a pulse width in accordance with a phase control input in a control voltage generating circuit for forming a control voltage to be applied to a voltage controlled oscillator. It is characterized by including a phase amount control unit for forming a pulsed control voltage, and establishing control as a phase amount for the oscillation output from the voltage controlled oscillator.

A second aspect of the present invention is a P including at least a phase comparator, a control voltage generating circuit and a voltage controlled oscillator.
In the LL circuit, the control voltage generation circuit includes a phase amount control unit that forms a pulse-shaped control voltage having a pulse width controlled according to the phase difference output from the phase comparator.

Furthermore, a third aspect of the present invention is a clock synchronizing circuit using a PLL circuit for generating an internal clock synchronized with an external clock, wherein the PLL circuit has a second aspect.
The PLL circuit of the present invention is applied.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION (A) Embodiment An embodiment of a control voltage generating circuit, a PLL circuit and a clock synchronizing circuit according to the present invention will be described below with reference to the drawings.

(A-1) Configuration of the Embodiment The clock synchronization circuit of the embodiment is composed of the PLL circuit 10 having the configuration shown in FIG.

The PLL circuit 10 of the embodiment has a phase comparator 11, a control voltage generating circuit 12 and a VCO (voltage controlled oscillator) 13. Although omitted in FIG. 1, an external clock and an internal clock are input to the phase comparator 11, and the VCO 13 outputs the internal clock.

The phase comparator 11 has the falling edges (or the rising edges) of the external clock and the internal clock.
Of the pulse width according to the phase difference is used as the UP signal when the phase of the external clock is advanced, and D when the phase of the external clock is delayed.
The OWN signal is output in negative logic.

The control voltage generating circuit 12 includes a phase comparator 11
VCO1 based on the UP and DOWN signals from
It generates a control voltage to be given to No. 3. Although the control voltage generation circuit 12 corresponds to a conventional charge pump circuit, in addition to the charge pump circuit configuration (phase-frequency control circuit unit 12A described later), other circuit units (phase-phase described later) are used. Since it has the control circuit section 12B), it will be referred to as a "control voltage generating circuit" as described above.

The VCO 13 oscillates and outputs an internal clock having a frequency corresponding to the control voltage input from the control voltage generation circuit 12. In this embodiment, the higher the control voltage, the higher the frequency of the internal clock. Is output.

This embodiment is characterized by the control voltage generating circuit 12 provided between the phase comparator 11 and the VCO 13.

The control voltage generating circuit 12 has a phase-frequency control circuit section 12A, a phase-phase control circuit section 12B and a resistor R1. The resistor R1 can be viewed as an element of the phase-frequency control circuit unit 12A and can be viewed as an element of the phase-phase control circuit unit 12B.

The phase-frequency control circuit section 12A is a circuit intended to control the frequency of the internal clock based on the phase difference between the external clock and the internal clock, as in the conventional case (of the conventional charge pump circuit). Corresponds to function;
The specific structure is the original according to the invention).

The phase-frequency control circuit section 12A includes two input buffers 30 and 31, and a charge control section 3.
2. It has an impedance conversion unit 33 and a charge drop correction unit 34.

One input buffer 30 inverts and amplifies the UP signal, captures the UP signal, and supplies it to the charge control section 32. The other input buffer 31 receives the DOWN signal.
The charge control unit 32 amplifies and captures the signal
To give to. The output stage inside the input buffer 31 is configured to allow the discharge current from the charge control unit 32 to flow to the ground.

The charge control unit 32 is connected to the VCO 1
The control voltage to 3 is formed and held.

The charge control section 32 is, for example,
A capacitor C1 for holding the control voltage, a diode D1 and a resistor R for charging the capacitor C1 during the high level period of the inverted UP signal from the input buffer 30.
2 and a diode D2 and a resistor R3 for discharging the capacitor C1 in the low level period of the DOWN signal from the input buffer 31. Note that the charging time constant is R2 × C1, the discharging time constant is R3 × C1, and it is preferable that the time constants are the same for charging and discharging by aligning the resistance values of the resistors R2 and R3.

The impedance converter 33 performs impedance conversion in order to transmit the voltage held by the capacitor C1 to the VCO 13 side while varying the voltage held as much as possible.

The impedance converter 33 includes a first amplification stage composed of an NPN transistor Q1 and a resistor R4, and a PN
It is a cascade connection with a second amplification stage consisting of a P-transistor Q2 and a resistor R5, and its output terminal is connected via a resistor R1.
It is connected to the input terminal of the VCO 13.

The charge loss correction unit 34 includes a capacitor C.
This is to compensate for a voltage drop due to charge loss (charge loss) due to discharge other than during control from 1. That is, while neither the UP signal nor the DOWN signal is being output from the phase comparator 11 (both are high levels), the input side is a diode that cannot flow backward, and the output side has a high impedance due to the impedance converter 33. Therefore, the electric charge accumulated in the capacitor C1 (hence, the VCO control voltage) is held, but even if the impedance conversion unit 33 is used, the electric charge slightly flows out from the capacitor C1. 34 are provided.

The charge drop correction unit 34 has an NPN transistor Q3 whose collector and base are connected to the power supply voltage.
And a constant R6 whose one end is connected to the emitter of the transistor Q3 and whose other end is connected to one end of the capacitor C1. Has been done.

The most significant feature of this embodiment is that the control voltage generating circuit 12 includes a phase-phase control circuit section 12B.

The phase-phase control circuit section 12B includes a ternary value generation section 40, a DC (direct current) cut capacitor C2 and a resistor R.
Have 7.

The ternary value generation unit 40 includes an HC 244 (a logic IC applied as a bus buffer;
44 circuit) 41, AND circuit 42, two resistors R
8 and R9.

The DOWN signal from the phase comparator 11 (here, both high level and low level are significant) is input to the input terminal A of the HC244 circuit 41, and the HC244 circuit 41 is connected to the gate terminal G thereof. When a significant level (low level) is input, the logic level to the input terminal A is passed and sent from the output terminal Y, and when a non-significant level (high level) is input to the gate terminal G, The output terminal Y is set to high impedance.

The AND circuit 42 receives the UP signal and the DOWN signal (here, the low level has meaning) from the phase comparator 11, and the AND circuit 42 calculates the logical product of the UP signal and the DOWN signal. HC2
44 to the gate terminal G of the active row of the circuit 41.

The resistors R8 and R9 are connected in series between the power supply voltage and the ground, and the connection point of these resistors R8 and R9 is connected to the output terminal Y of the HC244 circuit 41. That is, the resistor R8 is a pull-up resistor and the resistor R9 is a pull-down resistor.

The connection point of the resistors R8 and R9 is connected to the input terminal of the VCO 13 via the DC cut capacitor C2, and the connection point of the resistors R8 and R9 is connected to the input terminal of the VCO 13 via the resistor R7. ing. That is, the DC cut capacitor C2 and the resistor R7 are connected in parallel.

The DC cut capacitor C2 is HC244
The DC component of the pulse output (voltage) output by the circuit 41 is cut and applied to the input terminal of the VCO 13.

The resistor R7, together with the resistor R1 described above, limits the dependence of the input control voltage to the VCO 13 on the phase-frequency control circuit section 12A, as will be described later.

(A-2) Operation of Embodiment Next, operations of the control voltage generating circuit, the PLL circuit and the clock synchronizing circuit of the embodiment will be described.

In the phase comparator 11, the external clock and the timing of each falling edge of the internal clock output from the VCO 13 are compared, and when the phase of the external clock is advanced, a phase difference is found in the UP signal. A signal (low level) having a pulse width corresponding to the pulse width is formed, and when the phase of the external clock is delayed, a signal (low level) having a pulse width corresponding to the phase difference is formed in the DOWN signal. If so, UP signal and DO
Both WN signals maintain a non-significant logic level (high level).

The UP signal and D having the logic level according to the phase difference between the external clock and the internal clock as described above.
The control voltage generation circuit 12, which is supplied with the OWN signal, operates as follows.

The operation of the control voltage generating circuit 12 will be described below in the order of the operation of the phase-frequency control circuit section 12A and the operation of the phase-phase control circuit section 12B.

In the phase-frequency control circuit section 12A,
When a significant UP signal (low level pulse) is output from the phase comparator 11, the significant level (low level) pulse is inverted by the inversion buffer 30, so that the diode D1 and the resistor in the charge control section 32 are inverted. Electric charges are injected (charged) into the capacitor C1 via R2, and the control voltage to the VCO 13 is increased.

On the other hand, the significant DOWN from the phase comparator 11
When the signal (low level pulse) is output,
Significant level (low level) pulse is non-inverting buffer 3
1, the charge stored in the capacitor C1 passes through the resistor R3 and the diode D2 and the non-inverting buffer 3
1 (discharged), the control voltage to the VCO 13 is lowered.

During a period in which neither the significant UP signal nor the DOWN signal (low level pulse) is output from the phase comparator 11, the reverse current blocking function of each of the diodes D1 and D2 charges the capacitor C1 based on the UP signal. Also D
The capacitor C1 is not discharged based on the OWN signal, and the impedance conversion unit 33 causes the VCO
Since the 13 side has high impedance, the capacitor C1
The electric charge accumulated in the VCO 13 is retained, and the control voltage to the VCO 13 is also retained.

Even when the impedance conversion section 33 is used, a small amount of electric charge flows out from the capacitor C1, and the charge omission correction section 34 compensates for this outflow.

Next, the operation of the phase-phase control circuit section 12B in the control voltage generation circuit 12 will be described.

The phase-phase control circuit section 12B outputs three states of a high level pulse, a low level pulse, and a DC center potential in accordance with the signal from the phase comparator 11 as follows.

When a significant UP signal (low level pulse) is output from the phase comparator 11, the output level of the AND circuit 42 also becomes low level (pulse), and H
Since it is applied to the active-low gate terminal G of the C244 circuit 41, the logical level (high level: +5 V) of the DOWN signal input to the input terminal A of the HC244 circuit 41 during the pulse period is the HC244 circuit 41.
Is output from the output terminal Y. That is, when the UP signal is a low level pulse (the DOWN signal is high level in this period), the HC 244 circuit 41 outputs a high level pulse having a pulse width equal to the pulse width. Such a voltage change (high level pulse) is
The control voltage transmitted to the VCO 13 side through the C-cut capacitor C2 becomes a value obtained by adding the high level pulse from the phase-phase control circuit unit 12B to the DC potential output from the phase-frequency control circuit unit 12A. .

Further, the significant DOWN from the phase comparator 11
When a signal (low level pulse) is being output,
The output level of the AND circuit 42 also becomes a low level (pulse) and is applied to the gate terminal G of the active row of the HC 244 circuit 41, so during the pulse period, H
DOW input to the input terminal A of the C244 circuit 41
The logical level (low level: 0 V) of the N signal is HC244.
It is output from the output terminal Y of the circuit 41. That is, DO
When the WN signal is a low level pulse, the HC 244 circuit 41 outputs a low level pulse having a pulse width equal to the pulse width. Such a voltage change (low level pulse) is transmitted to the VCO 13 side through the DC cut capacitor C2, and the control voltage to the VCO 13 is
It is a value obtained by subtracting the low level pulse from the phase-phase control circuit unit 12B from the DC potential output from the phase-frequency control circuit unit 12A.

The significant UP signal from the phase comparator 11 is also D
When the OWN signal is not output (both the UP signal and the DOWN signal have a high logic level), AND
The output level of the circuit 42 becomes high level, and the HC 24
Since it is given to the active-low gate terminal G of the four circuits 41, the output of the HC244 circuit 41 becomes high impedance. As a result, the control voltage to the VCO 13 is the output voltage from the phase-frequency control circuit unit 12A is the resistance R
1, the resistor R7, and the value divided by the pull-up / down resistors R8 and R9 of the three-value generation unit 40.

Here, the phase-frequency control circuit section 12A has a characteristic of holding the control voltage, whereas the phase-phase control circuit section 12B has a characteristic of changing the output voltage in a pulse form.

The control voltage to the VCO 13 is the output of the phase-frequency control circuit section 12A and the phase-frequency control circuit section 12B.
However, the resistors R1 and R7 that divide the output of the phase-frequency control circuit unit 12A limit the dependence on the phase-frequency control circuit unit 12A. That is, both of the phase-frequency control circuit unit 12A and the phase-phase control circuit unit 12B act in the vicinity of the center (about 2 to 3 V) in the range of fluctuation of the control voltage to the VCO 13 (for example, 0 to 5 V), For the other fluctuation ranges, only the phase-phase control circuit unit 12B operates.

The control voltage generated by the control voltage generating circuit 12 as described above is given to the VCO 13, and the VCO 13
Oscillates a frequency according to the input control voltage,
Output as internal clock. The VCO 13 outputs an internal clock having a higher frequency as the control voltage is higher.

(A-3) Effects of the Embodiment Consider the case where the frequency of the external clock input to the PLL circuit 10 of the above embodiment rises stepwise as shown in FIG. This frequency change of the external clock corresponds to FIG. 3 described in the section of the problem to be solved by the invention.

In the case of only the conventional method of holding the frequency, if there is a difference between the frequencies of the external clock and the internal clock when the phase catches up (time C in FIG. 3), it causes the overshoot amount. It becomes a factor to occur.

On the other hand, in the method in which the frequency is changed in a pulse shape without being held, the phase is caught up (see FIG. 4).
At time b), the control voltage immediately becomes the central voltage (VCO
Returns to the control voltage when the center frequency is generated,
There is no overshoot. Further, when the phase difference occurs, the initial movement of the control of the VCO 13 is very fast, so that the phase difference with the external clock can be prevented from expanding. That is, the phase following property can be significantly improved.

However, only by the method of changing the control voltage in pulse form, it is necessary to constantly control the VCO 13 when the center frequency of the VCO 13 and the frequency of the external clock are different, and the output frequency is not stable. for that reason,
In this embodiment, as described above, both the method of holding the frequency and the method of changing the pulse shape without holding the frequency are used together.

As a result, the amplification of the jitter to the PLL circuit in the subsequent stage is suppressed within the control range (about 2 to 3 V) depending on the phase-frequency control circuit section 12A, and the VCO can be connected in any number of cascaded PLL circuits. There is no saturation from the variable range of.

As described above, according to the above-described embodiment, it is possible to significantly improve the followability while maintaining the stability of the output under normal conditions and solve the conventional problems.

Further, by adopting the configuration of the embodiment, the phase-frequency control circuit section 12A may be designed only in the direction of "fast charge control and minimum charge loss", and balance is taken into consideration. Since it is not necessary to do so, the design becomes easier than the conventional method.

Further, the impedance converter 3 having a grounded collector circuit is provided at the subsequent stage of the charge controller 32.
Since 3 is provided, the ability to hold the oscillation frequency can be improved.

Furthermore, the phase-phase control circuit section 12B
Uses the HC 244 circuit 41, the configuration is simple.

(B) Usage form PLL circuit 1 of the above embodiment as a clock synchronization circuit
0 is, for example, a multi-cabinet P as shown in FIG.
It can be used for the BX device 50.

In FIG. 5, a clock supply device (DC
S) The clock from 51 is a multi-cabinet PBX.
.., 10-61, 10-62 in each cabinet CAB1, ..., CAB6 of the device 50, and the PLL circuit 10-7 of the remote accommodating device 53 accommodating the terminal 52 is transmitted. Reach up to. Each of the PLL circuits 10-1, ..., 10-61, 10-62, 10-7 forms an internal clock synchronized with the input clock, and the PLL circuits 10-1, ..., 10-6 other than the final stage are formed.
1, 10-62 transmit the internal clock formed in the next stage.

[0072]

As described above, according to the present invention, it is possible to realize a control voltage generation circuit, a PLL circuit, and a clock synchronization circuit which have good followability and stability even with a sudden change in input.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main configuration of a PLL circuit according to an embodiment.

FIG. 2 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 3 is an explanatory diagram of a conventional problem.

FIG. 4 is an explanatory diagram of an effect of the PLL circuit of the embodiment.

FIG. 5 is a block diagram showing an example of a device to which the PLL circuit of the embodiment is applied.

[Explanation of symbols]

10 ... PLL circuit, 11 ... Phase comparator, 12 ... Control voltage generating circuit, 12A ... Phase-frequency control circuit section (frequency control section), 12B ... Phase-phase control circuit section (phase amount control section), 13 ... VCO (Voltage controlled oscillator), 30, 31 ...
Buffer, 32 ... Charge control section, 33 ... Impedance conversion section, 34 ... Charge drop correction section, 40 ...
Three-value generator, 41 ... HC244 circuit, R1, R7 ... Resistor, C2 ... DC cut capacitor.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5J106 AA04 BB02 CC01 CC21 CC41                       DD01 DD32 JJ04 KK02 KK18                       LL04

Claims (6)

[Claims] 1. A control voltage generation circuit for forming a control voltage to be applied to a voltage controlled oscillator, comprising: a phase amount control section for forming a pulse-shaped control voltage having a pulse width controlled according to a phase control input. A control voltage generation circuit characterized by establishing control as a phase amount for an oscillation output from a controlled oscillator. 2. A PLL circuit comprising at least a phase comparator, a control voltage generation circuit and a voltage controlled oscillator, wherein the control voltage generation circuit has a pulse width controlled according to a phase difference output from the phase comparator. A PL including a phase amount control unit that forms a pulsed control voltage.
L circuit. 3. The phase amount control section includes a ternary value generation section using an integrated circuit having a tri-state output, which outputs a ternary value in accordance with a phase difference output from the phase comparator. The PLL circuit according to claim 2. 4. The frequency control unit, wherein the control voltage generation circuit forms a direct current control voltage according to the phase difference output from the phase comparator, the control voltage from the phase amount control unit, and the frequency. The PLL circuit according to claim 2, further comprising a combining unit that combines the control voltage from the control unit. 5. The frequency control unit includes a charge control unit that controls a charge amount according to a phase difference output from the phase comparator, and an impedance conversion unit that is provided at a subsequent stage and has a high input impedance. The PLL circuit according to claim 4, characterized in that: 6. A clock synchronizing circuit using a PLL circuit for generating an internal clock synchronized with an external clock, wherein the PLL circuit according to any one of claims 2 to 5 is applied. Characteristic clock synchronization circuit.