JP2003060464A - Flat group delay low-pass filter and optical signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flat group delay low-pass filter, capable of eliminating the need for insertion, before and after a filter on a circuit, a fixed attenuator for suppressing the effect of reflections due to impedance mismatching between the filter and other components connected before and after the filter and having reduced manufacturing costs and components costs, and to provide an optical signal receiver provided with the same. SOLUTION: Inductors L1 , L2 set as series elements, resistors R1 , R2 set as shunting elements, capacitors C1 , C2 and inductors L'1 , L'2 are each formed of an electrode and a resistor film between paths S1 and S2 on a circuit chip substrate 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a group delay flat type low-pass filter that attenuates out-of-band noise without degrading a signal waveform by a flat group delay characteristic, and an optical signal receiving apparatus including the same.

[0002]

2. Description of the Related Art A Bessel low-pass filter can be used as a filter for removing a noise component and improving an error rate in, for example, digital communication using an optical fiber.

A Bessel low-pass filter is a ladder type circuit in which an inductor is a series element and a capacitor whose one end is grounded is a shunt element. These elements have a transfer function such that the argument argT of the transfer function T (jω) is approximately proportional to the frequency in order to flatten the group delay characteristic. When the number of stages of this filter is determined, the value of the circuit element is uniquely determined. The value of each element is, for example,
It can be easily calculated by using the normalization parameter of the reference low pass filter described in "Handbook of FILTER SYNTHESIS" by AIZverev.

FIG. 10 shows the circuit configuration of a 4-stage Bessel low-pass filter, and FIG. 11 shows its pass characteristic, reflection characteristic and group delay characteristic. In FIG. 10, L
₁ and L ₂ are inductors as series elements, and C ₁ and C
₂ is a capacitor as a shunt element. In FIG. 11A, S11 is a reflection characteristic and S21 is a passage characteristic. In this example, the cutoff frequency (the amount of passage is 3 dB
Attenuating frequency) is 7.5 GHz. Since the filter has a flat group delay characteristic as shown in FIG. 11B, it is possible to suppress signal distortion in a wideband signal and remove harmonic noise.

However, the filter shown in FIG. 10 has a poor reflection characteristic, and waviness due to multiple reflection occurs in the transmission characteristic due to a mismatch with front and rear parts. Conventionally, in order to improve its reflection characteristic, fixed attenuators (attenuators) have been inserted before and after the filter.

[0006]

[Problems to be Solved by the Invention]
It is inevitable to insert a fixed attenuator for impedance matching.
Is not only transmission loss, but also uneconomical
There was a problem. Therefore, in Japanese Patent Laid-Open No. 9-270655,
In order to improve the reflection characteristics, the inductor and resistor are connected in parallel.
A correction circuit in which a path and a capacitor are connected in series
The circuit used for the shunt element of the low-pass filter is shown.
Has been. FIG. 12 shows the filter shown in the above publication.
It is a figure which shows an internal structure. In FIG. 12, R₁~ R _Four
Is a resistance element, C₁~ C_FourIs a capacitor, L₁'~ L_Four′
Is an inductor. Also, L₁~ L₃Is a metal ribbon
It is an inductor consisting of. On the metal conductor plate 4,
Inductor L₁, L₂, L₃Relay
For this purpose, the insulating relay stand 5, 6, 7, 8 is fixed by adhesion.
It

However, in the filter having the configuration shown in FIG. 12, the inductance component also varies according to the variation in the length of the wire connecting the resistance elements R _{1 to} R ₄ and other components, and the filter group The delay characteristics change greatly. Therefore, there is a problem that the adjustment of the characteristics becomes necessary and the manufacturing cost increases. Further, since the individual components are individually mounted in the metal housing, there is a problem that the size of the entire filter is increased. Also,
For the shunt element, it is necessary to use an inductor having a larger inductance value than the series element, such as a spiral inductor. Such an inductor is more expensive than a capacitor or a resistance element and causes a cost increase.

An object of the present invention is to eliminate the need for inserting fixed attenuators before and after the filter in order to suppress the influence of reflection due to impedance mismatch with other parts connected before and after the filter in the circuit. Another object of the present invention is to provide a group delay flat type low-pass filter in which the manufacturing cost and the component cost are reduced, and an optical signal receiving device including the same.

[0009]

SUMMARY OF THE INVENTION The present invention is directed to a group delay flat type low-pass filter including a low-pass filter circuit including a series element connected in series between an input terminal and an output terminal and a shunt element whose one end is grounded. In the filter, the inductor as the series element is composed of the electrodes on the substrate, and the resistance as a part of the shunt element is composed of the resistive film pattern on the substrate.

Thus, by eliminating the wire for connecting the resistance element, the characteristic variation due to the variation in the length of the wire is eliminated, and the characteristic adjustment is not required and the manufacturing cost is reduced.

Further, according to the present invention, a delay equalizer composed of an inductor and a capacitor for changing the phase characteristic without changing the amplitude characteristic is provided at the front stage or the rear stage of the filter circuit, and the inductor of the delay equalizer is provided. And the capacitor is composed of electrodes on the substrate. This widens the frequency range in which the group delay becomes flat.

The present invention also relates to a photoelectric conversion circuit for receiving an optical signal and converting it into an electric signal, and the group delay flat type for inputting the electric signal converted by the photoelectric conversion circuit to attenuate unnecessary signal components. An optical signal receiving device is composed of the low-pass filter. This reduces out-of-band noise without degrading the signal waveform in digital communication or the like using an optical fiber.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The configuration of a group delay flat type low-pass filter according to the first embodiment will be described with reference to FIGS. FIG. 1 is a diagram showing a circuit pattern formed on a substrate. In FIG. 1, reference numeral 10 denotes a dielectric circuit chip substrate, on the upper surface of which two signal input / output lines S ₁ ,
S _2, and to form an inductor electrode L _1, L ₂ of the series element to its two lines S _1, S between _2. Further, inductor electrodes L ₁ ′ and L ₂ ′ as shunt elements, capacitor electrodes C ₁ and C ₂ and resistance films R ₁ and R ₂ are formed, respectively. The inductor electrodes L ₁ and L ₂ form a microstrip line together with the ground electrode formed on substantially the entire lower surface of the circuit chip substrate 10. If the characteristic impedance of this microstrip line is Za, the electrical angle is θ, and the inductor as a series element is L, then the following relationship holds.

Za · sin θ = ωL The inductor electrodes L ₁ ′ and L ₂ ′ also form a microstrip line together with the ground electrode on the lower surface. However, the inductor electrodes L ₁ ′ and L ₂ ′ are formed in a rectangular spiral shape as shown in the figure, and the outer peripheral end of the inductor electrode L ₁ ′ is connected to the inductor electrode patterns L ₁ and L ₂ . It is connected to a point (boundary). Further, the outer peripheral end of the inductor L ₂ ′ is connected near the output side line S ₂ . These inductor electrodes L ₁ ′,
The inner peripheral end of L ₂ ′ is connected to the capacitor electrodes C ₁ and C ₂ via lead lines Line 3 and Line 4. The lead lines Lines 3 and 4 and the inductor electrode L ₁ ′,
L ₂ ′ is insulated via an insulating layer such as SiO ₂ . The ends of the lines S ₁ and S ₂ are used as pads for wire connection to pads on other substrates.

As the circuit chip substrate 10, a sintered ceramic single layer substrate, a sintered ceramic multilayer substrate, a resin substrate or the like is used. The electrode pattern and the resistive film pattern are formed by a thick film process or a thin film process.

In the case of the thick film process, an electrode material such as Ag or a resistance material such as ruthenium oxide is pasted into a pattern by screen printing and then fired to form an electrode pattern or a resistance film pattern. In the case of thin film process, by vapor deposition, sputtering, or plating,
After forming an electrode material such as Ag and a resistance material such as tantalum oxide or nichrome over the entire surface, a resist is formed by a photolithography process and an unnecessary metal film is removed by etching. Alternatively, after a resist film pattern is formed by a photolithography process, an electrode material or a resistance material is deposited on a portion other than the resist film pattern by vapor deposition, sputtering, plating or the like, and finally the resist film is peeled off. Form a pattern. According to this thin film process, the variation in the position of each component is 10 μm or less, so that the variation in the electrical characteristics of the filter can be suppressed to a very small level.

FIG. 2 is an equivalent circuit diagram of the group delay flat type low-pass filter shown in FIG. In this way, a 4-stage group delay flat type low-pass filter is formed on the circuit chip substrate 10 which is a single dielectric substrate.

The capacitor electrode C₁, C₂Is a figure
Not only the shape as shown in 1, but a triangle that fills a predetermined area
It may be shaped, circular, fan-shaped or rhombic. Also, this
On the dielectric substrate as a shunt element of
Lower electrode / SiO₂, T₂O _FiveDielectric layer / upper
MIM (Metal Insulator Metal) that has a three-layer structure of electrodes
 ) A capacitor may be used. In addition,
Kuta electrode L₁′, L₂′ Is not limited to spiral shape,
It may have a meander line shape or a straight shape.

As described above, by forming the resistance element, the inductor, and the capacitor on the same substrate by patterning, the characteristic variation is smaller than that in the case where the individual parts are connected by the ribbon or the wire, and therefore the characteristic adjustment can be performed. It becomes unnecessary and the defect rate can be reduced. further,
Since the main part of the filter is formed on one substrate, the size can be reduced as a whole.

Next, the group delay flat type according to the second embodiment
The structure of the low-pass filter will be described with reference to FIG. Figure
3 is a flat group delay type with the cap 16 removed.
FIG. 3 is an exploded perspective view of a high-pass filter. In this example, the circuit
A capacitor electrode C is formed on the upper surface of the chip substrate 10. ₁, C₂,
Resistive film R₁, R₂, Inductor electrode L₁, L₂and
Railroad S₁, S ₂Are formed respectively. This track
S₁, S₂Sets its characteristic impedance to 50Ω
There is. On the lower surface of the circuit chip substrate 10, the entire ground electrode is provided.
Is forming. These configurations are the same as those shown in FIG.
It is like. The circuit chip substrate 10 will be described later.
The correction line and the capacitor electrode Cw are formed.
It

Reference numeral 11 denotes a package substrate which can be surface-mounted on the mounting substrate, and the circuit chip substrate 10 is mounted on the upper surface thereof. The package substrate 11 includes a ground electrode 12, a ground terminal 13, an input terminal 14, and an output terminal 1.
5 are formed respectively. The ground electrode formed on the lower surface of the circuit chip substrate 10 is electrically connected to the ground electrode 12 on the upper surface of the package substrate 11. Input / output pads P insulated from the ground electrode 12 are formed on the upper surface of the package substrate 11.
Between the ends of the lines S ₁ and S ₂ , as shown in FIG.
Connected with a wire W of books. A metal ribbon may be used instead of such a wire.

In FIG. 3, 16 is a metal cap. The cap 16 covers the circuit chip substrate 10 and the entire wire W portion so as to cover the package substrate 1
It is electrically and mechanically joined to the ground electrode 12 on the upper part of 1 by soldering. With this structure, the circuit portion of the filter is shielded by the cap 16 and the ground electrode 12 formed on the package substrate 11, and the circuit chip substrate 10
Radiation of electromagnetic waves from the surface is prevented to prevent deterioration of attenuation characteristics.

The lines S ₁ and S of the circuit chip substrate 10 are
A through hole having a conductor film formed on the inner surface may be provided at the end of _{2 and} the lines S ₁ and S ₂ may be connected to the pad P formed on the upper surface of the package substrate 11 on the lower surface of the circuit chip substrate 10. Further, electrodes extending from the lines S ₁ and S ₂ shown in FIG. 3 may be formed on the side surface of the circuit chip substrate 10 and connected to the pads P on the package substrate 11.
Similarly, a castellation cut out in a semicircular shape is provided on the side surface of the circuit chip substrate 10, and the line on the circuit chip substrate is connected to the pad P on the package substrate via the side surface electrode provided on the inner surface thereof. You may do it. The two pads P on the package substrate 11 are electrically connected to the input terminal 14 and the output terminal 15, respectively.

FIG. 4A is a diagram showing an electrode pattern of a main part of the group delay flat type low-pass filter shown in FIG.
(B) is an equivalent circuit diagram thereof. In (A), Cw is a capacitor electrode for generating a correction capacitance between the ground electrode and the lower surface of the circuit chip substrate 10. In (B), this correction capacity is represented as Cw. Also,
In (A), Sw is a correction line, and lines S ₁ , S
_At the end of ₂ , the characteristic impedance of the line is lowered.

In FIG. 4B, Lw1 is the inductance component of the wire W that connects between the correction line Sw and the pad P, and Lw2 is the inductance of the wire W that connects the correction capacitance electrode Cw and the pad P. It is an ingredient. Although FIG. 4 shows the input side of the filter,
The output side is also similarly configured.

As described above, by connecting the correction capacitance Cw to the shunt, and by generating a capacitance component between the low impedance correction line Sw and the ground, the capacitance component of the correction line Sw and Lw.
1, Lw2, Cw form a π-type low-pass filter. As a result, the position where the reflection characteristic is good is shifted to the low frequency side, and the reflection characteristic in the used frequency band can be improved.

Even when the correction line Sw does not exist, a structure in which a low-pass filter composed of Lw1, Lw2, and Cw is inserted is formed, and the position where the reflection characteristic is good is shifted to the low frequency side, and the reflection characteristic in the used frequency band is improved. it can.

The correction line Sw has a larger capacity than the correction capacitance Cw.
Since the effect of improving the deterioration of the reflection characteristics due to the wire connection is small, it may not be necessarily formed depending on the required characteristics. If the inductance component of the wire W is small, the correction capacitance electrode Cw is also unnecessary.

Next, the configuration of the group delay flat type low-pass filter according to the third embodiment will be described with reference to FIGS. This flat group delay low-pass filter is a Bessel low-pass filter circuit to which a delay equalizer is added.

FIG. 5 is a circuit diagram of the delay equalizer. Here, Xa and Xb are reactances, and Xa and Xb are circuits in which the following relationship is established with the resistance R of the external circuit (generally, this resistance R is a pure resistance of 50Ω).

Xa.Xb = R ^{2 Since} this lattice type circuit cannot be realized by an unbalanced circuit such as a microstrip line, it is converted into an unbalanced circuit as shown in FIG. 5B.

FIG. 6 is an equivalent circuit diagram of the unbalanced circuit shown in FIG. 5B. As shown in FIG. 6A, Xa in FIG. 5 can be configured by a parallel circuit of an inductor La and a capacitor Ca, and Xb is an inductor Lb and a capacitor C.
b series circuit. This circuit is transformed into a symmetrical type as shown in FIG. 6 (B) or (C). In this example, series elements are connected in parallel with LC and shunt elements are connected with L
Although the configuration of C series connection is applied, it can be used as a delay equalizer as long as the above condition is satisfied.

FIG. 7 shows a group delay formed on a circuit chip substrate.
It is a figure which shows the structure of a flat type low-pass filter. In Figure 7
The inductor electrode L₁, L₂, Resistance film R₁, R
₂, Capacitor electrode C₁, C₂, Inductor electrode L
₁′, L₂′, And track S ₂The part is shown in Fig. 1.
It is almost the same as what was done. However, capacitor electrode C ₂
And inductor electrode L₂The pattern of'is shown in Fig. 1.
I made it inside out (mirror symmetry) pattern. this
Depending on the pattern, the capacitor electrode C₁And C₂Between
The gap is narrowed to prevent the overall size from increasing.

In FIG. 7, Ca is a capacitor electrode, and in this example, the capacitor is formed by comb-shaped electrode patterns facing each other. La is an inductor electrode and constitutes an inductor. Cb is an electrode for a capacitor, and forms a capacitor with the ground electrode on the lower surface. These Ca, La, and Cb constitute the delay equalizer shown in FIG. 6B or 6C as a lumped constant circuit.

One electrode end of the capacitor electrode Ca also serves as a pad for wire connection. In this example, a delay equalizer is provided before the low-pass filter, and one electrode end of Ca is used for input and the line S ₂ is used for output. Similarly, a delay equalizer may be provided after the low pass filter.

FIG. 8 is a diagram showing the group delay characteristics of the entire filter with and without the delay equalizer shown in FIG. As described above, in the case where the delay equalizer is not provided, the flat characteristic within 6 psec is up to 10 GHz.
Spreads up to 6 GHz, and flat group delay characteristics are obtained over a wide band. Moreover, even if the delay equalizer is provided, the pass characteristic and the reflection characteristic of the filter hardly change.

In each of the embodiments described above, an example is shown in which electrodes are formed on a single-layer circuit chip substrate to form a microstrip line. However, a multilayer substrate is used and strip lines are formed in the same manner. May be.

Next, the configuration of the optical signal receiving apparatus according to the fourth embodiment will be described with reference to FIG. FIG. 9 is a block diagram showing the circuit configuration of the optical signal receiving device. In FIG. 9, reference numeral 21 is a photodiode that receives an optical signal from the optical fiber. Reference numeral 22 is a preamplifier that amplifies the electric signal converted by the photodiode 21. Reference numeral 23 denotes a flat delay group type low-pass filter, which uses a filter having any one of the structures described above. This filter removes noise components such as harmonic components caused by long-distance transmission and signal amplification. The timing circuit 25 is
A sampling pulse is generated from the digital pulse pattern of the input signal and given to the discrimination circuit 24. Identification circuit 24
Is the equalized waveform "1", "0" based on the sampling pulse
Is performed and the original digital pulse pattern is reproduced.

Conventionally, in such an optical signal receiving device, a fixed attenuator for suppressing the influence of reflection was required before and after the low-pass filter 23. However, according to the present invention, the filter 23 itself is low. The fixed attenuator is not necessary because of its reflective property.

[0040]

According to the present invention, a group delay flat type low-pass filter including a low-pass filter circuit including a series element connected in series between an input terminal and an output terminal and a shunt element having one end grounded is provided. By configuring the inductor as the series element by the electrode on the substrate and the resistance as a part of the shunt element by the resistive film pattern on the substrate, the wire for connecting the resistive element becomes unnecessary, and the wire The characteristic variation due to the variation in the length of the
Manufacturing cost can be reduced.

Further, according to the present invention, a delay equalizer composed of an inductor and a capacitor, which changes the phase characteristic without changing the amplitude characteristic, is provided before or after the filter circuit, and the delay equalizer is provided. By configuring the inductor and the capacitor of (1) with the electrodes on the substrate, the frequency range in which the group delay becomes flat is expanded.

Further, according to the present invention, a photoelectric conversion circuit for receiving an optical signal and converting it into an electric signal, and the group delay for attenuating a harmonic component by inputting the electric signal converted by the photoelectric conversion circuit. By configuring the optical signal receiving device with the flat type low-pass filter, it is possible to reduce the out-of-band noise without degrading the signal waveform in digital communication using an optical fiber.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a group delay flat type low-pass filter according to a first embodiment.

FIG. 2 is an equivalent circuit diagram of the same group delay flat type low-pass filter.

FIG. 3 is an exploded perspective view of a flat group delay low-pass filter according to a second embodiment.

FIG. 4 is a diagram showing an electrode pattern of a main part and an equivalent circuit of the main part of the same group delay flat low-pass filter.

FIG. 5 is a circuit diagram of a delay equalizer used in a group delay flat type low-pass filter according to a third embodiment.

FIG. 6 is an equivalent circuit diagram of the delay equalizer.

FIG. 7 is a diagram showing the configuration of a group delay flat type low-pass filter according to a third embodiment.

FIG. 8 is a diagram showing group delay characteristics of the same filter compared with a case without a delay equalizer.

FIG. 9 is a block diagram showing a circuit configuration of an optical signal receiving device according to a fourth embodiment.

FIG. 10 is a circuit diagram of a conventional Bessel filter.

FIG. 11 is a diagram showing reflection characteristics, passage characteristics, and group delay characteristics of the filter.

FIG. 12 is a diagram showing a configuration of a conventional group delay flat type low-pass filter.

[Explanation of symbols]

1-input terminal 2-output terminal 3-filter case 4-Metal conductor plate 5-8-Relay stand 10-circuit chip substrate 11-Package substrate 12-ground electrode 13-Grounding terminal 14-input terminal 15-output terminal 16-cap R-resistance element or resistance film C, C'-capacitor or capacitor electrode Cw-correction capacitance or correction capacitance electrode L-inductor or inductor electrode Lw-inductance component S-rail W-wire P-pad

Claims (3)

[Claims] 1. A group delay flat low-pass filter including a low-pass filter circuit comprising a series element connected in series between an input terminal and an output terminal, and a shunt element having one end grounded, and an inductor as a series element. Is a flat-type low-pass filter of the group delay type in which a resistor as a part of a shunt element is constituted by a resistive film pattern on the substrate. 2. A front stage or a rear stage of the filter circuit,
The group according to claim 1, wherein a delay equalizer including an inductor and a capacitor, which changes the phase characteristic without changing the amplitude characteristic, is provided, and the inductor and the capacitor of the delay equalizer are configured by electrodes on the substrate. Flat delay type low-pass filter. 3. The photoelectric conversion circuit for receiving an optical signal and converting it into an electric signal, and the electric signal converted by the photoelectric conversion circuit as an input to attenuate unnecessary signal components. An optical signal receiving device including a flat delay type low-pass filter.