JP2003060203A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated gate field effect transistor using SiC, which is restrained from being reduced in mobility due to the influence of a gate insulating film/SiC interface and reduced in ON-state resistance. SOLUTION: An insulated gate field effect transistor is equipped with a P-type SiC substrate 11, a semiconductor region composed of an N-type SiC layer 12 which is provided in contact with the SiC substrate 11 to serve as an embedded channel and a P-type SiC layer 13 provided in contact with the SiC layer 12, a gate electrode 21 provided on the SiC layer 13 through the intermediary of a gate insulating film 17, and N-type source/drain regions 15 and 16 formed on the surface of the SiC substrate 11 so as to sandwich the gate electrode 21 between them. A current flowing between the source/drain regions 15 and 16 is controlled by controlling the carrier concentration of the SiC layer 12 with the potentials of the SiC substrate 11 and the gate electrode 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an insulated gate field effect transistor, and more particularly to an insulated gate field effect transistor using silicon carbide (SiC) as a semiconductor layer.

[0002]

2. Description of the Related Art Silicon carbide (Si
As a field effect transistor using C), a surface channel insulated gate field effect transistor is known.
SiC has a dielectric breakdown field strength 10 times that of silicon,
Moreover, since the crystal mobility is similar to that of silicon, the use of SiC makes it possible to manufacture a semiconductor element having a high breakdown voltage and a low resistance. However, the insulated gate field effect transistor is
When manufactured by C, the resistance of the bulk part can be lowered,
Since the mobility of carriers at the insulating film / SiC interface is orders of magnitude smaller than that of silicon, there is a problem that the channel resistance increases and the resistance of the entire device does not decrease.

In order to solve this problem, a layer having a conductivity type different from that of the substrate is formed in the semiconductor region adjacent to the insulated gate, and a channel is formed closer to the substrate side with respect to the interface between the insulating film and SiC. A channel insulated gate semiconductor device has been proposed (IEEE transactions on Electro
n devices vol. 41, No 7 1257-1264).

FIG. 4A is a cross-sectional view of a device structure of a typical buried channel insulated gate field effect transistor using SiC. 41 in the figure is a p-type SiC substrate, 4
2 is an n-type SiC buried layer (channel layer), 45 is an n-type SiC source region, 46 is an n-type SiC drain region, 4
7 is a gate insulating film, 51 is a gate electrode, 52 is a source electrode, and 53 is a drain electrode.

FIG. 4B is a diagram showing an impurity concentration distribution in a cross section taken along the line BB 'in FIG. 4A. By setting the thickness and concentration of the buried layer to appropriate values, the carrier concentration of the buried layer can be controlled by the electric field from the gate electrode, and a buried channel insulated gate field effect transistor can be manufactured. An enhancement type transistor can be manufactured by selecting a gate electrode having an appropriate work function.

In this insulated gate field effect transistor, when a voltage is applied to the gate electrode, a channel is formed not in the interface but in the substrate, so that it is possible to suppress the influence of mobility decrease at the insulating film / SiC interface. .
FIG. 4C shows a state in which a buried channel is formed in a band diagram of a channel portion of a typical buried channel insulated gate field effect transistor.

By the way, in the buried channel insulating gate type field effect transistor of this type, when the voltage of the gate electrode is increased in order to increase the carrier concentration of the channel, the carriers are gradually distributed to the side of the gate insulating film having a low mobility. Therefore, there is a problem that the mobility is rapidly reduced. FIG. 5 shows the relationship between the field effect mobility and the gate voltage of a buried channel insulated gate field effect transistor using SiC. The field effect mobility shows a very large value immediately after the buried channel is formed, but it rapidly decreases as a gate voltage is applied.

Further, the buried channel structure is likely to be a depletion type transistor in which a current flows even when the voltage applied to the gate electrode is 0V, and a device structure is required to form an enhancement type transistor in which the gate drive circuit can be simplified. However, there are problems such as being restricted and being difficult to manufacture.

[0009]

As described above, the conventional buried channel insulated gate field effect transistor has a problem that mobility is deteriorated due to the influence of the gate insulating film / SiC interface. In addition, the buried channel structure is likely to be a depletion type transistor, and there are problems that the device structure is limited and the manufacturing is difficult for an enhancement type transistor.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a mobility due to an influence of a gate insulating film / SiC interface in an insulated gate field effect transistor using SiC. Another object of the present invention is to provide a semiconductor device which suppresses the deterioration of the semiconductor device, has a low on-resistance, and is easy to manufacture an enhancement type transistor.

[0011]

(Structure) In order to solve the above problems, the present invention adopts the following structure.

That is, the present invention is directed to a first SiC of the first conductivity type.
Layer, a semiconductor of a second conductivity type second SiC layer provided in contact with the first SiC layer, and a semiconductor of a first conductivity type third SiC layer provided in contact with the second SiC layer A region, a gate electrode formed on the third SiC layer via a gate insulating film, and a second conductivity type source / drain region formed on the surface of the semiconductor region with the gate electrode interposed therebetween. A semiconductor device comprising: the first S
The current between the source / drain regions is controlled by controlling the carrier concentration of the second SiC layer by the potentials of the iC layer and the gate electrode.

Here, the following are preferred embodiments of the present invention.

(1) It is possible to deplete the second SiC layer by the potentials of the first SiC layer and the gate electrode.

(2) The second SiC layer is depleted while the potentials of the first SiC layer and the gate electrode are zero.

(3) The thickness of the third SiC layer is 30 nm or more.

(4) The first SiC layer is a SiC substrate,
The second and third SiC layers are each formed by ion implantation.

(Operation) According to the present invention, the third SiC layer having the same conductivity type as the first SiC layer (eg, SiC substrate) is replaced with the second SiC film having the second conductivity type serving as a buried channel.
By forming the layer on the gate insulating film side, the buried channel can be kept away from the gate insulating film / SiC interface, and deterioration of mobility in the buried channel can be suppressed. Further, it is possible to suppress the formation of a channel at the gate insulating film / SiC interface in which the mobility is drastically deteriorated when the gate voltage is applied, and it is possible to increase the threshold voltage. As a result, it is possible to realize an insulated gate field effect transistor with low mobility deterioration even when a large gate voltage is applied in the enhancement type.

Further, by setting the film thickness of the third SiC layer to 30 nm or more, the above effect can be surely obtained. This has been made clear by the inventors' earnest research and experiments.

The inventors of the present invention, in the course of proceeding with the trial research of a buried channel insulated gate field effect transistor using SiC, have mobility degradation of the gate insulating film / SiC interface in a region of about 30 nm from the surface. I found that. FIG. 6 is a diagram showing the relationship between the drain current and the gate voltage of a buried channel insulated gate field effect transistor using SiC. Drain voltage is 0.1
It was fixed at V. The solid line is the measured value, and the broken line is the result of device simulation assuming that the mobility deteriorates due to the effect of the interface in the region where the distance is 30 nm from the interface.

As can be seen from FIG. 6, the simulation result successfully reproduces the characteristic of the measured value that the slope of the drain current with respect to the gate voltage becomes smaller as the gate voltage is applied. That is, the mobility is a distance 3 from the interface.
It shows the validity of the hypothesis that degradation occurs due to the effect of the interface in the region of 0 nm. Furthermore, the inventors conducted further simulation analysis, and in the conventional buried channel insulated gate field effect transistor, carriers were distributed in the region where the mobility was deteriorated near the interface even when the buried channel was formed. , Gate insulation film / Si
It was found that the mobility was affected by the C interface.

Therefore, the thickness of the third SiC layer is 30 nm.
With the above settings, it is possible to more reliably suppress the deterioration of mobility in the buried channel.

[0023]

DETAILED DESCRIPTION OF THE INVENTION The details of the present invention will be described below with reference to the illustrated embodiments.

FIG. 1A is a sectional view showing an element structure of a buried channel insulated gate field effect transistor according to one embodiment of the present invention. FIG. 1B is the same as FIG.
It is an impurity concentration distribution diagram in the cross section along the AA 'line of (a).

An n-type SiC layer (second SiC layer) 1 as a buried channel layer is formed on a part of the surface of a p-type silicon carbide (SiC) substrate (first SiC layer) 11.
2 is formed on the p-type SiC layer (third SiC
Layer) 13 is formed. The impurity concentration of the p-type SiC substrate 11 is 1 × 10 ¹⁷ cm ⁻³ . The impurity concentration of the n-type SiC layer 12 is 1 × 10 ¹⁷ cm ⁻³ , and its film thickness is 20.
It is 0 nm. The impurity concentration of the p-type SiC layer 13 is 2 × 1
The film thickness is 0 ¹⁷ cm ^-3 and 50 nm. Note that Si
The C layers 12 and 13 were formed by multi-step ion implantation into the SiC substrate 11 and high temperature annealing after the ion implantation.

SiC substrate 1 with SiC layers 12 and 13 interposed therebetween
On the surface of No. 1, n-type Si to be source / drain regions
C layers 15 and 16 are formed. These source / drain regions are n-type like the SiC layers 12 and 13.
It was formed by multi-stage ion implantation of type impurities. further,
The junction depth in the source / drain regions 15 and 16 is 0.3 μm.

The gate insulating film 1 is formed on the p-type SiC layer 13.
7 are formed. The gate insulating film 17 has a thickness of 4
0 nm and formed by dry oxidation at 1200 ° C.,
After Ar annealing at 1200 ° C., reoxidation was performed in a wet atmosphere at 950 ° C. Then, the gate insulating film 1
7, a gate electrode 21 is formed, a source electrode 22 is formed on the SiC layer 15 serving as a source region, and a drain electrode 23 is formed on the SiC layer 16 serving as a drain region. Each of these electrodes was made of aluminum.

The buried channel insulated gate field effect transistor of this embodiment is different from the conventional buried channel insulated gate field effect transistor in that the p-type
That is, the type SiC layer 13 is present. FIG. 1C shows a band diagram in the state where the buried channel is formed. It can be seen that the channel is formed deeper in the substrate as compared with the conventional device shown in FIG. The carriers in the buried channel increase as the gate voltage is applied. However, unlike the conventional buried channel insulating gate field effect transistor, the carriers in the buried channel are separated from the gate insulating film / SiC interface and move by the interface. The effect of deterioration is small. Further, when the gate voltage is increased, an inversion layer is formed at the gate insulating film / SiC interface, but the voltage at which the inversion layer is formed shifts to the high voltage side as compared with the conventional structure.

FIG. 2 shows the relationship between the field effect mobility and the gate voltage of the buried channel insulated gate field effect transistor of this embodiment in comparison with the conventional example. The solid line shows the mobility of the transistor of this embodiment, and the broken line shows the mobility of the transistor of the related art. The mobility of this embodiment is larger than that of the conventional example.

FIG. 3 compares the relationship between the drain current and the gate voltage according to the present embodiment with the characteristics of the conventional buried channel insulated gate field effect transistor.
The drain voltage was fixed at 0.1V. The solid line shows the drain current characteristic of the transistor of this embodiment, and the broken line shows the drain current characteristic of the buried channel insulated gate field effect transistor according to the conventional technique. It can be seen that according to the present embodiment, the influence of mobility deterioration is suppressed up to the region where the gate voltage is high, the current value at the same gate voltage is increased, and the on-resistance is reduced.

Here, in the characteristic shown in FIG. 3, the slope of the line showing the drain current characteristic is the mobility, and it is understood that the mobility of this embodiment is less deteriorated up to a higher gate voltage than the conventional example. . In addition, in the insulated gate field effect transistor of this embodiment, the mobility of the inversion layer was 200 cm ² / Vs.

As described above, according to this embodiment, the n-type SiC layer 12 as the buried channel and the gate insulating film 17 are formed.
And p-type SiC having a conductivity type opposite to that of the buried channel.
By sandwiching the layer 13, it becomes possible to improve the mobility of the channel and significantly reduce the series resistance component thereof. As a result, the low loss characteristic originally possessed by the element using SiC has come to be utilized.

Also, n-type Si as a buried channel
A p-type SiC layer 13 is provided between the C layer 12 and the gate insulating film 17.
By sandwiching the two, it becomes easy to raise the threshold value of the gate voltage, and it becomes easy to design an enhancement type transistor which can simplify the gate drive circuit. This makes a great contribution to the development and popularization of SiC insulated gate field effect semiconductor devices, especially for power.

The present invention is not limited to the above embodiment. In the embodiments, the most basic lateral insulated gate field effect transistor has been described, but the present invention is not limited to the lateral insulated gate field effect transistor, but may be a vertical insulated gate field effect transistor or an insulated gate bipolar transistor. Needless to say, the present invention can be applied to (IGBT), and further to power semiconductor elements such as MOS thyristors.

Further, the thickness of the third SiC layer is not limited to 50 nm, and the thickness of the gate insulating film / S is not limited by the layer.
It may be appropriately set within a range in which the decrease in mobility at the iC interface can be sufficiently suppressed, and is generally set to 30 nm or more. However, if it is too thick, the control by the gate electrode becomes difficult, and therefore it is generally desirable that the thickness is about 100 nm or less.

The first SiC layer is not necessarily limited to the substrate but may be a layer formed on the substrate. Furthermore, the method for forming the second and third SiC layers and the source / drain regions is not necessarily limited to the multi-stage ion implantation, but can be changed appropriately according to the specifications. Further, in the embodiment, the first and third SiC layers are p-type and the second SiC layer is n-type, but these relationships may be reversed. In addition, various modifications can be made without departing from the scope of the present invention.

[0037]

As described above in detail, according to the present invention, a third SiC layer having a conductivity type opposite to that of the second SiC is provided between the second SiC layer which becomes the buried channel and the gate insulating film. By forming it, deterioration of mobility due to the influence of the gate insulating film / SiC interface can be suppressed. Therefore, S
The on-resistance can be reduced in the insulated gate field effect transistor using iC, and the enhancement type transistor can be easily manufactured.

[Brief description of drawings]

FIG. 1 shows an element structure cross section (a) of a buried channel insulated gate field effect transistor according to an embodiment of the present invention, an impurity distribution (b) along a line AA ′, and a band diagram (c). Fig.

FIG. 2 is a diagram showing the gate voltage dependence of mobility in the same embodiment as compared with a conventional example.

FIG. 3 is a diagram showing a gate voltage dependency of a drain current in the same embodiment as compared with a conventional example.

FIG. 4 is a view showing a device structure cross section (a) of a conventional buried channel insulated gate field effect transistor, an impurity distribution (b) along a line BB ′, and a band diagram (c).

FIG. 5 is a diagram showing gate voltage dependence of mobility in a conventional example.

FIG. 6 is a diagram showing the gate voltage dependence of drain current in a conventional example in comparison with simulation results.

[Explanation of symbols]

11 ... p-type SiC substrate (first SiC layer) 12 ... n-type SiC buried channel layer (second SiC layer)
Layer) 13 p-type SiC layer (third SiC layer) 15 n-type SiC source region 16 n-type SiC drain region 17 gate insulating film 21 gate electrode 22 source electrode 23 drain electrode

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tetsuo Hatakeyama             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center (72) Inventor Takashi Shinohe             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center (72) Inventor Kenji Fukuda             1-1-1 Higashi 1-1-1 Tsukuba City, Ibaraki Prefecture             Inside the National Institute of Advanced Industrial Science and Technology (72) Inventor Kazuo Arai             1-1-1 Higashi 1-1-1 Tsukuba City, Ibaraki Prefecture             Inside the National Institute of Advanced Industrial Science and Technology (72) Inventor Shinsuke Harada             1-1-1 Higashi 1-1-1 Tsukuba City, Ibaraki Prefecture             Inside the National Institute of Advanced Industrial Science and Technology (72) Inventor Seiji Suzuki             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F-term (reference) 5F140 AA01 AA30 AC22 AC23 AC24                       BA02 BB06 BB13 BC06 BE07                       BJ01 BJ05 BK13

Claims (4)

[Claims] 1. A first conductivity type first SiC layer, said first S layer.
Second conductivity type second SiC provided in contact with the iC layer
A layer, a semiconductor region formed of a third SiC layer of a first conductivity type provided in contact with the second SiC layer, and a gate electrode formed on the third SiC layer via a gate insulating film. A semiconductor device comprising a source / drain region of the second conductivity type formed on the surface of the semiconductor region with the gate electrode sandwiched between the first SiC layer and the gate electrode. The second
A semiconductor device characterized in that the current between the source and drain regions is controlled by controlling the carrier concentration of the SiC layer. 2. The semiconductor device according to claim 1, wherein the second SiC layer can be depleted by the potentials of the first SiC layer and the gate electrode. 3. The semiconductor device according to claim 1, wherein the second SiC layer is depleted when the potential difference between the first SiC layer and the gate electrode is zero. 4. The semiconductor device according to claim 1, wherein the thickness of the third SiC layer is 30 nm or more.