CN101552286A - Metal-semiconductor field effect transistor and production method thereof - Google Patents

Metal-semiconductor field effect transistor and production method thereof Download PDF

Info

Publication number
CN101552286A
CN101552286A CNA2009100220138A CN200910022013A CN101552286A CN 101552286 A CN101552286 A CN 101552286A CN A2009100220138 A CNA2009100220138 A CN A2009100220138A CN 200910022013 A CN200910022013 A CN 200910022013A CN 101552286 A CN101552286 A CN 101552286A
Authority
CN
China
Prior art keywords
silicon carbide
type
grid
layer
buffer layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2009100220138A
Other languages
Chinese (zh)
Inventor
吕红亮
张睿
张玉明
张义门
郭辉
郑少金
王德龙
张甲阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CNA2009100220138A priority Critical patent/CN101552286A/en
Publication of CN101552286A publication Critical patent/CN101552286A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses a metal-semiconductor field effect transistor formed in silicon carbide, mainly solving the problem of surface trap formed on the surface when making a component. The transistor comprises a semi-insulating silicon carbide substrate (1), a p-type silicon carbide buffer layer (2), a n-type silicon carbide conducting channel layer (3), a n+ capping layer (5), a source electrode (7) and a drain electrode (8), wherein a n-type silicon carbide buffer layer (4) is arranged between the n-type silicon carbide conducting channel layer (3) and the n+ capping layer (5); and a grid electrode (6) are buried inside the buffer layer to form a buried-channel and buried-grid structure. The process of making the component comprises the following steps of: epitaxially growing the p-type silicon carbide buffer layer, the n-type silicon carbide channel layer, the n-type silicon carbide buffer layer and n+ capping layer in sequence; etching grid recession windows on the n+ capping layer and carrying out sacrificial oxidation; and forming the source electrode, the drain electrode and the grid electrode by evaporating metal and peeling. The metal-semiconductor field effect transistor can be used for the manufacturing of high-frequency and high-power integrated circuits.

Description

Metal-semiconductor field effect transistor and preparation method thereof
Technical field
The invention belongs to field of microelectronic devices, particularly a kind of field-effect transistor can be used for the making of high-frequency high-power integrated circuit.
Background technology
In recent years, along with electronic circuit in for example application of radio frequency, S-wave band and X-band work of high frequency, become more general for needs greater than the electronic circuit of 20 watts high-power disposal ability.Need transistor than high power load for this reason.At present, the transistor that has been used for high power load mainly contains bipolar transistor, power metal-oxide-semiconductor field effect transistor MOSFETs and junction field effect transistor JFETs.But the power handling capability of above these devices under higher operating frequency still has been subjected to certain restriction.
In recent years, developed the metal-semiconductor field effect transistor MESFETs that is applied to the high frequency aspect.This MESFETs device is because have only the majority carrier loaded current, thus than the design of bipolar transistor preferably the MESFET structure be used for frequency applications.Input has switching time faster this MESFETs device because the grid capacitance that reduces allows grid again, thus than the design of MOSFET and JFET preferably MESFET design.And the Schottky gate electrode structure of MESFET device makes it can produce the transistor that satisfies the frequency applications needs more.
The transistor that is applied to the high frequency field is except structure type, more mainly be that the characteristic that forms transistorized semi-conducting material influences its running parameter equally, i.e. electron mobility, saturated electron drift velocity, electrical breakdown electric field and thermal conductivity during transistor work.
Electron mobility is meant the average drift velocity of electronics under the unit electric field.In the past, the response time faster because bigger electric current will appear in less electric field when applying electric field, and then can appear, so should preferably have the semi-conducting material of high electron mobility.
Saturated electron drift velocity is meant the maximal rate that electronics can obtain in semi-conducting material.Because higher speed can change the short time from source electrode to drain electrode into, be used for frequency applications so should preferably have the material of higher saturated electron drift velocity.
The electrical breakdown electric field, the electric field strength the when electric current that is meant the puncture of schottky junction and the grid by device increases suddenly.Because can bear bigger electric field usually, so should be used for high-power, high frequency transistor by preferably high electrical breakdown electric field material for given scantling.
Thermal conductivity is meant semi-conducting material branch heat dissipation capability.In typical operation, high-power and high frequency transistor produces more substantial heat than small-signal transistor usually.When the temperature of semi-conducting material increased, along with leakage current increases, carrier mobility can reduce, and causes the decline of field-effect transistor overall performance.Therefore, if from semiconductor heat-dissipating, material will keep lower temperature and can carry bigger electric current.So should preferably high heat-conductivity materials be used for high-power, high frequency transistor.
Past is because the high electron mobility of III-V compounds of group has produced for example MESFETs of the highest frequency of GaAs (GaAs) of n type III-V compounds of group.Though the device with these material has improved operating frequency and has suitably improved power handling capability, because the puncture voltage and the thermal conductivity of these materials are lower, has limited their application in high power device.
Carborundum (SiC) is known by people with its good physical characteristic and electrical characteristics always, and it allows to make electronic device in theory.The SiC material is owing to have 4 * 10 6The high breakdown electric field, 2.0 * 10 of V/cm 7The characteristics of the high saturated electron drift velocity of cm/sec and the high heat conductance of 4.9W/cm-° of K, thereby be suitable for high frequency, powerful application.But, again because the difficulty of SiC device making technics has limited it in high-power and extensive use high frequency.
Along with the development of device making technics, on silicon (Si) substrate, made MESFETs with carborundum channel layer.But because the application of Si substrate has limited the heat-sinking capability of device usually.Therefore, growth SiC usually can cause producing defective in the epitaxial loayer because temperature is too high on the Si substrate, thereby causes device bigger leakage current when working.
In recent years, along with the improvement and the development of SiC device making technics, made the MESFETs of the SiC epitaxial loayer of on the SiC substrate, growing.Because the epitaxial loayer of growing has improved crystal mass,, and puncture voltage, power output and the operating frequency of MESFETs have further been improved so these devices have demonstrated the thermal characteristics that is better than the Si substrate devices on the SiC substrate.
But, present existing MESFET device architecture is because its surface exists serious trap effect, thereby under the MESFET device applies drain voltage biasing, electronics is during from gate tunneling to the surface charge depletion region, captured by surface trap, and then produce parasitic grid, and form depletion layer near surface.This depletion layer will cause the minimizing of effective channel thickness, the decline of electron mobility and the reduction of leakage current.Along with the increase of drain-to-gate voltage difference, the influence of surface trap effect becomes more obvious, and this will have a strong impact on the microwave power output characteristic of MESFET.
Summary of the invention
The objective of the invention is to overcome above-mentioned, a kind of structure and manufacture method of metal-semiconductor field effect transistor is provided,, improve microwave, the power out-put characteristic of device to reduce or to eliminate the surface trap effect of device so that the deficiency of technology to be arranged.
For achieving the above object, device of the present invention comprises: semi-insulating type silicon carbide substrates (1), p type silicon carbide buffer layer (2), n type carborundum conductivity channel layer (3), n+ block layer (5), source electrode (7) and drain electrode (8), it is characterized in that being provided with one deck n type silicon carbide buffer layer (4) between n type conductivity channel layer (3) and the n+ block layer (5), be embedded with grid (6) in this resilient coating, form buried channel-bury grid structure.
For achieving the above object, the method for making device of the present invention comprises the steps:
1) on the silicon carbide substrates of semi-insulating type, epitaxial growth one deck doping content is 1.0 * 10 15Cm -3～2.0 * 10 15Cm -3, thickness is the p type silicon carbide buffer layer of 0.50 μ m～0.80 μ m;
2) on p type silicon carbide buffer layer, epitaxial growth one deck doping content is 1.0 * 10 15Cm -3～4.0 * 10 15Cm -3, thickness is the n type silicon carbide epitaxial channel layer of 0.20 μ m～0.40 μ m;
3) on n type carborundum channel layer, epitaxial growth one deck doping content is 1.0 * 10 17Cm -3～2.0 * 10 17Cm -3, thickness is the silicon carbide buffer layer of the n type of 0.05 μ m～0.15 μ m;
4) on the silicon carbide buffer layer of n type, epitaxial growth one deck doping content is 1.0 * 10 19Cm -3～2.0 * 10 19Cm -3, thickness is the n+ block layer of 0.15 μ m～0.30 μ m;
5) at the centre of surface of n+ block layer, utilize the RIE method to etch the grid recess window, and carry out sacrificial oxidation on the surface;
6) at both sides photolithographic source, the drain region of n+ block layer, and successively by evaporation, peel off and anneal and form source, the drain electrode of ohmic contact;
7) photoetching grid recess zone, and at the grooved area zone line by RIE method etching n type resilient coating to 0.03 μ m～0.10 μ m, at institute etching place by evaporation, peel off, form the grid of the unsymmetric structure of Schottky contacts, finish the making of device.
The present invention makes conducting channel be moved in the body by device surface owing to be provided with one deck n type silicon carbide buffer layer between MESFET device surface and conducting channel, weakens even eliminated the influence of surface trap effect effectively; Because grid is imbedded in the n type silicon carbide buffer layer, reduced gate bottom and surface contact area greatly, thereby reduced the influence that the surface trap effect causes device significantly, and improved the control ability of grid simultaneously conducting channel.
Description of drawings
Fig. 1 is a structure chart of the present invention.
Fig. 2 is a making flow chart of the present invention.
Fig. 3 utilizes the emulation contrast images of the ISE TCAD of simulation software to the I-V DC characteristic of the MESFET of the MESFET of embodiments of the invention 1 described structure and ordinary construction.Wherein Fig. 3 a is the I-V characteristic curve of ordinary construction MESFET, and Fig. 3 b is the I-V characteristic curve of embodiment 1 described structure MESFET.
With reference to Fig. 1, device of the present invention comprises from bottom to top: semi-insulating type silicon carbide substrates 1, p type silicon carbide buffer layer 2, n type carborundum conductivity channel layer 3, n type silicon carbide buffer layer 4 and n+ block layer 5; Imbed the grid 6 in the n type resilient coating, and source electrode 7 and drain electrode 8 on the n+ block layer.Wherein p type buffer layer concentration is 1.0 * 10 15Cm -3～2.0 * 10 15Cm -3, thickness is 0.50 μ m～0.8 μ m, n type conductivity channel layer concentration is 1.0 * 10 15Cm -3～4.0 * 10 15Cm -3, thickness is 0.20 μ m～0.4 μ m, n type silicon carbide buffer layer concentration is 1.0 * 10 15Cm -3～2.0 * 10 15Cm -3, thickness is 0.05 μ m～0.15 μ m, n+ block layer concentration is 1.0 * 10 19Cm -3～2.0 * 10 19Cm -3, thickness is 0.15 μ m～0.30 μ m, the degree of depth that grid is imbedded n type resilient coating is 0.03 μ m～0.10 μ m.
With reference to Fig. 2, the making of device of the present invention provides following three kinds of embodiment.
Embodiment 1, and the detailed process of making device of the present invention is as follows:
Step 1, epitaxial growth p type silicon carbide buffer layer.
On the silicon carbide substrates of semi-insulating type, epitaxial growth one deck p type mixes, concentration is 1.4 * 10 15Cm -3, thickness is the p type epitaxial buffer layer of 0.50 μ m.
Step 2, epitaxial growth n type carborundum channel layer.
On p type silicon carbide buffer layer, epitaxial growth one deck n type mixes, concentration is 3.4 * 10 17Cm -3, thickness is the n type carborundum channel layer of 0.26 μ m.
Step 3, epitaxial growth n type silicon carbide buffer layer.
On n type carborundum channel layer, epitaxial growth one deck n type mixes, concentration is 1.4 * 10 15Cm -3, thickness is the silicon carbide buffer layer of the n type of 0.10 μ m.
Step 4, epitaxial growth n+ block a shot the layer.
On the silicon carbide buffer layer of n type, epitaxial growth one deck n type mixes, concentration is 1.0 * 10 19Cm -3, thickness is the n+ block layer of 0.20 μ m.
Step 5, etching grid recess window and sacrificial oxidation.
5a) in the centre of surface zone of n+ block layer, utilize the RIE method to etch the grid recess window, the width of its etching is 5 μ m, and the degree of depth is 0.6 μ m;
5b) after the etching of recessed grid region, utilizing dry-oxygen oxidation technology to form thickness at device surface is 200
Figure A20091002201300081
Fine and close SiO 2Oxide layer after oxide layer forms, is corroded smooth to its surface.
Step 6 forms source electrode, the drain electrode of ohmic contact.
6a) source, the drain region on photoetching n+ block layer both sides utilize wet etching to erode this source, the interior SiO of drain region 2
6b) eroding SiO 2Source, drain region in, band glue evaporation NiCr alloy, and peel off the Metal Cr in this source, drain region, when keeping temperature to be 980 ℃ under the nitrogen environment protection, short annealing 5 minutes makes Ni and SiC generate nisiloy, source electrode, the drain electrode of formation ohmic contact.
Step 7, the grid of formation Schottky contacts.
7a) photoetching grid recess zone utilizes wet etching to erode SiO in this grid recess zone 2
7b) eroding SiO 2The grid recess zone line, by RIE method etching n type resilient coating to 0.08 μ m;
7c) in the n type resilient coating of etching, band glue evaporation Ti/Pt/Au multiple layer metal, and, form the asymmetric gate of Schottky junction structure by stripping metal Ti, wherein the distance of grid and source electrode is that the distance of 1 μ m, grid and drain electrode is 3 μ m, finishes the making of device.
Embodiment 2, and the detailed process of making device of the present invention is as follows:
Step 1, epitaxial growth p type silicon carbide buffer layer.
On the silicon carbide substrates of semi-insulating type, epitaxial growth one deck p type mixes, concentration is 1.0 * 10 15Cm -3, thickness is the p type epitaxial buffer layer of 0.80 μ m.
Step 2, epitaxial growth n type carborundum channel layer.
On p type silicon carbide buffer layer, epitaxial growth one deck n type mixes, concentration is 4.0 * 10 17Cm -3, thickness is the n type carborundum channel layer of 0.20 μ m.
Step 3, epitaxial growth n type silicon carbide buffer layer.
On n type carborundum channel layer, epitaxial growth one deck n type mixes, concentration is 1.0 * 10 15Cm -3, thickness is the silicon carbide buffer layer of the n type of 0.05 μ m.
Step 4, epitaxial growth n+ block a shot the layer.
On the silicon carbide buffer layer of n type, epitaxial growth one deck n type mixes, concentration is 2.0 * 10 19Cm -3, thickness is the n+ block layer of 0.15 μ m.
Step 5, etching grid recess window and sacrificial oxidation.
5a) in the centre of surface zone of n+ block layer, utilize the RIE method to etch the grid recess window, the width of its etching is 5 μ m, and the degree of depth is 0.6 μ m;
5b) after the etching of recessed grid region, utilizing dry-oxygen oxidation technology to form thickness at device surface is 200
Figure A20091002201300091
Fine and close SiO 2Oxide layer after oxide layer forms, is corroded smooth to its surface.
Step 6 forms source electrode, the drain electrode of ohmic contact.
6a) source, the drain region on photoetching n+ block layer both sides utilize wet etching to erode this source, the interior SiO of drain region 2
6b) eroding SiO 2Source, drain region in, band glue evaporation NiCr alloy, and peel off the Metal Cr in this source, drain region, when keeping temperature to be 980 ℃ under the nitrogen environment protection, short annealing 5 minutes makes Ni and SiC generate nisiloy, source electrode, the drain electrode of formation ohmic contact.
Step 7, the grid of formation Schottky contacts.
7a) photoetching grid recess zone utilizes wet etching to erode SiO in this grid recess zone 2
7b) eroding SiO 2The grid recess zone line, by RIE method etching n type resilient coating to 0.10 μ m.
7c) in the n type resilient coating of etching, band glue evaporation Ti/Pt/Au multiple layer metal, and, form the asymmetric gate of Schottky junction structure by stripping metal Ti, wherein the distance of grid and source electrode is that the distance of 1 μ m, grid and drain electrode is 3 μ m, finishes the making of device.
Embodiment 3, and the detailed process of making device of the present invention is as follows:
Step 1, epitaxial growth p type silicon carbide buffer layer.
On the silicon carbide substrates of semi-insulating type, epitaxial growth one deck p type mixes, concentration is 2.0 * 10 15Cm -3, thickness is the p type epitaxial buffer layer of 0.60 μ m.
Step 2, epitaxial growth n type carborundum channel layer.
On p type silicon carbide buffer layer, epitaxial growth one deck n type mixes, concentration is 1.0 * 10 17Cm -3, thickness is the n type carborundum channel layer of 0.40 μ m.
Step 3, epitaxial growth n type silicon carbide buffer layer.
On n type carborundum channel layer, epitaxial growth one deck n type mixes, concentration is 2.0 * 10 15Cm -3, thickness is the silicon carbide buffer layer of the n type of 0.15 μ m.
Step 4, epitaxial growth n+ block a shot the layer.
On the silicon carbide buffer layer of n type, epitaxial growth one deck n type mixes, concentration is 1.6 * 10 19Cm -3, thickness is the n+ block layer of 0.30 μ m.
Step 5, etching grid recess window and sacrificial oxidation.
5a) in the centre of surface zone of n+ block layer, utilize the RIE method to etch the grid recess window, the width of its etching is 5 μ m, and the degree of depth is 0.6 μ m;
5b) after the etching of recessed grid region, utilizing dry-oxygen oxidation technology to form thickness at device surface is 200
Figure A20091002201300101
Fine and close SiO 2Oxide layer after oxide layer forms, is corroded smooth to its surface.
Step 6 forms source electrode, the drain electrode of ohmic contact.
6a) source, the drain region on photoetching n+ block layer both sides utilize wet etching to erode this source, the interior SiO of drain region 2
6b) eroding SiO 2Source, drain region in, band glue evaporation NiCr alloy, and peel off the Metal Cr in this source, drain region, when keeping temperature to be 980 ℃ under the nitrogen environment protection, short annealing 5 minutes makes Ni and SiC generate nisiloy, source electrode, the drain electrode of formation ohmic contact.
Step 7, the grid of formation Schottky contacts.
7a) photoetching grid recess zone utilizes wet etching to erode SiO in this grid recess zone 2
7b) eroding SiO 2The grid recess zone line, by RIE method etching n type resilient coating to 0.03 μ m.
7c) in the n type resilient coating of etching, band glue evaporation Ti/Pt/Au multiple layer metal, and, form the asymmetric gate of Schottky junction structure by stripping metal Ti, wherein the distance of grid and source electrode is that the distance of 1 μ m, grid and drain electrode is 3 μ m, finishes the making of device.
Effect of the present invention can further specify by following emulation to embodiment 1:
(1) emulation content: utilize the ISE TCAD of simulation software, to the MESFET of embodiment 1 described structure, and the MESFET of ordinary construction draws, and above two kinds DC I-V characteristics of having drawn the MESFET structure are carried out analog simulation, obtains emulating image.Wherein the condition of emulation is that drain voltage changes to 20V from 0V, grid voltage get respectively 0V ,-2V ,-4V ,-6V ,-8V.
(2) simulation result, as shown in Figure 3.Fig. 3 a is the I-V characteristic curve of ordinary construction MESFET, and Fig. 3 b is the I-V characteristic curve of embodiment 1 described structure MESFET.From Fig. 3 a and Fig. 3 b as can be seen, getting 0V with grid voltage is example, the drain saturation current density I of the MESFET of the described structure of Fig. 3 a DsatNear 540 μ A/ μ m, and the drain saturation current density I of the MESFET of the described structure of Fig. 3 b DsatNear 300 μ A/ μ m.This shows that the DC I-V characteristic of the MESFET of embodiment 1 described structure is significantly improved than the MESFET of ordinary construction.

Claims (6)

1. metal-semiconductor field effect transistor, comprise: semi-insulating type silicon carbide substrates (1), p type silicon carbide buffer layer (2), n type carborundum conductivity channel layer (3), n+ block layer (5), source electrode (7) and drain electrode (8), it is characterized in that being provided with one deck n type silicon carbide buffer layer (4) between n type conductivity channel layer (3) and the n+ block layer (5), be embedded with grid (6) in this resilient coating, form buried channel-bury grid structure.
2. according to the transistor of claim 1, wherein the doping content of n type silicon carbide buffer layer (4) is 1.0 * 10 15Cm -3～2.0 * 10 15Cm -3, thickness is 0.05 μ m～0.15 μ m.
3. according to the transistor of claim 1, wherein to imbed the degree of depth of n type silicon carbide buffer layer (4) be 0.03 μ m～0.10 μ m to grid (6), and grid (6) is respectively 1.0 μ m and 3.0 μ m apart from the distance of source electrode (7) and drain electrode (8).
4. the manufacture method of a metal-semiconductor field effect transistor comprises the steps:
1) on the silicon carbide substrates of semi-insulating type, epitaxial growth one deck p type mixes, concentration is 1.0 * 10 15Cm -3～2.0 * 10 15Cm -3, thickness is the p type silicon carbide buffer layer of 0.50 μ m～0.80 μ m;
2) on p type silicon carbide buffer layer, epitaxial growth one deck n type mixes, concentration is 1.0 * 10 17Cm -3～4.0 * 10 17Cm -3, thickness is the n type silicon carbide epitaxial channel layer of 0.20 μ m～0.40 μ m;
3) on n type carborundum channel layer, epitaxial growth one deck n type mixes, concentration is 1.0 * 10 15Cm -3～2.0 * 10 15Cm -3, thickness is the silicon carbide buffer layer of the n type of 0.05 μ m～0.15 μ m;
4) on the silicon carbide buffer layer of n type, epitaxial growth one deck n type mixes, concentration is 1.0 * 10 19Cm -3～2.0 * 10 19Cm -3, thickness is the n+ block layer of 0.15 μ m～0.30 μ m;
5) at the centre of surface of n+ block layer, utilize the RIE method to etch the grid recess window, and carry out sacrificial oxidation on the surface;
6) at both sides photolithographic source, the drain region of n+ block layer, and successively by evaporation, peel off and anneal and form source, the drain electrode of ohmic contact;
7) photoetching grid recess zone, and at the grooved area zone line by RIE method etching n type resilient coating to 0.03 μ m～0.10 μ m, at institute etching place by evaporation, peel off, form the grid of the unsymmetric structure of Schottky contacts, finish the making of device.
5. manufacture method according to claim 4, the described etching grid recess of step 5) window wherein, its width is 5 μ m, the degree of depth is 0.6 μ m.
6. manufacture method according to claim 4, the grid of the unsymmetric structure of the described formation Schottky contacts of step 7) wherein, be by between grid and the source electrode be 1 μ m apart from etching, by between grid and the drain electrode be 3 μ m apart from etching.
CNA2009100220138A 2009-04-14 2009-04-14 Metal-semiconductor field effect transistor and production method thereof Pending CN101552286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA2009100220138A CN101552286A (en) 2009-04-14 2009-04-14 Metal-semiconductor field effect transistor and production method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2009100220138A CN101552286A (en) 2009-04-14 2009-04-14 Metal-semiconductor field effect transistor and production method thereof

Publications (1)

Publication Number Publication Date
CN101552286A true CN101552286A (en) 2009-10-07

Family

ID=41156386

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2009100220138A Pending CN101552286A (en) 2009-04-14 2009-04-14 Metal-semiconductor field effect transistor and production method thereof

Country Status (1)

Country Link
CN (1) CN101552286A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102903632A (en) * 2012-10-24 2013-01-30 中国电子科技集团公司第四十七研究所 Manufacture method of Schottky diode NiCr barrier low-temperature alloy
CN104134697A (en) * 2014-08-11 2014-11-05 北京大学 Asymmetric Schottky source drain transistor and preparing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102903632A (en) * 2012-10-24 2013-01-30 中国电子科技集团公司第四十七研究所 Manufacture method of Schottky diode NiCr barrier low-temperature alloy
CN102903632B (en) * 2012-10-24 2014-10-08 中国电子科技集团公司第四十七研究所 Manufacture method of Schottky diode NiCr barrier low-temperature alloy
CN104134697A (en) * 2014-08-11 2014-11-05 北京大学 Asymmetric Schottky source drain transistor and preparing method thereof
CN104134697B (en) * 2014-08-11 2017-02-15 北京大学 Asymmetric Schottky source drain transistor and preparing method thereof

Similar Documents

Publication Publication Date Title
CN100517761C (en) Transistors having buried P-type layers beneath the source region and methods of fabricating the same
CN1286184C (en) Silicon carbide metal-semiconductor field effect transistors and methods of fabricating silicon carbide metal-semiconductor field effect transistors
Yoshida et al. A high-power AlGaN/GaN heterojunction field-effect transistor
CN105304689B (en) AlGaN/GaN HEMT devices and production method based on fluorinated graphene passivation
CN101378062B (en) Ed inverting circuit and integrated circuit element including the same
Kambayashi et al. Normally off n-channel GaN MOSFETs on Si substrates using an SAG technique and ion implantation
JP2003318398A (en) Silicon carbide semiconductor device
JP2005086171A (en) Semiconductor device and method of fabricating same
Ochiai et al. AlGaN/GaN heterostructure metal-insulator-semiconductor high-electron-mobility transistors with Si3N4 gate insulator
CN104167445B (en) GaN-based enhancement/depletion mode heterojunction field effect transistor with buried gate structure
Imanishi et al. Drain current density over 1.1 A/mm in 2D hole gas diamond MOSFETs with regrown p++-diamond ohmic contacts
Wang et al. Performance enhancement by using the n/sup+/-GaN cap layer and gate recess technology on the AlGaN-GaN HEMT fabrication
Masante et al. 175V,> 5.4 MV/cm, $50\\mathrm {m}\Omega.\text {cm}^{2} $ at 250° C Diamond MOSFET and its reverse conduction
Liu et al. AlN/GaN superlattice channel HEMTs on silicon substrate
Li et al. High voltage normally-off GaN MOSC-HEMTs on silicon substrates for power switching applications
CN113270492A (en) Trench type GaN insulated gate bipolar transistor
US20040119092A1 (en) Semiconductor device
CN101552286A (en) Metal-semiconductor field effect transistor and production method thereof
Liang et al. Power microelectronics: device and process technologies
CN113540224B (en) N-substrate groove type GaN insulated gate bipolar transistor
CN113410297B (en) MIS split gate GaN-based high electron mobility transistor and preparation method thereof
CN104167440A (en) Enhanced AlGaN/GaN heterojunction field effect transistor
Du et al. Normally-Off Metal-Insulator-Semiconductor P-GaN gated AlGaN/GaN high electron mobility transistors with low gate leakage current
TWI724694B (en) GaN HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME
CN109817711B (en) Gallium nitride transverse transistor with AlGaN/GaN heterojunction and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20091007