JP2003060067A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for forming a high performance low voltage operation MISFET and a high reliability high voltage operation MISFET on the same substrate. SOLUTION: Series resistance is reduced by forming a single layer spacer 13 on the side wall of the gate electrode 6L of a low voltage operation MISFET QL thereby decreasing the width of an LDD region 7L relatively. Furthermore, electric field at the end part of drain is relaxed by forming a two layer spacer 12 on the side wall of the gate electrode 6H of a high voltage operation MISFET QH thereby increasing the width of an LDD region 7H relatively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing technique, and more particularly to a MISFET (metal insulator semiconductor field) having a plurality of types of LDD (lightly doped drain) structures having different applied voltages.
The present invention relates to a technology effectively applied to a semiconductor device having a built-in d effect transistor).

[0002]

2. Description of the Related Art Memory LSI (large scale integrated)
circuit) and CMOS (complementary metal oxid)
In a logic LSI or the like, the power supply voltage between the internal circuit and the input / output circuit may be different.

For example, the width of the gate electrode of the MISFET of the internal circuit (hereinafter referred to as the gate length) is defined as M of the input / output circuit.
Although the speed is increased by setting the gate length of the ISFET shorter than that of the ISFET, in order to secure the withstand voltage of the semiconductor region forming the source / drain of the MISFET of the internal circuit, the power supply voltage of the internal circuit is set to that of the input / output circuit. It is set lower than the power supply voltage.

Hereinafter, two types of MISFETs having LDD structures having different operating voltages, which have been studied by the present inventors, will be described.

As shown in FIG. 15, MISFET Q _H having a relatively high operating voltage (hereinafter referred to as high voltage operating MISFET) Q _H and M having a relatively low operating voltage are provided on the same substrate 51.
ISFET (hereinafter referred to as low voltage MISFET) Q
_L and _L are formed, the gate insulating film 52 is formed thicker than the gate insulating film 52 of the low voltage operating MISFET Q _L in order to ensure the reliability of the gate insulating film 52 of the high voltage operating MISFET Q _H. It

Further, the source / drain of the high-voltage operating MISFET Q _H is composed of a relatively low-concentration LDD region 53 and a relatively high-concentration source / drain diffusion region 54, and similarly, the low-voltage operating MISFET Q _L of the high-voltage operating MISFET Q _H. The source / drain is composed of a relatively low concentration LDD region 53 and a relatively high concentration source / drain diffusion region 54. However, high voltage MISFET Q _H
And the low-voltage operation MISFET Q _L to each obtain the desired operating characteristics, the high-voltage operation MISFET
Means for changing the impurity concentration of the LDD region 53 constituting a part of the source-drain by the Q _H and the low-voltage operation MISFET Q _L is also taken.

[0007]

However, the present inventor has found that the semiconductor device technology having two types of MISFETs of LDD structure having different operating voltages has the following problems.

In the low voltage operation MISFET, the resistance of the source / drain has a great influence on the operation speed.
It is necessary to reduce the width of the LDD region to reduce the series resistance of the LDD region. On the other hand, in the high-voltage operation MISFET, it is necessary to increase the width of the LDD region to relax the electric field at the drain end in order to suppress the deterioration of device characteristics due to hot carriers.

However, FIG. 15 in the high voltage operation MISFET Q _H and the low-voltage operation MISFET Q _L was examined by the inventors as shown in, the spacer 55 which determines the width of the LDD region 53 on the side walls of the respective gate electrodes 56 at the same time It formed and can not be separately formed to the dimensions required width of the LDD region 53 in the high voltage operation MISFET Q _H and the low-voltage operation MISFET Q _L. Therefore, the low-voltage operation MISFET Q _H, can not be obtained a high speed operation desired, also in the high voltage operation MISFET Q _L,
There is a problem that the desired reliability cannot be obtained.

An object of the present invention is to provide a high performance low voltage MISFET and a high reliability high voltage MISSF on the same substrate.
It is to provide a technique capable of forming ET.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, when a high-voltage operation MISFET and a low-voltage operation MISFET are formed on the same substrate, an LDD which forms a gate insulating film, a gate electrode, and a source / drain of the high-voltage operation MISFET and the low-voltage operation MISFET. Regions are sequentially formed, a silicon nitride film and a silicon oxide film are sequentially deposited on the substrate, and the silicon oxide film is anisotropically etched to form gate electrodes of the high-voltage operation MISFET and the low-voltage operation MISFET. Forming a first spacer made of a silicon oxide film on each side wall, removing the first spacer formed on the side wall of the gate electrode of the low-voltage operation MISFET, and anisotropically etching the silicon nitride film. On the sidewall of the gate electrode of the high-voltage operation MISFET, The second spacer is formed consisting of film, and a step of forming a third spacer made of a silicon oxide film on the side wall of the gate electrode of the low-voltage operation MISFET.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the sectional views of the essential part of the semiconductor substrate shown in FIGS. In the figure, Q _H is
For example, a high voltage operation M supplied with a power supply voltage of 3.3V
ISFET, Q _L is a low voltage operation MISFET, for example the power supply voltage of 1.2V is supplied.

First, as shown in FIG. 1, a semiconductor substrate 1 made of, for example, p-type single crystal silicon is prepared. Next, the semiconductor substrate 1 is thermally oxidized to have a thickness of 0.
A thin silicon oxide film 2 having a thickness of about 01 μm is formed, and then a silicon nitride film 3 having a thickness of about 0.1 μm is deposited on the silicon oxide film 2 by a CVD method.

After that, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are successively dry-etched using the resist pattern as a mask to form a device isolation groove having a depth of about 0.35 μm in the semiconductor substrate 1 in the device isolation region. 4a is formed.

Next, as shown in FIG. 2, the silicon oxide film 4b deposited on the semiconductor substrate 1 by the CVD method is etched back or polished by the CMP (chemical mechanical polishing) method to form the inside of the element isolation trench 4a. Silicon oxide film 4
While leaving b, the silicon nitride film 3 is removed by a wet etching method using hot phosphoric acid to form an element isolation region. Then, the semiconductor substrate 1 is annealed at about 1000 ° C. to densify the silicon oxide film 4b embedded in the element isolation trench 4a.

Then, after removing the silicon oxide film 2 using a hydrofluoric acid-based aqueous solution, a high voltage MISFET Q _{H is} operated.
Is formed on the surface of the semiconductor substrate 1 in the formation region of
The gate insulating film 5H of about m is formed, and the low voltage operation MIS is performed.
The semiconductor substrate 1 of the surface of the formation region of the FETs Q _L, for example, to form the thickness of 2nm about the gate insulating film 5L. The gate insulating films 5H and 5L can be formed as follows, for example.

First, the semiconductor substrate 1 is subjected to the first thermal oxidation treatment.
To form an insulating film on the surface of the semiconductor substrate 1 and then
Low voltage operation MISFE using resist pattern as mask
TQ _LThe insulating film in the formation region of is removed. Second half
The body substrate 1 is washed, and then the semiconductor substrate 1 is washed twice.
Apply thermal oxidation treatment to the eyes. As a result, the high voltage operation MIS
FETQ_H1st and 2nd thermal oxidation in the formation area of
The gate insulating film 5H formed by the treatment is formed, and the low voltage
Operation MISFETQ_LIn the formation area of
Then, the gate insulating film 5L formed by the process is formed.

Next, as shown in FIG. 3, a polycrystalline silicon film having a thickness of about 200 nm in which an n-type impurity such as phosphorus is introduced is deposited on the semiconductor substrate 1 by the CVD method, and thereafter,
The polycrystalline silicon film is etched using the resist pattern as a mask to form a gate electrode 6H having a gate length of about 0.2 to 0.25 μm in the formation region of the high voltage operation MISFET Q _H , and at the same time, a formation region of the low voltage operation MISFET Q _L. Then, a gate electrode 6L having a gate length of about 0.1 to 0.12 μm is formed. After that, the semiconductor substrate 1 is exposed to, for example, 800 ° C.
Dry oxidation treatment is performed.

[0022] Then, after covering the forming region of the low voltage operation MISFET Q _L in the resist pattern, the high-voltage operation MI
Using the gate electrode 6H of the SFETQ _H as a mask, n-type impurities such as phosphorus are ion-implanted into the semiconductor substrate 1 to form a relatively low-concentration LDD region 7H that constitutes a part of the source / drain of the high-voltage operation MISFET Q _H. To do. Similarly, after covering the formation region of the high-voltage operation MISFET Q _H with a resist pattern, n-type impurities such as arsenic are ion-implanted into the semiconductor substrate 1 by using the gate electrode 6L of the low-voltage operation MISFET Q _L as a mask, and the low-voltage operation MISF.
Forming a relatively low concentration LDD region 7L which constitutes a part of the source and drain of ETQ _L.

Next, as shown in FIG. 4, a silicon nitride film 8 having a thickness of, for example, about 60 nm and a silicon oxide film 9 having a thickness of, for example, about 100 nm are sequentially deposited on the semiconductor substrate 1. The silicon oxide film 9 is, for example, TE
OS (tetra ethyl ortho silicate: Si (OC ₂ H ₅ ))
₄ ) and ozone (O ₃ ) can be deposited by a thermal CVD method using source gas.

Next, as shown in FIG. 5, under the condition that an etching selection ratio is secured with respect to the silicon nitride film 8,
Silicon oxide film 9 by RIE (reactive ion etching) method
Is anisotropically etched to operate high voltage MISFET Q _H
The respective side walls of the gate electrode 6L of the gate electrode 6H and low-voltage operation MISFET Q _L of the silicon oxide film 9
The spacer 10 made of is formed.

Thereafter, as shown in FIG. 6, a high voltage operation M
After covering the formation region of the ISFET Q _H with the resist pattern 11, the spacer 10 in the formation region of the low-voltage operation MISFET Q _L is removed by wet etching using a hydrofluoric acid-based aqueous solution.

Next, after removing the resist pattern 11, as shown in FIG. 7, a silicon nitride film is formed by the RIE method under the condition that an etching selection ratio is secured with respect to the semiconductor substrate 1 and the silicon oxide film 4b. 8 is anisotropically etched to form the gate electrode 6H of the high voltage operation MISFET Q _H.
Of the side wall to form a two-layer spacer 12 consisting of spacer 10 (silicon oxide film 9) and the silicon nitride film 8, the first layer spacers 13 made of a silicon nitride film 8 on the side walls of the gate electrodes 6L of low voltage MISFET Q _L simultaneously Form. The width (L _H ) of the two-layer spacer 12 of the high voltage operating MISFET Q _H is, for example, about 150 nm, and the low voltage operating M
ISFETQ 1 layer width of the spacer 13 of the _L (L _L) is, for example, about 60 nm.

Next, as shown in FIG. 8, high voltage operation MI
Gate electrode 6H and two-layer spacer 12 of SFETQ _H
If, n in the semiconductor substrate 1 and the gate electrode 6L and one layer spacer 13 of low voltage MISFET Q _L as a mask
-Type impurities, such as arsenic, are ion-implanted, and high voltage operation M
ISFETQ _H and the low-voltage operation MISFET Q _L source and drain of the other a relatively high concentration drain diffusion region 14 which forms a part is formed.

Next, heat treatment is performed at 1000 ° C. for about 1 second in order to activate the ion-implanted impurities.

Next, for example, after depositing a cobalt film having a thickness of about 10 nm on the semiconductor substrate 1 by a sputtering method, a heat treatment at about 500 to 600 ° C. is applied to the semiconductor substrate 1 for about 60 seconds to form a high voltage MISFET Q _H. the surface and the surface of the source-drain diffusion region 14 of the gate electrode 6H, a gate electrode 6L of low voltage MISFET Q _L
A silicide layer 15 having a thickness of about 30 nm is selectively formed on the surface of the source and the surface of the source / drain diffusion region 14. Then, the semiconductor substrate 1 is subjected to heat treatment at about 700 to 800 ° C. for about 90 seconds to reduce the resistance of the silicide layer 15.

Next, as shown in FIG. 9, after forming the interlayer insulating film 16 made of, for example, a silicon oxide film on the semiconductor substrate 1, the interlayer insulating film 16 is processed by the dry etching method using the resist pattern as a mask. Accordingly, the high voltage operation MISFET Q _H and the low voltage operation MISFE
A contact hole 17 reaching the silicide layer 15 on the source-drain diffusion region 14 of the TQ _L perforating respectively. Although not shown, the high voltage operation MISFETQ
A contact hole reaching the silicide layer 15 on the gate electrode 6L of the gate electrode 6H and low-voltage operation MISFET Q _L of _H are simultaneously formed.

Next, as shown in FIG. 10, the semiconductor substrate 1
A metal film, for example, a tungsten film is deposited thereon, and the surface of the metal film is flattened by, for example, the CMP method to form a plug 18 in which the metal film is embedded inside the contact hole 17. Then, the metal film deposited on the upper layer of the interlayer insulating film 16 is etched to form the wiring layer 19, whereby the semiconductor device of the first embodiment is substantially completed. In addition, you may form a multilayer wiring in the upper layer of the wiring layer 19 as needed.

In the first embodiment, the high voltage operation M
On the sidewall of the gate electrode 6H of the ISFET Q _H, the two-layer spacer 12 including the spacer 10 (silicon oxide film 9) and the silicon nitride film 8 was formed, but the spacer having a laminated structure including three or more insulating films was formed. May be.

As described above, according to the first embodiment, the spacer 13 having a relatively small width is formed on the side wall of the gate electrode 6L of the low-voltage operation MISFET Q _L , so that the width of the LDD region 7L is relatively small. small becomes because the series resistance can be reduced to, it is possible to obtain a high-speed operation of the low voltage operation MISFET Q _L. In addition, high voltage operation MISFE
By forming the laminated spacer 12 having a relatively large width on the side wall of the gate electrode 6H of TQ _H , the width of the LDD region 7H becomes relatively large and the electric field at the drain end can be relaxed. It is possible to suppress deterioration of device characteristics due to hot carriers.

(Embodiment 2) A semiconductor device manufacturing method according to another embodiment of the present invention will be described with reference to the sectional views of the essential part of the semiconductor substrate shown in FIGS.

[0035] First, as shown in FIG. 11, a gate electrode 6L of the gate electrode 6H and low-voltage operation MISFET Q _L of the high-voltage operation MISFET Q _H in the same manner as that of the first embodiment, followed by the source and drain After forming the relatively low-concentration LDD regions 7H and 7L forming a part of the above, a silicon nitride film 8 and a silicon oxide film 9 are sequentially deposited on the semiconductor substrate 1. The steps up to this point are the same as the steps shown in FIGS. 1 to 4 of the first embodiment.

Next, as shown in FIG. 12, a high voltage operation M
After covering the formation region of ISFET Q _H with the resist pattern 20, the exposed silicon oxide film 9 is removed by wet etching using a hydrofluoric acid-based aqueous solution.

Next, after the resist pattern 20 is removed, as shown in FIG. 13, the silicon oxide film 9 is anisotropically formed by the RIE method under the condition that an etching selection ratio is secured with respect to the silicon nitride film 8. and sex etched to form a spacer 21 made of a silicon oxide film 9 on the side walls of the gate electrode 6H in high voltage operation MISFET Q _H.

After that, in the same manner as in the first embodiment,
The silicon nitride film 8 is anisotropically etched by the RIE method,
A two-layer spacer 22 composed of a spacer 21 (silicon oxide film 9) and a silicon nitride film 8 is formed on the side wall of the gate electrode 6H of the high-voltage operating MISFET Q _H , and at the same time, silicon nitride is formed on the side wall of the gate electrode 6L of the low-voltage operating MISFET Q _L. A one-layer spacer 23 made of the film 8 is formed. Then, after forming the interlayer insulating film 16 on the semiconductor substrate 1, a contact hole 17 is formed in the interlayer insulating film 16, and then a plug 18 is formed inside the contact hole 17.
After that, the metal film deposited on the semiconductor substrate 1 is etched to form the wiring layer 19, whereby the semiconductor device of the second embodiment shown in FIG. 14 is substantially completed.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, a logic circuit in which a memory cell and a logic circuit are provided on the same semiconductor substrate.
In a mixed memory, a MISFET having a spacer having a relatively small width is formed on a side wall of a gate electrode in a memory cell forming region where a fine gate pitch is required, and a MISFET of a logic circuit requiring high reliability is formed. A spacer having a relatively large width may be formed on the sidewall of the gate electrode in the formation region.

[0041]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Since the LDD region having a relatively small width is formed by the spacer having a relatively small width formed on the sidewall of the gate electrode of the low voltage operation MISFET, the LDD is formed.
High-speed low-voltage operation M due to reduction of series resistance in the region
ISFET can be realized. In addition, the LDD having a relatively large width is formed by the spacer having a relatively large width formed on the sidewall of the gate electrode of the high-voltage operation MISFET.
Since the region is formed, deterioration of device characteristics due to hot carriers can be suppressed by relaxing the electric field at the drain end. This enables high-performance low-voltage operation MISF
The ET and the high-reliability high-voltage operation MISFET can be formed on the same substrate.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor device studied by the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 silicon oxide film 3 silicon nitride film 4a element isolation groove 4b silicon oxide film 5H gate insulating film 5L gate insulating film 6H gate electrode 6L gate electrode 7H LDD region 7L LDD region 8 silicon nitride film 9 silicon oxide film 10 spacer 11 Resist pattern 12 Two-layer spacer 13 One-layer spacer 14 Source / drain diffusion region 15 Silicide layer 16 Interlayer insulating film 17 Contact hole 18 Plug 19 Wiring layer 20 Resist pattern 21 Spacer 22 Two-layer spacer 23 One-layer spacer 51 Substrate 52 Gate insulating film 53 LDD region 54 the source and drain diffusion regions 55 spacer 56 gate electrode Q _H high voltage operation MISFET Q _L low voltage MISFET

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tomohiro Saito             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F-term (reference) 5F048 AA00 AA07 AB01 AB03 AC01                       AC03 BA01 BB06 BB08 BB12                       BB16 BC06 BF06 BF07 BG14                       DA25 DA27 DA30

Claims (5)

[Claims] 1. A semiconductor device having a plurality of MISFETs of LDD structure having different operating voltages on the same substrate, wherein the side wall of a gate electrode of the MISFET having a relatively high operating voltage is composed of two or more insulating films. A semiconductor device in which a laminated spacer is formed, and the width of the laminated spacer is larger than the width of the spacer formed on the sidewall of the gate electrode of the MISFET having a relatively low operating voltage. 2. A method of manufacturing a semiconductor device, wherein a plurality of MISFETs having LDD structures having different operating voltages are formed on the same substrate, wherein two or more layers are formed on a sidewall of a gate electrode of the MISFET having a relatively high operating voltage. A MISFE having a relatively low operating voltage is formed by forming a laminated spacer made of an insulating film and having a relatively large width.
A method of manufacturing a semiconductor device, characterized in that a spacer having a relatively small width is formed on a sidewall of a gate electrode of T. 3. A first MISF having a relatively high operating voltage.
A method of manufacturing a semiconductor device, wherein ET and a second MISFET having a relatively low operating voltage are formed on the same substrate.
(A) After forming the gate insulating films of the first and second MISFETs, respectively, the first and second MISs are formed.
Forming the gate electrodes of the FETs, respectively (b)
Forming LDD regions forming source / drain of the first and second MISFETs, respectively;
(C) a step of sequentially depositing a first insulating film and a second insulating film having an etching selection ratio with respect to the first insulating film on the substrate; Isotropically etched to form first spacers made of the second insulating film on the sidewalls of the gate electrodes of the first and second MISFETs respectively, and (e) the second MI.
Removing the first spacer formed on the side wall of the gate electrode of the SFET; and (f) anisotropically etching the first insulating film to form the side wall of the gate electrode of the first MISFET. Second composed of the first and second insulating films
Forming a spacer, and forming a third spacer made of the first insulating film on the sidewall of the gate electrode of the second MISFET. 4. A first MISF having a relatively high operating voltage.
A method of manufacturing a semiconductor device, wherein ET and a second MISFET having a relatively low operating voltage are formed on the same substrate.
(A) After forming the gate insulating films of the first and second MISFETs, respectively, the first and second MISs are formed.
Forming the gate electrodes of the FETs, respectively (b)
Forming LDD regions forming source / drain of the first and second MISFETs, respectively;
(C) sequentially depositing a first insulating film and a second insulating film having an etching selection ratio with respect to the first insulating film on the substrate, and (d) forming the second MISFET. Removing the second insulating film in the region
(E) anisotropically etching the second insulating film to form a first spacer on the side wall of the gate electrode of the first MISFET; and (f) anisotropically forming the first insulating film. Etching is performed to form a second spacer made of the first and second insulating films on the sidewall of the gate electrode of the first MISFET, and the first spacer is provided on the sidewall of the gate electrode of the second MISFET. And a step of forming a third spacer made of an insulating film. 5. A method of manufacturing a semiconductor device in which a memory cell and a logic circuit are formed on the same substrate, wherein a spacer having a relatively small width is provided on a sidewall of a gate electrode in a region where the memory cell is formed. MISFET
And having a spacer having a relatively large width on the sidewall of the gate electrode in the region where the logic circuit is formed.
A method of manufacturing a semiconductor device, which comprises forming an SFET.