JP2003059795A - Method and apparatus for partitioning pattern for writing, method for writing, method for making mask, semiconductor device and method for manufacturing the same, program for partitioning pattern for writing and computer readable recording medium recorded with the program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus for partitioning a pattern for writing which enable the partition of any pattern without generating a fine pattern, method for writing, mask and method for making the same, semiconductor device and method for manufacturing the same, program for partitioning a pattern for writing and computer readable recording medium recorded with the program. SOLUTION: Lines passing the peak of a pattern 21 to be written on a resist are set as first partition candidate lines L1a-L1d, and lines not passing the peak which are obtained based on the first partition candidate lines L1a-L1d are set as second partition candidate lines L2a-L2b, L2c-L2h. Out of regions demarcated by the first and second partition candidate lines, adjacent regions are combined into a rectangle or a trapezoid so as to eliminate short sides having a predetermined length or shorter, and the rectangle or the trapezoid obtained by this combination process is used as a writing unit of a writing apparatus 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern for drawing which eliminates a minute pattern which leads to deterioration of drawing accuracy in drawing by a variable shaping method in which a charged particle beam is irradiated in rectangular units to draw a pattern. Division processing method, drawing pattern division processing apparatus, drawing method, mask, mask making method, semiconductor device, semiconductor device manufacturing method, drawing pattern division processing program, and computer-readable recording of this program Regarding the medium.

[0002]

2. Description of the Related Art FIG. 18 shows an example of a variable shaping type electron beam drawing apparatus. The electron beam drawing apparatus 1 includes a first electron gun 2 and a first opening 3a that is arranged below the electron gun 2 and has a rectangular opening 3a.
An aperture 3, a shaping deflector 4 for deflecting the electron beam transmitted through the first aperture 3, and a second aperture 5 arranged below the shaping deflector 4 and having a rectangular opening 5a formed therein,
An objective lens 6 arranged below the second aperture 5,
A positioning deflector 7 arranged below the objective lens 6,
The semiconductor substrate 8 or the mask substrate 9 coated with a resist is mounted on the stage (not shown). The shaping deflector 4 and the positioning deflector 7 are electromagnetic deflectors or electrostatic deflectors.

The electron beam EB emitted from the electron gun 2 has a rectangular cross section by passing through the first aperture 3. The electron beam having the rectangular cross section is deflected by the shaping deflector 4 to the second aperture 5. Reach The electron beam that has reached the second aperture 5 is transmitted only through the portion (rectangle) of the opening 5 a formed in the second aperture 5. The electron beam transmitted through the second aperture 5 passes through the objective lens 6 and the positioning deflector 7, and is focused and imaged at a desired position on the resist on the semiconductor substrate 8 or the mask substrate 9. That is, the electron beam has a rectangular sectional shape by the first aperture 3 and the second aperture 5, and its size can be arbitrarily changed by adjusting the deflection amount by the shaping deflector 4.

As described above, in the variable molding type drawing apparatus,
Since the electron beam having a rectangular cross section is used for drawing, it is necessary to divide the pattern to be drawn into rectangular units (shot division). For example, the design pattern (original pattern) 20 shown in FIG. 19 is divided into two rectangular patterns 20a and 20b. Then, the cross-sectional size of the electron beam is adjusted according to the size of each of the rectangular patterns 20a and 20b, and the electron beam shot is performed twice to write the pattern 20. The division unit may be a trapezoid other than a rectangle.
In this case, the trapezoidal hypotenuse can be formed by multiple exposure in which electron beam shots having a rectangular cross section are overlapped while shifting their positions. Here, for example, assuming that multiple exposure is performed 20 times, the dose amount per one electron beam shot is reduced to 1/20.

In shot division of such a pattern, a minute pattern may occur depending on the division method. For example, the pattern 20b shown in FIG. In the electron beam drawing apparatus using the variable shaping method, if such a minute pattern exists, the minute pattern cannot be drawn according to the design data (for example, the corners are rounded) and the drawing accuracy deteriorates. The problem is known. In this specification, for example, a pattern having a short side with a width of about 0.3 μm or less is a minute pattern.

In order to prevent this phenomenon, it is general to optimize the pattern division so that a minute pattern does not occur during shot division. For example, the pattern 20 is replaced with two patterns 20c as shown in FIG.
If it is divided into 20d, it is possible to avoid the generation of minute patterns.

[0007]

In the conventional pattern dividing processing, a method of dividing by using a line segment passing through the vertices of the pattern is generally used. This is in consideration of convenience in performing the division processing by the computer, and the division line is simply set in the x direction or the y direction from the vertex given by the coordinate value data of (x, y). However, with such a dividing method that depends only on dividing lines that pass through vertices, the generation of minute patterns may not be avoided no matter how the dividing lines are set. For example, pattern 2 as shown in FIG. 21A.
In the case of 1, as shown in FIG. 21B, a minute pattern 21b is generated even when divided by dividing lines L1a and L1b extending in the x direction from the apex, and a dividing line L1 extending in the y direction from the apex.
Even if it is divided by c and L1d, the minute pattern 21a is generated. As described above, the conventional division method has a problem in that it is inevitable that a minute pattern is generated depending on the pattern, and thus accurate drawing cannot be performed.

The present invention has been made in view of the above problems, and a drawing pattern division processing method for realizing division processing for any pattern while avoiding generation of minute patterns,
Dividing device for drawing pattern, drawing method, mask, mask making method, semiconductor device, semiconductor device manufacturing method,
It is an object of the present invention to provide a drawing pattern division processing program and a computer-readable recording medium recording the program.

[0009]

According to a first aspect of the present invention, there is provided a method of dividing a drawing pattern, wherein a pattern to be drawn on a resist is divided into units that can be drawn by a drawing apparatus. In the division processing method, a line segment that passes through each vertex of the pattern is set as a first division candidate line, and a line segment that does not pass through a vertex obtained based on the first division candidate line is set as a second division candidate line. Set as, first and second
The pattern is divided based on the division candidate lines of.

A drawing pattern division processing apparatus according to claim 6 of the present invention is a drawing pattern division processing apparatus for dividing a pattern to be drawn on a resist into units that can be drawn by the drawing apparatus. , A first division candidate line setting means for setting a line segment that passes through each vertex of the pattern as a first division candidate line, and a line segment that does not pass through the apex obtained based on the first division candidate line for the second division candidate line. A second division candidate line setting means set as a division candidate line and an adjacent area among the areas divided by the first and second division candidate lines are rectangular so as to eliminate short sides having a predetermined length or less. Alternatively, a combination processing unit for combining with a trapezoid is provided, and a rectangle or a trapezoid obtained by the combination is used as a unit for drawing by the drawing device.

According to the drawing method of claim 10 of the present invention,
A line segment that passes through each vertex of the pattern to be drawn on the resist is set as a first division candidate line, and a line segment that does not pass through the apex obtained based on the first division candidate line is set as a second division candidate line. Then, the pattern is divided into units that can be drawn by the drawing apparatus based on the first and second division candidate lines, and the pattern is drawn on the resist by the drawing apparatus for each divided unit.

A mask according to a fifteenth aspect of the present invention comprises a first division candidate line which is a line segment passing through each vertex of a pattern and a line segment which does not pass through the apex obtained based on the first division candidate line. Based on a certain second division candidate line, the pattern is divided into units that can be drawn by the drawing apparatus, and the divided pattern is
It is obtained by drawing each divided unit on a resist formed on the mask substrate with a drawing device and transferring the drawn pattern onto the mask substrate.

According to a twentieth aspect of the present invention, in a mask making method, a line segment passing through each vertex of a pattern is set as a first division candidate line, and a vertex obtained based on the first division candidate line is passed through. A line segment that is not set is set as a second division candidate line, a pattern is divided into units that can be drawn by the drawing apparatus based on the first and second division candidate lines, and a mask is provided for each divided unit. The method has a procedure of drawing a pattern on a resist formed on a substrate with a drawing apparatus and a procedure of transferring the drawn pattern to a mask substrate.

In a semiconductor device according to a twenty-fifth aspect of the present invention, a first division candidate line which is a line segment passing through each apex of the pattern and a line segment which does not pass through the apex obtained based on the first division candidate line. On the basis of the second division candidate line that is, the pattern divided into units that can be drawn by the drawing device is drawn by the drawing device on the resist formed on the mask substrate for each divided unit. The pattern was exposed and transferred onto the semiconductor substrate using a mask formed by transferring the drawn pattern onto the mask substrate.

In the semiconductor device according to claim 30 of the present invention, a first division candidate line which is a line segment passing through each vertex of the pattern and a line segment which does not pass through the apex obtained based on the first division candidate line. On the basis of the second division candidate line, the pattern is divided into units that can be drawn by the drawing device, and the divided units are drawn on the resist formed on the semiconductor substrate by the drawing device. The drawn pattern was transferred to the semiconductor substrate.

A semiconductor device manufacturing method according to a thirty-fifth aspect of the present invention is that a line segment passing through each vertex of a pattern is set as a first division candidate line, and a vertex obtained based on the first division candidate line is set. A procedure for setting a line segment that does not pass as a second division candidate line, and dividing the pattern into units that can be drawn by the drawing apparatus based on the first and second division candidate lines, and for each divided unit. A step of drawing a pattern on a resist formed on a mask substrate with a drawing device, a step of transferring the drawn pattern to a mask substrate to obtain a mask,
And a procedure of exposing and transferring a pattern onto a semiconductor substrate using this mask.

A semiconductor device manufacturing method according to a forty-first aspect of the present invention is that a line segment passing through each vertex of a pattern is set as a first division candidate line, and a vertex obtained based on the first division candidate line is set. A procedure for setting a line segment that does not pass as a second division candidate line, and dividing the pattern into units that can be drawn by the drawing apparatus based on the first and second division candidate lines, and for each divided unit. The method has a procedure of drawing a pattern on a resist formed on a semiconductor substrate by a drawing device and a procedure of transferring the drawn pattern to the semiconductor substrate.

According to a forty-fifth aspect of the present invention, there is provided a program for dividing a pattern for drawing, which divides a pattern to be drawn on a resist into units which can be drawn by a drawing apparatus. A segment is set as the first division candidate line, a line segment that does not pass through the vertices obtained based on the first division candidate line is set as the second division candidate line, and the first and second division candidate lines are set. Among the areas divided by the division candidate lines, adjacent areas are combined into a rectangle or a trapezoid so as to eliminate a short side having a predetermined length or less, and the rectangle or the trapezoid is used as a unit of drawing by the drawing device. Let the computer run.

A computer-readable recording medium according to a forty-ninth aspect of the present invention is a line segment passing through each vertex of a pattern for dividing a pattern to be drawn on a resist into units that can be drawn by a drawing apparatus. Is set as the first division candidate line, a line segment that does not pass through the vertices obtained based on the first division candidate line is set as the second division candidate line, and the first and second division lines are set. A procedure in which adjacent areas of the areas separated by the candidate lines are combined into a rectangle or a trapezoid so as to eliminate a short side of a predetermined length or less, and the rectangle or the trapezoid is used as a unit of drawing by a drawing device; It records the division processing program of the drawing pattern to be executed by.

That is, according to the present invention, by setting a dividing line that does not pass through the vertices other than the dividing line that passes through the vertex,
Conventionally, even for a pattern in which the generation of a minute pattern is inevitable only with a dividing line that passes through the apex, the dividing process is realized by eliminating the minute pattern.

The drawing pattern thus divided is input to the drawing device as drawing data, and in response to this, the drawing device forms the pattern on the resist formed on the mask substrate or the semiconductor substrate by the charged particle beam. (For example, electron beam) is used for drawing. The pattern drawn on the resist is transferred to a mask substrate or a semiconductor substrate through subsequent development and etching treatments. The mask substrate thus obtained is used as a mask for exposing and transferring a pattern onto a semiconductor substrate. On the other hand, a semiconductor substrate on which a pattern is directly drawn by a drawing device is a semiconductor substrate on which a pattern is formed by a so-called direct drawing method without using a mask. The semiconductor substrate manufactured by direct drawing or using a mask is then subjected to various processes, and a semiconductor device is completed through a chip dividing process, a bonding process, a packaging process, and the like.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the structure of a drawing pattern division processing apparatus according to the first embodiment of the present invention. The division processing device receives the input of the design pattern, and sets the first division candidate line setting means 11a for setting the first division candidate line and the second division candidate line based on the first division candidate line. Second division candidate line setting means 11b,
In order to eliminate a short side of a predetermined length (for example, 0.3 μm) or less that causes deterioration of drawing accuracy between adjacent areas among areas divided by the first and second division candidate lines,
The drawing processing unit 12 is composed of a combination processing unit 12 that combines the drawing unit 1 into a rectangular unit or a trapezoid unit. Note that the drawing apparatus 1 is the electron beam drawing apparatus 1 described above with reference to FIG. 18, and its operation is also the same.

The division processing device is specifically a computer, and the processing of the various processing means 11a, 11b, 12 is executed by a central processing unit (CPU).

The drawing pattern division processing program according to the present embodiment is stored in a storage device accessible to the central processing unit, and the central processing unit decodes the program when the program is executed and is also stored in the storage unit. The pattern data (such as the coordinate value data of the vertices) thus read is read out and the procedure described below is executed.

Next, referring to the flowchart of FIG.
The flow of the pattern division processing according to this embodiment will be described.

First, in step S1, the first division candidate line setting means 11a sets the first division candidate line in the input design pattern (original image pattern). Considering, for example, the case where the pattern 21 shown in FIG. 21A is input as a division processing target, as shown in FIG. 21B, the outer shape (outline) of the pattern 21 is formed in each of the x and y directions from each vertex of the pattern 21. A straight line is drawn up to the side where
1d.

This processing is the same as the conventional division processing based on line segments passing through vertices. Therefore, only with the first division candidate lines L1a to L1d, the pattern 21 is drawn no matter how it is divided. A minute pattern having a minute width w (for example, 0.3 μm or less) that causes deterioration of accuracy is generated.

Therefore, in the present embodiment, as the next step S2, the process for setting the second division candidate line is performed by the second division candidate line setting means 11b. The second division candidate line is set as a line segment that does not pass through the apex as follows. In FIG. 3, the second division candidate line L2a is the first
Pattern 2 connected to the first division candidate line L1a (L1b) and the first division candidate line L1a (L1b) on the same straight line
It is set as a vertical bisector of a line segment formed by the side m1 (m2) of 1. The second division candidate line L2b is connected to the first division candidate line L1c (L1d) and the pattern 21 which is connected to the first division candidate line L1c (L1d) on the same straight line.
Is set as a vertical bisector of a line segment formed by the side n1 (n2) of the.

The second division candidate lines L2a and L2b are not set at any positions that do not pass through the vertices, but are based on the previously set first division candidate lines L1a to L1d as described above. Since it is set by a clear algorithm, it is easy to perform automatic and quick processing by the computer. Also, it is possible to prevent the number of lines from being unnecessarily increased.

On the computer, each line segment is recognized by the coordinate value data at both ends, and various processes are performed based on this coordinate value data.

Then, steps S3 and S4 described below are performed.
At the first and second division candidate lines L1 set above
The combining processing of the areas delimited by a to L1d and L2a to L2b is performed. In this combining process, the combining process is performed according to an algorithm of combining the rectangular pattern or the trapezoid which is a drawing unit by the drawing apparatus 1 so that the minute pattern is eliminated.

At step S3, as shown in FIG. 4, attention is paid to the vertices P1 and P2 having an interior angle θ of more than 180 °, and the joining process is performed on the three regions sharing the corresponding vertices P1 and P2. The internal angle referred to here is the inner corner of the pattern among the angles formed by the two sides forming one vertex.

Considering the vertex P1, for example, among the three regions a1, b1 and c1 that share the vertex P1, there is an option of joining a1 and b1 or joining b1 and c1. Here, the area with the smallest area (or the area with the smallest area if there is no area with a minute width) is preferentially combined among the areas having a minute width that causes deterioration of drawing accuracy.
Therefore, in this case, since the area c1 itself does not have a side with a minute width that causes deterioration of drawing accuracy, the area a1
And the region b1 are connected.

The same joining process is performed for all the regions having vertices whose interior angle is larger than 180 °, and the result is as shown in FIG. That is, the area a1 and the area b1 are combined to form the area d1, and the area a2 and the area b2 are combined to form the area d2.
Becomes

The connection processing on the computer is as follows. The regions a1 and b1 are recognized as, for example, the coordinate values (x, y) of the lower left vertex and the width and height data from these coordinate values, and this is recognized by the combining process, for example, the lower left vertex of the region b1. It is recognized as an area d1 having data of coordinate values (x, y) of x, width, and height of area a1 + area b1.

Then, in step S4, the combining process is continued for the other areas. As an algorithm in this case, as a result of combining with the adjacent area, the one with the smallest area in the area with the minute width (the one with the smallest area if there is no area with the minute width) eliminates the minute width. So that they join together. Further, the regions whose minute widths have already been eliminated are combined so that the area of the regions becomes larger. If any adjacent area cannot be combined as a rectangle or trapezoid, leave it as it is.

As a result, in FIG. 5, the area e1 and the area f1 are combined to form the area g1 shown in FIG.

Next, in FIG. 6, a region e2 and a region f
2 are combined to form a region g2 shown in FIG.

Next, in FIG. 7, a region d1 and a region g
1, the area d2 and the area g2 are combined to become an area h1 and an area h2 shown in FIG. 8, respectively.

Next, referring to FIG. 8, a region i1 and a region j
1, the region i2 and the region j2 are combined to form a region k1 and a region k2 shown in FIG. 9, respectively.

Next, in FIG. 9, a region k1 and a region h
1, the region k2 and the region h2 are combined to form a region 1 (lowercase letter L) 1 and a region 1 (lowercase letter L) 2 shown in FIG. 10, respectively, and finally a division result as shown in FIG. 10 is obtained.

In the division result shown in FIG. 10, the minute pattern is eliminated, and the areas c1, c2, l1,
12 is a rectangle that is a unit that can be drawn by the drawing apparatus 1. That is, the pattern 21 is drawn by four electron beam shots for each of the four regions (patterns) c1, c2, l1, and l2.

Even if a minute pattern is eliminated in the middle of the combining process, if the combining process ends there, the division may be cut into pieces and the number of shots may increase. Is not rectangular or trapezoidal). This allows
By reducing the number of divisions, that is, the number of shots as much as possible, the labor and time for drawing can be reduced.

The pattern thus divided is input to the drawing apparatus 1 as drawing data.
When a pattern is drawn on the resist formed on the semiconductor substrate (for example, a silicon wafer) 8 by the drawing apparatus 1 (in the case of so-called direct drawing), the resist is then developed to remove this resist. As a mask, the semiconductor substrate 8 is etched, a thin film is formed, and the like.

On the other hand, for example, when a pattern is drawn on the resist formed on the mask substrate 9 in which a chromium film is formed on the quartz substrate, the resist is developed after that and the chromium is used as a mask. The film is etched to obtain a mask with the desired pattern. Then, by exposure transfer using this mask, the pattern on the mask is transferred and formed on the semiconductor substrate.

As described above, in the present embodiment, not only the dividing lines that pass the vertices of the pattern but also the dividing lines that do not pass the vertices are set, and the dividing is performed based on these dividing lines. It is possible to improve the accuracy of the drawing pattern by realizing the division result in which the minute pattern is eliminated even for the pattern in which the minute pattern cannot be eliminated conventionally. As a result, a mask obtained by drawing the pattern, a semiconductor substrate obtained by exposure transfer or direct drawing using this mask, and further a dividing process from this semiconductor substrate to a chip, a bonding process, a packaging process, etc. It is possible to improve the quality of the semiconductor device obtained after that.

Next, a second embodiment of the present invention will be described.

The second embodiment differs from the first embodiment in the way of setting the second division candidate line. In the second embodiment, of the areas divided by the first division candidate line, the vertical and horizontal crossing is performed at the center point of a minute area having a short side of a predetermined length or less that causes deterioration of drawing accuracy. The line segment is used as the second division candidate line.

Specifically, as shown in FIG. 11, the first division candidate line L set as in the first embodiment is set.
1a to L1d have three minute regions 22a, 22b, 22
c occurs. Then, line segments L2c and L2d that vertically and horizontally intersect at the center point of the minute region 22a, line segments L2e and L2f that vertically and horizontally intersect at the center point of the minute region 22b, and the minute region 2
Line segments L2g and L2h intersecting vertically and horizontally at the center point of 2c are set as second division candidate lines.

Then, the combining process of the areas delimited by the first and second division candidate lines L1a to L1d and L2c to L2h set as described above is performed. In this combining process, as in the first embodiment, the combining process is performed in accordance with an algorithm for eliminating a minute pattern and combining with a rectangle or a trapezoid which is a drawing unit by the drawing apparatus 1.

First, as shown in FIG. 12, the internal angle θ is 18
Focusing on the vertices P1 and P2 larger than 0 °, the joining process is performed on the three regions sharing the corresponding vertices P1 and P2.

Considering, for example, the vertex P1, of the three regions A1, B1, and C1 sharing the vertex P1, the region C1 itself has a side with a minute width that causes deterioration of drawing accuracy. Since it does not exist, the area A1 and the area B1 having a very small width that deteriorates the drawing accuracy are combined. Similar joining processing is performed on all regions having vertices whose interior angle is greater than 180 °. That is, the area A2 and the area B2 are also combined.

The combining process is continued for other areas. As the algorithm in this case, as in the case of the first embodiment, the smallest area among the areas having a minute width (the smallest area if there is no area having a minute width)
On the other hand, as a result of combining with the adjacent region, the bonding is performed so that the minute width is eliminated. Further, the regions whose minute widths have already been eliminated are combined so that the area of the regions becomes larger.
If any adjacent area cannot be combined as a rectangle or trapezoid, leave it as it is.

Thus, first, as shown in FIG.
Area E1 in which area A1, area B1, and area C1 are combined
And an area E in which the area A2, the area B2, and the area C2 are combined.
2 is obtained.

Then, as shown in FIG. 14, areas E1 and
Region I1 in which region F1, region G1, and region H1 are combined
Then, a region I2 in which the region E2, the region F2, the region G2, and the region H2 are combined is obtained.

Finally, as shown in FIG.
The pattern 21 is divided into six rectangular areas C1, C2, J1, J2, K1, and K2 in which the minute pattern is eliminated.

In the second embodiment, too,
The same effect as the first embodiment can be obtained.

Further, in the first and second embodiments, the first embodiment is more advantageous in terms of drawing time because the number of divisions, that is, the number of shots is smaller.

However, when applied to the gate layer of a MOS transistor, for example, the division result according to the first embodiment shows that the division line L2b extends along the extending direction of the gate layer 25 as shown in FIG. Therefore, division of the gate layer 25 on the active region 24 is unavoidable. Therefore, as the operating region of the transistor, the connection accuracy of the gate layer 25 on the active region 24, which requires high pattern accuracy, may be deteriorated, and normal operation of the transistor may be hindered.

On the other hand, in the division according to the second embodiment, as shown in FIG. 17, it is possible to arrange the division boundary only outside the active area (on the field area) where the connection accuracy is not so required. The division of the gate layer 26 on the active region 24 can be avoided. Therefore, the pattern of the gate layer 26 can be transferred onto the active region 24 by one shot, so that the influence of deterioration of the connection accuracy can be prevented.

Although the respective embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to these.
Various modifications are possible based on the technical idea of the present invention.

The order of region combination is not limited to that shown in the above embodiments. For example, in the first embodiment, in the state shown in FIG. 5, the region e1 and the region i1, and the region f1 and the region j1 are respectively combined first, and then the regions obtained by this combination are combined, and It may be combined with d1 to obtain the region 11 shown in FIG.

The unit for connecting the areas is not limited to a rectangle but may be a trapezoid.

Further, the present invention is applicable not only to the pattern 21 shown in each of the above-mentioned embodiments but also to patterns of other shapes. In short, the present invention is effective for all patterns having a shape in which the generation of minute patterns cannot be avoided only by the dividing lines passing through the vertices.

[0066]

According to the first aspect of the present invention, it is possible to surely perform the division process while avoiding the minute pattern for any pattern, and prevent the deterioration of the drawing accuracy. In addition, claim 2
In the division based on the division candidate line according to, it is possible to reduce the number of divisions as much as possible, and it is suitable for shortening the drawing time. A layout that avoids division in step 1 can be taken, and reliable operation of transistors is guaranteed. Further, according to claim 4, it is possible to efficiently combine the small areas based on a clear algorithm, and according to claim 5, the division result is based on only the minimum necessary dividing line. The number of shots can be suppressed and the drawing time can be shortened.

According to the sixth aspect of the present invention, even for any pattern, the minute pattern is surely avoided by the efficient division line setting and the small area joining process based on the clear algorithm. The division processing can be performed and the deterioration of drawing accuracy can be prevented. Further, in the division based on the division candidate line according to claim 7, the number of divisions can be minimized, which is suitable for shortening the drawing time, and in the division based on the division candidate line according to claim 8, the pattern is applied to the gate layer of the transistor. In this case, you can take a layout that avoids splitting on the active area,
Guarantees reliable operation of the transistor. Further, according to the ninth aspect, it is possible to obtain a division result based on only the minimum necessary division line, and it is possible to suppress an increase in the number of shots and shorten the drawing time.

According to the tenth aspect of the present invention, it is possible to surely perform the division processing while avoiding the minute pattern for any pattern, and prevent the deterioration of the drawing accuracy. In addition, claim 1
The division based on the division candidate line according to 1 can reduce the number of divisions as much as possible, which is suitable for shortening the drawing time. In the division based on the division candidate line according to claim 12, when the pattern is applied to the gate layer of the transistor, the active area is reduced. A layout that avoids the above division can be taken, and reliable operation of the transistor is guaranteed. Further, according to claim 13, small areas can be efficiently combined based on a clear algorithm, and according to claim 14, the division result is based only on the minimum necessary dividing line. The number of shots can be suppressed and the drawing time can be shortened.

According to the fifteenth and twentieth aspects of the present invention, it is possible to surely perform the division processing while avoiding the fine pattern for any pattern, prevent the deterioration of the pattern drawing accuracy on the mask substrate, and obtain the good quality. The mask of is obtained. In addition, in the division based on the division candidate lines according to claims 16 and 21, the number of divisions can be minimized, which is suitable for shortening the drawing time. In the division based on the division candidate lines according to the claims 17 and 22, the pattern is a gate layer of a transistor. When applied to, the layout avoiding division on the active area can be taken, and reliable operation of the transistor is guaranteed. In addition, claim 1
According to 8 and 23, it is possible to efficiently combine small regions based on a clear algorithm, and further,
According to No. 24, it is possible to obtain a division result based only on the necessary minimum division line, and it is possible to suppress an increase in the number of shots and shorten the drawing time and further the mask creation time.

According to the twenty-fifth and thirty-fifth aspects of the present invention, it is possible to surely perform the division processing while avoiding a minute pattern for any pattern, and prevent the reduction of the pattern drawing accuracy on the mask substrate. As a result, it is possible to improve the quality of the mask, the semiconductor substrate obtained using the mask, and the semiconductor device obtained from the semiconductor substrate. In addition, claim 2
The division based on the division candidate lines by 6, 36 can reduce the number of divisions as much as possible, which is suitable for shortening the drawing time.
In the division based on the division candidate lines 7 and 37, when the pattern is applied to the gate layer of the transistor, the layout avoiding the division on the active region can be taken, and the reliable operation of the transistor is guaranteed. In addition, claim 28,
According to 38, small regions can be efficiently combined based on a clear algorithm.
According to the above, it is possible to obtain a division result based only on the minimum necessary division line, and suppress the increase in the number of shots and draw time,
Further, the manufacturing time of the semiconductor device can be shortened.

According to Claims 30 and 40 of the present invention, division processing can be performed on any pattern while reliably avoiding a minute pattern, and it is possible to prevent deterioration of pattern drawing accuracy on a semiconductor substrate. It is possible to improve the quality of the semiconductor device obtained from the substrate. In addition, in the division based on the division candidate lines according to claims 31 and 41, the number of divisions can be minimized, which is suitable for shortening the drawing time. In the division based on the division candidate lines according to the claims 32 and 42, the pattern is the gate layer of the transistor. When applied to, the layout avoiding division on the active area can be taken, and reliable operation of the transistor is guaranteed. Further, according to claims 33 and 43, it is possible to efficiently combine small regions based on a clear algorithm, and according to claims 34 and 44,
It is possible to obtain the division result based on only the minimum necessary dividing line, and it is possible to suppress the increase in the number of shots and shorten the drawing time and further the manufacturing time of the semiconductor device.

According to the forty-fifth and forty-ninth aspects of the present invention, even for any pattern, a minute pattern can be surely formed by efficient division line setting and small area combining processing based on a clear algorithm. The avoidance of division processing can be performed and the reduction of drawing accuracy can be prevented. Further, in the division based on the division candidate lines according to claims 46 and 50, the number of divisions can be minimized, which is suitable for shortening the drawing time. In the division based on the division candidate lines according to the claims 47 and 51, the pattern is a gate layer of a transistor. When applied to, the layout avoiding division on the active area can be taken, and reliable operation of the transistor is guaranteed. Further, according to the forty-eighth and fifty-second aspects, it is possible to obtain the division result based on only the minimum necessary division line, and it is possible to suppress the increase in the number of shots and shorten the drawing time.

[Brief description of drawings]

FIG. 1 is a flowchart showing a flow of a drawing pattern division process according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a division processing device according to the same embodiment.

FIG. 3 is a diagram showing a state in which first and second division candidate lines are set in a division target pattern in the first embodiment of the present invention.

FIG. 4 is a diagram showing vertices that exceed an internal angle of 180 ° for the pattern to be divided in FIG.

FIG. 5 is a diagram showing region joining regarding a region having vertices having an interior angle exceeding 180 ° shown in FIG. 4;

FIG. 6 is a diagram showing region combination performed subsequent to FIG. 5;

FIG. 7 is a diagram showing region combination performed subsequent to FIG. 6;

FIG. 8 is a diagram showing a region combination performed after FIG. 7;

FIG. 9 is a diagram showing region combination performed after FIG. 8;

FIG. 10 is a diagram showing a final pattern division result according to the first embodiment.

FIG. 11 is a diagram showing a state in which first and second division candidate lines are set in a division target pattern in the second embodiment of the present invention.

12 is an internal angle 18 of the pattern to be divided in FIG.
It is a figure which shows the vertex which exceeds 0 degree.

FIG. 13 is a diagram showing a region combination regarding a region having vertices having an interior angle exceeding 180 ° shown in FIG. 12;

FIG. 14 is a diagram showing region combination performed after FIG. 13;

FIG. 15 is a diagram showing a final pattern division result according to the second embodiment.

FIG. 16 is a plan view showing an example in which the pattern divided in the first embodiment is applied to a gate layer.

FIG. 17 is a plan view showing an example in which the pattern divided in the second embodiment is applied to a gate layer.

FIG. 18 is a schematic perspective view of a variable shaping type electron beam drawing apparatus.

FIG. 19 is a diagram showing an example of division of minute pattern generation.

FIG. 20 is a diagram showing an example of division in which a minute pattern does not occur.

FIG. 21 is a diagram showing a conventional dividing line and a pattern in which a minute pattern cannot be eliminated by the dividing line.

[Explanation of symbols]

1 ... Drawing device, 2 ... Electron gun, 3 ... First aperture, 4 ... Molding deflector, 5 ... Second aperture, 6 ...
Objective lens, 7 ... Positioning deflector, 8 ... Semiconductor substrate, 9 ... Mask substrate, 11a ... First division candidate line setting means, 11b ... Second division candidate line setting means, 12 ...
... combining processing means, 21 ... pattern, L1a to L1d ...
... first division candidate line, L2a to L2h ... second division candidate line.

Continued front page    (54) [Title of Invention] Drawing pattern division processing method, drawing pattern division processing device, drawing method, mask, mask                     Creation method, semiconductor device, semiconductor device manufacturing method, drawing pattern division processing program, and                     Computer-readable recording medium recording program

Claims (52)

[Claims] 1. A method of dividing a drawing pattern, which divides a pattern to be drawn on a resist into units that can be drawn by a drawing apparatus, wherein a line segment passing through each vertex of the pattern is divided into first parts. Set as a candidate line, a line segment that does not pass through the vertex obtained based on the first division candidate line is set as a second division candidate line, and the line segment based on the first and second division candidate lines A method for dividing a drawing pattern, which is characterized by dividing a pattern. 2. A vertical bisector of a line segment formed by the first division candidate line and a side of the pattern connected to the first division candidate line on the same straight line is divided into the second division lines. The division processing method of the drawing pattern according to claim 1, wherein the division line is a candidate line. 3. A line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line is set as the second division candidate line. The method for dividing a drawing pattern according to claim 1, wherein: 4. The adjacent areas of the areas divided by the first and second division candidate lines are combined into a rectangular shape or a trapezoidal shape so as to eliminate a short side having a predetermined length or less, and the combination is performed. The division processing method of the drawing pattern according to claim 1, wherein a rectangle or a trapezoid obtained by the above is used as a unit of drawing by the drawing device. 5. The method for dividing a drawing pattern according to claim 4, wherein the combining is performed until the combination cannot be performed in a rectangular shape or a trapezoidal shape. 6. A drawing pattern division processing device for dividing a pattern to be drawn on a resist into units that can be drawn by a drawing device, wherein a line segment passing through each vertex of the pattern is divided into first parts. First dividing candidate line setting means for setting as a candidate line, and a second dividing candidate line for setting a line segment that does not pass through the apex obtained based on the first dividing candidate line as a second dividing candidate line Setting means; and combining processing means for combining adjacent areas of the areas divided by the first and second division candidate lines into a rectangular shape or a trapezoid so as to eliminate short sides having a predetermined length or less. A drawing pattern division processing device, wherein a rectangle or a trapezoid obtained by the combination is used as a unit of drawing by the drawing device. 7. The second segmentation candidate line setting means is a line segment formed by the first segmentation candidate line and a side of the pattern that is connected to the first segmentation candidate line on the same straight line. 7. The drawing pattern division processing apparatus according to claim 6, wherein a vertical bisector is set as the second division candidate line. 8. The line that intersects vertically and horizontally at the center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line, the second division candidate line setting means. 7. The drawing pattern division processing apparatus according to claim 6, wherein minutes are set as the second division candidate lines. 9. The drawing pattern division processing apparatus according to claim 6, wherein the combination processing means performs the combination until the combination cannot be a rectangle or a trapezoid. 10. A drawing method in which a pattern to be drawn on a resist is divided into units that can be drawn by a drawing device, and the pattern is drawn on the resist by the drawing device for each unit. In that case, a line segment that passes through each vertex of the pattern is set as a first division candidate line, and a line segment that does not pass through the apex obtained based on the first division candidate line is set as a second division candidate line. A drawing method comprising: setting and dividing the pattern based on the first and second division candidate lines. 11. A vertical bisector of a line segment formed by the first division candidate line and a side of the pattern connected to the first division candidate line on the same straight line is divided into the second division lines. The drawing method according to claim 10, wherein the drawing line is a candidate line. 12. A line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line is set as the second division candidate line. The drawing method according to claim 10, wherein: 13. The adjacent areas among the areas divided by the first and second division candidate lines are combined into a rectangular shape or a trapezoidal shape so as to eliminate a short side having a predetermined length or less, and the combination is performed. The drawing method according to claim 10, wherein a rectangle or a trapezoid obtained by the above is used as a drawing unit by the drawing device. 14. The drawing method according to claim 13, wherein the combining is performed until the combination cannot be a rectangle or a trapezoid. 15. A pattern divided into units that can be drawn by a drawing device is drawn by the drawing device on a resist formed on the mask substrate for each unit, and the drawn pattern is the mask substrate. In the mask formed by transferring the pattern to the pattern, the pattern in the division process includes a first division candidate line that is a line segment that passes through each vertex of the pattern, and the vertex obtained based on the first division candidate line. A mask that is divided based on a second division candidate line that is a line segment that does not pass through. 16. The second division candidate line is a vertical segment of a line segment formed by the first division candidate line and a side of the pattern that is connected to the first division candidate line on the same straight line. The mask according to claim 15, wherein the mask is an bisector. 17. The second division candidate line is a line segment that crosses vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line. The mask according to claim 15, wherein the mask is provided. 18. The adjacent areas of the areas divided by the first and second division candidate lines are combined into a rectangular shape or a trapezoidal shape so as to eliminate a short side having a predetermined length or less, and the combination is performed. 16. The mask according to claim 15, wherein a rectangle or a trapezoid obtained by the above is used as a unit for drawing by the drawing device. 19. The mask according to claim 18, wherein the coupling is performed until the rectangular or trapezoidal coupling cannot be performed. 20. A procedure of dividing a pattern into units that can be drawn by a drawing apparatus; a step of drawing the pattern for each unit on a resist formed on a mask substrate by the drawing apparatus; In the method for producing a mask, which comprises a procedure for transferring the pattern to the mask substrate, a line segment passing through each vertex of the pattern is set as a first division candidate line in the division processing, and the first division A line segment that does not pass through the apex obtained based on a candidate line is set as a second division candidate line, and the pattern is divided based on the first and second division candidate lines. How to make. 21. A vertical bisector of a line segment formed by the first division candidate line and a side of the pattern connected to the first division candidate line on the same straight line is divided into the second division lines. 21. The mask creating method according to claim 20, wherein the mask is a candidate line. 22. A line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line is set as the second division candidate line. 21. The method of making a mask according to claim 20, wherein. 23. The adjacent areas of the areas separated by the first and second division candidate lines are combined into a rectangular shape or a trapezoidal shape so as to eliminate a short side having a predetermined length or less, and the combination is performed. 21. The mask creating method according to claim 20, wherein a rectangle or a trapezoid obtained by the above is used as a unit of drawing by the drawing device. 24. The method of making a mask according to claim 23, wherein the combining is performed until the combination cannot be a rectangle or a trapezoid. 25. A pattern divided into units that can be drawn by a drawing device is drawn by the drawing device on a resist formed on the mask substrate for each unit, and the drawn pattern is the mask substrate. In a semiconductor device in which the pattern is exposed and transferred to a semiconductor substrate by using a mask formed by transferring the pattern to the semiconductor substrate, the pattern in the dividing process is a first division candidate line that is a line segment that passes through each vertex of the pattern. The semiconductor device is characterized by being divided based on a second division candidate line which is a line segment that does not pass through the apex obtained based on the first division candidate line. 26. The second divisional candidate line is a vertical segment of a line segment formed by the first divisional candidate line and a side of the pattern that is connected to the first divisional candidate line on the same straight line. 26. The semiconductor device according to claim 25, which is a bisector. 27. The second division candidate line is a line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line. 26. The semiconductor device according to claim 25, wherein: 28. The adjacent areas of the areas separated by the first and second division candidate lines are combined in a rectangular shape or a trapezoidal shape so as to eliminate a short side having a predetermined length or less, and the combination is performed. 26. The semiconductor device according to claim 25, wherein a rectangle or a trapezoid obtained by the above is used as a unit of drawing by the drawing device. 29. The semiconductor device according to claim 28, wherein the coupling is performed until the rectangular or trapezoidal coupling cannot be performed. 30. A pattern divided into units that can be drawn by a drawing device is drawn by the drawing device on a resist formed on the semiconductor substrate for each unit, and the drawn pattern is the semiconductor substrate. In the semiconductor device transferred to, the pattern in the division process includes a first division candidate line that is a line segment that passes through each vertex of the pattern, and the apex obtained based on the first division candidate line. A semiconductor device characterized by being divided based on a second division candidate line which is a line segment that does not pass through. 31. The second divisional candidate line is a vertical segment of a line segment formed by the first divisional candidate line and a side of the pattern connected on the same straight line to the first divisional candidate line. 31. The semiconductor device according to claim 30, wherein the semiconductor device is an equidistant line. 32. The second division candidate line is a line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line. The semiconductor device according to claim 30, wherein the semiconductor device is present. 33. Combining adjacent areas of the areas separated by the first and second division candidate lines into a rectangle or a trapezoid so as to eliminate short sides having a predetermined length or less, 31. The semiconductor device according to claim 30, wherein a rectangle or a trapezoid obtained by the above is used as a unit for drawing by the drawing device. 34. The semiconductor device according to claim 33, wherein the coupling is performed until the rectangular or trapezoidal coupling cannot be performed. 35. A procedure of dividing a pattern into units that can be drawn by a drawing apparatus, a step of drawing the patterns for each of the units on a resist formed on a mask substrate by the drawing apparatus, and In the method of manufacturing a semiconductor device, which comprises a step of transferring the formed pattern to the mask substrate to obtain a mask, and a step of exposing and transferring the pattern onto the semiconductor substrate using the mask, in the dividing process, A line segment that passes through each vertex is set as a first division candidate line, and a line segment that does not pass through the apex obtained based on the first division candidate line is set as a second division candidate line. And a method of manufacturing a semiconductor device, wherein the pattern is divided based on a second division candidate line. 36. A vertical bisector of a line segment formed by the first division candidate line and a side of the pattern connected to the first division candidate line on the same straight line is divided into the second division lines. 36. The method of manufacturing a semiconductor device according to claim 35, wherein the candidate line is used. 37. A line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line is set as the second division candidate line. 36. The method for manufacturing a semiconductor device according to claim 35, wherein 38. Combining adjacent areas among areas separated by the first and second division candidate lines into a rectangular shape or a trapezoid so as to eliminate short sides having a predetermined length or less, The method of manufacturing a semiconductor device according to claim 35, wherein a rectangle or a trapezoid obtained by the above is used as a unit of drawing by the drawing device. 39. The method of manufacturing a semiconductor device according to claim 38, wherein the coupling is performed until the rectangular or trapezoidal coupling cannot be performed. 40. A step of dividing a pattern into units that can be drawn by a drawing apparatus; a step of drawing the pattern for each unit on a resist formed on a semiconductor substrate by the drawing apparatus; A method of manufacturing a semiconductor device having a procedure of transferring a different pattern to the semiconductor substrate, in the dividing process, a line segment passing through each vertex of the pattern is set as a first dividing candidate line, and A semiconductor obtained by setting a line segment that does not pass through the apex obtained based on a division candidate line as a second division candidate line, and divides the pattern based on the first and second division candidate lines. Device manufacturing method. 41. A vertical bisector of a line segment formed by the first division candidate line and a side of the pattern connected to the first division candidate line on the same straight line is divided into the second division lines. The method of manufacturing a semiconductor device according to claim 40, wherein the candidate line is used. 42. A line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line is set as the second division candidate line. The method of manufacturing a semiconductor device according to claim 40, wherein: 43. Combining adjacent areas among areas separated by the first and second division candidate lines into a rectangle or a trapezoid so as to eliminate short sides having a predetermined length or less, The method of manufacturing a semiconductor device according to claim 40, wherein a rectangle or a trapezoid obtained by the above is used as a unit of drawing by the drawing device. 44. The method of manufacturing a semiconductor device according to claim 43, wherein the coupling is performed until the coupling cannot be performed in a rectangular shape or a trapezoidal shape. 45. A step of setting a line segment passing through each vertex of the pattern as a first division candidate line in order to divide a pattern to be drawn on a resist into units that can be drawn by a drawing device, A procedure of setting a line segment that does not pass through the apex obtained based on the first division candidate line as a second division candidate line, and adjoins the areas divided by the first and second division candidate lines. The regions are combined into a rectangle or a trapezoid so as to eliminate a short side having a predetermined length or less, and a procedure for using the rectangle or the trapezoid as a unit of drawing by the drawing device is executed. Split processing program. 46. A vertical bisector of a line segment formed by the first division candidate line and a side of the pattern connected to the first division candidate line on the same straight line is defined by the second division. 46. The drawing pattern division processing program according to claim 45, wherein the program is a candidate line. 47. A line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line is set as the second division candidate line. 46. The drawing pattern division processing program according to claim 45. 48. The drawing pattern division processing program according to claim 45, wherein the combination is performed until the combination into a rectangle or a trapezoid becomes impossible. 49. A step of setting a line segment passing through each vertex of the pattern as a first division candidate line in order to divide a pattern to be drawn on a resist into units that can be drawn by a drawing device, A procedure of setting a line segment that does not pass through the apex obtained based on the first division candidate line as a second division candidate line, and adjoins the areas divided by the first and second division candidate lines. The regions are combined into a rectangle or a trapezoid so as to eliminate a short side having a predetermined length or less, and a procedure for using the rectangle or the trapezoid as a unit of drawing by the drawing device is executed. A computer-readable recording medium recording a division processing program. 50. A vertical bisector of a line segment formed by the first division candidate line and a side of the pattern connected to the first division candidate line on the same straight line is divided into the second division lines. 50. A computer-readable recording medium storing the drawing pattern division processing program according to claim 49, wherein the recording medium is a candidate line. 51. A line segment that intersects vertically and horizontally at a center point of a region having a short side of a predetermined length or less among regions divided by the first division candidate line is set as the second division candidate line. 50. A computer-readable recording medium recording the drawing pattern division processing program according to claim 49. 52. The computer-readable recording medium recording the division processing program of the drawing pattern according to claim 49, wherein the combining is performed until the combination into a rectangle or a trapezoid becomes impossible.