JP2003059689A - Capacitor charging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent oscillation stop of a flyback DC/DC converter that detects the secondary current even when a slow speed microcomputer is used. SOLUTION: The capacitor charging device comprises a main capacitor, a flyback DC/DC converter, a secondary-current detecting means for detecting the secondary current of this converter, a switching element for controlling the ON-OFF of this converter, and a judgement means for judging whether or not this converter is charging. It comprises a first charging mode in which the switching element is made from 'OFF' to 'ON' when the secondary-current detecting means detects discharging of a secondary current and a second charging mode in which the switching element performs a fixed OFF-time drive, and thereby, when the judgement means judges with charge stop, it is oscillated by switching from the first charging mode to the second charging mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor charging device, and is mainly used in a camera electronic flash device.
The present invention relates to a C / DC converter.

[0002]

2. Description of the Related Art Conventionally, for example, in Japanese Unexamined Patent Publication No. 7-85988, a battery voltage and a main capacitor voltage are detected, and the primary winding is detected from the detection results of the battery voltage and the main capacitor voltage. A technique is disclosed in which a pulse width and a duty ratio of PWM for driving are obtained by inference, and the main capacitor is charged while switching stepwise or continuously.

Further, in Japanese Unexamined Patent Publication No. 2000-66274, the off time of a SW element that drives a current to the primary winding is defined as the period from the generation of the secondary current generated in the secondary winding to its disappearance. A technique for generating control signals so as to be substantially equal has been disclosed.

However, the above-mentioned conventional example, JP-A-7-85.
In the charging by the PWM drive set as disclosed in Japanese Patent Laid-Open No. 988 and Japanese Patent Laid-Open No. 2000-66274, the discharge time of the secondary current changes depending on the charging voltage of the main capacitor, as shown in FIG. Therefore, it is difficult to set the PWM off time so that the current crosses zero, and it is necessary to design so that a loss time occurs as shown in FIG. 8, and therefore the charging time is extended.

Therefore, a charging method (hereinafter, secondary current detection) control has been considered in which the secondary current is detected and the primary drive is performed for a predetermined time after the secondary current is completely discharged. By performing such control, high controllability can be obtained without loss of charging time.

FIG. 11 shows a timing chart of strobe charging by the secondary current detection. Since the circuit diagram is the same as that of the second embodiment of FIG. 9 and will be described later, the description thereof is omitted here.

The signals in the timing chart of FIG. 11 will be described. In the figure, the primary current represents the current flowing in the primary winding of the transformer (106), and the secondary current is the transformer (106).
Shows the current flowing in the secondary winding of the FET, FETGATE shows the gate input signal of the FET (107) on the circuit, and the secondary current IC input signal shows the resistor (121) and the resistor (12) on the circuit.
2) shows the secondary current detection signal connected to the control IC (105). The ON period of the timer end interrupt signal indicates the period from when the microcomputer (105a) accepts the timer end interrupt until the interrupt operation ends and the next interrupt operation is accepted. Similarly, the ON period of the secondary current detection interrupt signal indicates the period from the acceptance of the secondary current detection interrupt by the microcomputer (105a) to the acceptance of the next interrupt operation. Further, (A) in the figure shows the time when the charging voltage of the main capacitor (109) is high, and (B) in the figure shows the time when the charging voltage is low.

In this control, after the primary drive for a predetermined time measured by the timer, the microcomputer accepts a timer end interrupt process for ending the timer operation (see FIG. 11).
(A) (timing of timer end interrupt processing), FETGATE to low level (Fig. 11 (A) (F
ETGATE) timing). Next, when the discharge of the secondary current is completed, the secondary current IC input signal rises from the low level to the high level (FIG. 11A (timing of secondary current IC input signal)). Next, by detecting this rising edge, the next primary drive is performed. In order to detect this rising edge, there is a method of detecting the rising edge and the state detection in which software processing is repeatedly detected until a high level is reached, and a method of interrupting the microcomputer. As shown in FIG. 6, the secondary current emission time is about several μsec to several tens of μsec, and the strobe charging is desired to have a design without loss time as shown in FIG. Processing is advantageous.

[0009]

[Problems to be Solved by the Invention]
After the interrupt processing is accepted, the interrupt operation is finally completed, and a certain time t0 is required to enable input of the next interrupt input signal. In a mobile device such as a camera, generally, a high-speed microcomputer is not used, and in some cases t0 takes about several μsec. On the other hand, the secondary current emission time is shortened to about 1 μsec at the high charging voltage of (B) as shown in FIG. When the time until the secondary current is discharged is long (A), the secondary current IC input signal is inverted from low level to high level, a secondary current detection interrupt signal is generated, and the microcomputer accepts this. The following charging operation can be performed. However, when the time until the secondary current is discharged is short (B), the secondary current IC input signal is inverted from the low level to the high level, and the secondary current detection interrupt signal is generated (FIG. 11 (B). ) (Timing of secondary current detection interrupt signal), but the timer end interrupt operation is not completed (Fig. 11 (B)).
(Timer end interrupt signal timing), the secondary current detection interrupt signal cannot be accepted by the microcomputer. Therefore, the next charging operation cannot be performed and oscillation may stop.

In the DC / DC converter of the present invention, when the discharge of the secondary current is detected, the charge which performs the primary drive is switched to the charge by the fixed pulse drive when the discharge time of the secondary current is short, thereby reducing the cost. Even if a low-speed microcomputer is used, control is performed so that oscillation does not stop.

[0011]

DISCLOSURE OF THE INVENTION The present invention for solving the above problems includes a main capacitor and a battery as a power source, and a flyback DC / DC converter for boosting the battery voltage to charge the main capacitor. A switch element for controlling ON / OFF of a primary current of the DC / DC converter, a drive control means for controlling drive of the switch element, a secondary current detecting means for detecting a secondary current of the DC / DC converter, and the fly. In the capacitor charging device having a determination means for determining whether or not the buck type DC / DC converter is performing a charging operation, the drive control means may be:
There is a first charging mode in which the switching element is turned on from the off state when the secondary current detection means detects the discharge of the secondary current, and a second charging mode in which the switching element is driven by a fixed off time. Then, when the determination means determines that the charging is stopped during charging, the capacitor charging device is provided, which switches from the first charging mode to the second charging mode and oscillates.

By doing so, it is possible to prevent oscillation stop even if a low-speed microcomputer is used.

[0013]

(First Embodiment) FIG. 1 shows a flyback booster circuit according to a first embodiment of the present invention.

(101) is a battery as a power source,
(101a) is an internal resistance of the battery, and (124) is a capacitor connected in parallel with the battery. (105) is a control IC
Then, the camera sequence such as photometry of the camera, distance measurement, lens drive, film feeding, and the strobe flash device associated with the present invention are controlled. (105a) is a microcomputer for controlling I
It has a storage means RAM in C to control the camera sequence, and (105b) is an A / D converter (hereinafter A / D).
Then, the input voltage is digitized. (105c) is a timer for measuring the time for driving the primary current, which will be described later.
Reference numeral (106) is a transformer, which causes energy to be accumulated in the core by causing a current to flow in the loop of the battery positive electrode, the primary winding, and the battery negative electrode, and the counter electromotive force is generated by the energy. (10
7) is a FET, which drives the current of the primary winding of the transformer (106). Reference numeral (131) is a resistor that pulls down the gate of the FET (107).

Reference numeral (109) is a main capacitor for accumulating charges. Reference numeral (108) is a high-voltage rectifying diode, the cathode of which is connected to the beginning of the secondary winding of the transformer (106) and the anode of which is connected to the cathode of a diode (120) described later. (120) is a diode, the anode of which is connected to the cathode of the main capacitor (109) and the cathode of which is connected to the anode of the high-voltage rectifying diode (108), and which mainly applies the counter electromotive force generated from the secondary winding of the transformer (106). A current loop of the electric charge accumulated in the capacitor is formed by the configuration of the main capacitor (109), the diode (120) and the high voltage rectifying diode (108). Reference numeral (121) is a resistor, one side of which is connected to the cathode of the diode (120) and the other side of which is connected to the control IC (105). Reference numeral (122) is a resistance, and the input of the control IC (105) to which the resistance (121) is connected is pulled up to the auxiliary power supply Vcc boosted from the battery voltage by a DC / DC converter (not shown). Here, the resistance ratio of the resistance (121) and the resistance (122) is 1 to 50 for the resistance (121) and 10 to 50 for the resistance (122).
It is a degree. The diode (120) and the resistor (12
1) and the resistor (122) constitute the secondary current detection circuit described in the claims.

Reference numeral (125) is a diode, the anode of which is connected to the positive electrode of the battery. (126) is a resistor, and a series circuit of the resistor (126) and the diode (125) is connected between the positive electrode of the main capacitor (109) and the positive electrode of the battery (101). This diode (125) and resistor (12
According to 6), by making the voltage of the main capacitor the battery voltage, it is possible to prevent the detection malfunction of the secondary current near 0V from occurring. (110) is a trigger circuit, (111) is a discharge tube, receives a trigger voltage from the trigger circuit (110),
It emits light by the electric charge accumulated in the main capacitor (109). (130) is an inverter which inverts the gate signal of the FET (107). (132) is an AND circuit to which the gate inversion signal of the FET (107) and the output of the secondary current detection circuit are input. The inverter (130) and the AND circuit (132) constitute a judgment means for judging whether or not the oscillation described in the claims is stopped.

Reference numeral (102) is a shutter driving means for driving the shutter, and reference numeral (103) is a constant voltage circuit for supplying a control power source as a power source to each circuit block. (11
2) is a charging voltage detecting means, which is A / in the control IC (105).
The voltage connected to D (105b) and stored in the main capacitor (109) is detected. (113) is a photometric means for detecting the subject brightness. (114) is a distance measuring means for detecting the distance to the subject. Reference numeral (115) is a lens driving means, which drives the photographing lens based on the detection result from the distance measuring means (114) to focus the subject on the film surface, and (116) is a film feeding means for automatically measuring the film. Loading, hoisting and rewinding. (117)
Sets the camera to READY for shooting (11
8) is SW1, which activates an electric circuit in the camera by the first stroke of the shutter button to perform photometry and detection of distance measurement. (119) is SW2, which is a second stroke of the shutter button and serves as a start signal of the photographing sequence after SW1.

The operation of the camera including the booster circuit of the first embodiment having the configuration of the booster circuit of FIG. 1 will be described below with reference to the flow charts of FIGS. 2, 4 and 5.

First, referring to FIG. 2, MAINSW (117),
The sequence at the time of turning on will be described.

In step (S401), MAINSW (1
It is detected whether or not 17) is turned on. MAIN here
When it is detected that the SW (117) is turned on, the step (S40
2) A battery check (hereinafter BC) is performed to detect whether or not the battery voltage of the camera is operable, and the result is stored in the RAM in the microcomputer (105a).

Next, in step (S403), step (S
402), it is judged from the BC result stored in the RAM whether or not the voltage is an operable voltage of the camera, and if it is an operable voltage, the step (S404) determines that the voltage is inoperable. If there is, go to step (S401).
Next, in step (S404), photometry is performed by the photometry means (113) for subject brightness detection, and the photometry result is stored in the RAM in the microcomputer (105a). Next step (S40
5) In step (S404), the microcomputer (105a)
It is determined from the subject brightness information whether or not the photometric detection result of the internal RAM is a photometric result that requires stroboscopic light emission at the time of shooting. Here, if the strobe precharge is not necessary at a brightness that does not require strobe emission, MAINS
The W-on sequence ends. If the strobe preliminary charge is required at the brightness required for the strobe in step (S405), the process proceeds to the rush mode in step (S406) to perform the strobe charge.

Here, the flash mode of step (S406) is performed by the flow chart shown in FIG. 5, which will be described later in detail. First, in the step (S201), the detection of the charging voltage of the main capacitor is performed by the voltage in the control voltage detecting circuit (112) in the control IC (105).
/ D (105b), and the detection result is detected by the microcomputer (10
5a) Store in internal RAM. Next step (S202)
In step (S201), it is determined whether or not to charge the battery, based on the detection result obtained in step (S201). Here, if the result of the A / D of the RAM in the microcomputer (105a) is the charge completion voltage, the process proceeds to step (S208), the charge OK flag is set, and the charge sequence is ended. Step (S
If the result of A / D in the RAM in the microcomputer (105a) is not charging completed in 202), the process proceeds to step (S203) to start the charging time timer and start strobe charging in the first charging mode described later (S204). To do.

Now, the circuit operation of the booster circuit will be described with reference to the timing chart of FIG.

First, the signals in the timing chart of FIG. 3 will be described. The primary current in the figure indicates the current flowing through the primary winding of the transformer (106). The secondary current is the transformer (10
The current flowing in the secondary winding of 6) is shown. FETGATE indicates the gate input signal of the FET (107) on the circuit. The secondary current IC input signal indicates the secondary current detection signal in which the resistor (121) and the resistor (122) on the circuit are connected and also connected to the control IC (105). In addition, FIG.
Represents the operation in the first charge mode described in the claim for detecting the secondary current, and (B) represents each signal in the second charge mode described in the claim for driving with a fixed pulse. .
However, since the secondary current is not detected in (B), the secondary current detection signal is omitted.

Next, the circuit operation in FIG. 3 will be described.

First, the secondary current detection mode will be described with reference to FIG. A predetermined oscillation signal (Fig. 3) is sent from the control IC (105) to the gate of the FET (107) via the connection terminal.
(A) (timing of (FETGATE)) is given. At this time, the timer (105c) is simultaneously set. Therefore, a high-level signal is applied to the control electrode of the FET (107) so that the battery positive electrode and the transformer (10
6) Primary winding, FET (107) drain = source,
Resistance (130), current in loop of battery negative electrode (Fig. 3 (A)
(Primary current)) flows. Therefore, the transformer (106)
An induced electromotive force is generated in the secondary winding of the transformer, but since the polarity of this current is blocked by the high-voltage rectifying diode (108), the excitation current does not flow from the transformer (106) and the energy is reduced by the transformer (106). ) Is accumulated in the inner core. This energy storage (current drive) is performed for a predetermined time (see FIG. 3) preset by the timer (105c).
(A) (timing of (FETGATE)).

Here, when the predetermined time set by the timer (105c) has elapsed, the timer operation ends and a timer end interrupt signal is generated, and the microcomputer (105a)
Accepts the timer end interrupt processing (Fig. 3 (A))
(Timing of timer end interrupt processing), FE
With the gate of T (107) at low level, FET (10
7) is turned off (timing of FIG. 3 (A) (FETGATE)) to interrupt the current and make it non-conductive.

By turning off the FET (107), a counter electromotive force is generated in the secondary winding of the transformer (106). This back electromotive force is a secondary current (Fig. 3 (A) (secondary current)
Timing), the main capacitor (109), the diode (120), and the high-voltage rectifier diode (108) flow in a loop from the transformer (106).
The electric charge is accumulated in 09). Then, the secondary current IC input signal has a resistance (122) and a resistance (121) from Vcc.
Due to the shunt current of the secondary current passing through, a low level (timing of FIG. 3A (secondary current IC input signal)) is reached at the same time when the secondary current starts to be discharged.

Next, when the energy accumulated in the transformer (106) is released and the secondary current is shunted to maintain the low level, the secondary current IC input signal is released from the secondary current. At the timing of (FIG. 3 (A) (secondary current)), the low level is inverted to the high level (FIG. 3).
(A) (Timing of secondary current IC input signal).

In response to the secondary current IC input signal being inverted from low level to high level, a secondary current detection interrupt signal is generated, and the microcomputer (105a) accepts this secondary current detection interrupt signal (see FIG. 3 (A) (timing of secondary current detection interrupt signal), control IC (10
5) again generates a high level signal at the gate of the FET (107).

Similar to the above-mentioned primary drive, the FET (1
07) conductive (timing of Fig. 3 (FETGATE))
Then, energy is stored in the transformer (106) for a predetermined time. When a predetermined time has passed, the low level signal causes the FET (107) to be non-conducting and the transformer (106).
The stored energy is released from the main capacitor (1
09). By repeating the above operation, the voltage of the main capacitor (109) rises.

Next, the second charging mode using a fixed pulse will be described.

Since the above-mentioned primary drive is equivalent to the first charge mode of FIG. 3A, detailed description thereof will be omitted.
Conduct T (107) (Fig. 3 (B) (FETGATE)
Energy is stored in the transformer (106) for a predetermined time. And after a predetermined time has passed,
The FET (107) is turned off by the low level signal (see FIG. 3).
(B) (timing of (FETGATE)). F
By turning off the ET (107), the transformer (106)
A counter electromotive force is generated in the secondary winding of the transformer (106)
The stored energy is released from the main capacitor (1
09). Then, after the fixed off time Toff has elapsed again, the control IC (105) again generates a high level signal at the gate of the FET (107) (FIG. 3B (FETG
ATE) timing).

As in the case of the primary drive described above, the FET (1
07) conductive (timing of Fig. 3 (FETGATE))
Then, energy is stored in the transformer (106) for a predetermined time. When a predetermined time has passed, the low level signal causes the FET (107) to be non-conducting and the transformer (106).
The stored energy is released from the main capacitor (1
09). By repeating the above operation, the voltage of the main capacitor (109) rises.

Further, if the control is performed by the fixed pulse, since the microcomputer generally has a timer by hardware, erroneous detection due to the interrupt processing as described in the conventional example does not occur.

When the charging operation is started in (S204), charging is performed in the first charging mode for detecting the secondary current. At this time, if the charging voltage rises, as shown in FIG.
The emission time of the secondary current is shortened. Finally, 1 μsec
The secondary current detection interrupt signal is generated before the timer end interrupt processing is completed, but the microcomputer cannot accept the secondary current detection interrupt signal. Therefore, the next charging operation cannot be performed and the oscillation stops.

The operation of the determination circuit for determining whether or not charging is being performed will be described with reference to the timing chart of FIG. 12 and the flowchart of FIG.

A method of determining this oscillation will be described with reference to the timing chart of FIG. The signals of the timing chart of FIG. 12 will be described. The inverted signal of FETGATE indicates the output of the in-circuit inverter (130) of FIG.
The secondary current detection IC input signal indicates the secondary current detection signal in which the resistor (121) and the resistor (122) on the circuit are connected and also connected to the control IC (105). b is the control IC
An AND circuit (132) input to the terminal b of (105)
The output signal of is shown.

As described above in the first charging mode, the FE
When the gate of T (107) is at high level, the secondary current does not flow because the primary current is flowing through the oscillating transformer (106), and therefore the secondary current detection IC input signal is at high level. On the contrary, while the secondary current is flowing, the input signal of the secondary current detection IC is low level and the FET (10
The gate of 7) is low level. Therefore, the output of the AND circuit (132) is always at low level during oscillation. When the oscillation is stopped, both the inverted signal of the gate of the FET (107) and the input signal of the secondary current detection IC become high level, and the output of the AND circuit (132) becomes high level.

According to this determination method, the control circuit (10
5) shows the output state of the AND circuit (132) as D
Predetermined time d1 longer than the oscillation cycle of the C / DC converter
Repeated in units of (for example, about 1 msec), DC /
When it is detected that the output of the AND circuit (132), which is a state that appears while the DC converter oscillation is stopped, is high, it is determined that the oscillation of the booster circuit is stopped.

Next, description will be made with reference to the flowchart of FIG. When the control circuit (105) detects the oscillation of the DC / DC converter, this step ends. (S5
01). Further, when the control circuit (105) does not detect the oscillation of the booster circuit, the oscillation in the first charging mode for detecting the secondary current is stopped, so that the fixed pulse described above is output from the first charging mode. The control is switched to the second charging mode which is the control by oscillating again and the oscillation is performed again (S502), and the determination means operation is prohibited in the subsequent charging operation (S503).

As shown in FIG. 6, the secondary current discharge time approaches a constant value in the latter half of charging even when the off time is fixed, so that the time lag shown in FIG. 8 is almost eliminated.

As described above, the state of charge is determined during charging, and when oscillation is stopped, control by secondary current detection is switched to control by fixed pulse.

By performing such control, it becomes possible to perform strobe charging without stopping oscillation even when a slow microcomputer is used.

Returning again to the flow chart of FIG. 5, if strobe charging is started (S204) and then step (S205) is reached, A in the control IC (105)
/ D (105b) detects the charging voltage by the voltage through the charging voltage detection circuit (112), and stores the detection result in the RAM in the CPU (105). Next, in step (S206), it is determined whether or not the charging voltage detected in step (S205) is a voltage for completion of charging, and if completion of charging is not detected in step (S206), step ( Proceed to S210 and proceed to step (S20).
It is determined whether the charging timer started in 3) has passed a predetermined time. If the charging timer has passed the predetermined time, the process proceeds to step (S211) to stop the charging operation started in step (S204). , Step (S212)
Then, the flag of charging NG is set and the charging sequence is ended.

If the charging timer has not elapsed for the predetermined time, the process returns to step (S204), the charging voltage is detected in step (S205), and then step (S2).
06), the step (S210) is repeated,
When the charge completion voltage is detected by the detection of the charge completion in step (S206), the process proceeds to step (S207) to stop the charge, the charge OK flag is set in step (S208), the charge sequence is terminated, and MAI
End the sequence when NSW is on.

Next, the release sequence will be described with reference to FIG.

In step (S101), the control IC (10
5) Initialize the internal microcomputer (105a). Next, in step (S102), it is detected whether SW1 (118) which is the first stroke of the release SW has been turned on.
Next, when SW1 (118) is detected in step (S103), step (S402) is followed by step (S402).
In the same way as the above, a battery check (hereinafter referred to as “B”) for detecting whether or not the camera battery voltage can operate the camera.
C) is performed, and the detection result of A / D of the battery voltage is stored in the RAM in the microcomputer (105a). Next, in step (S105), in step (S104), it is determined from the BC result stored in the RAM whether or not the voltage is an operable voltage of the camera, and if it is an operable voltage, the step (S106). If the voltage is inoperable, the process proceeds to step (S102).

Next, in step (S106), the distance measuring means (114) detects the distance to the object and stores the distance measuring result in the RAM in the microcomputer (105a). Next, in step (S107), the brightness of the subject is detected by the photometric means (11
3) Performed by R in the microcomputer (105a) similarly to distance measurement
The photometric result is stored in the AM (105a). Next, in step (S108), it is determined whether or not strobe charging is necessary based on the photometric data detected in step (S107) and stored in the RAM in the microcomputer (105a).
When it is necessary to emit the flash light, the shooting situation is dark or there is backlight. If strobe light emission is required here, the process proceeds to step (S109), and if not, the process proceeds to (S111) to enter a standby state for turning on the SW2 (119). If strobe charging is required at step (S108) and the flash mode at step (S109) is entered, the above-described charging sequence of the flowchart of FIG. 5 is performed. Since the charging sequence is as described above, it is omitted here.

Next, when the charging sequence is completed in the flash mode of step (S109), step (S11)
It is determined whether the charging of 0) is completed. This determination is the result of the flag indicating whether the charging is OK in the charging sequence of step (S109). If the charging is completed with OK, SW2 (11) of step (S111)
It will be in the standby state of 9) ON. If charging is not completed with NG, SW1 (11) in step (102)
Return to detection of 8).

Next, when it is detected that the SW2 (119) is turned on from the standby state of the SW2 in the step (S111), the process proceeds to the step (S112) and is stored in the RAM in the microcomputer (105a) for the distance measurement performed in the step (S106). The lens drive means (115) controls the drive of the photographing lens according to the measured distance data. Next, step (S11
If the flash light emission is required according to the photometric data stored in the RAM in the microcomputer (105a) for photometry performed in step (S107), the control IC (10
The trigger circuit (110) outputs a light emission signal from the trigger signal from 5) to perform strobe light emission, and at the same time, shutter drive control by the shutter drive means (102) is performed.

Next, in step (S114), lens reset is performed to return the lens at the focal position to the initial lens position. Next, in step (S115), the film driving means (1
By 16), the film feed control to the next frame is performed,
Next, in step (S116), it is determined whether or not strobe preliminary charging is performed. If the flash preliminary charging is not performed here, the result determined in step (S108) based on the photometric result obtained in step (S117) is that the flash emission shooting mode is not the flash emission shooting mode. When the flash preliminary charging is performed, the result determined in step (S108) based on the photometric result obtained in step (S107) is the flash emission photographing mode. Here, step (S116)
If the result is that the flash preliminary charge is not performed, the process returns to the detection of SW1 (119) in step (S102). If the result of step (S116) indicates that the flash preliminary charge is performed, the process proceeds to step (S117). Step (S1
The strobe charging of 17) is the same sequence as the sequence step (S406) after turning on the MAINSW described above, and thus the description thereof will be omitted. After that, the step (S11
When the charging in 7) is completed, a series of camera sequences is completed, and the process returns to the detection of SW1 (119) in step (S102).

(Second Embodiment) The second embodiment shows a modification of the first embodiment, in which the first charging mode by the secondary current detection is changed to the second charging mode by the fixed off time. Is switched when the voltage of the main capacitor 27 is equal to or higher than the predetermined voltage V1. The voltage of the main capacitor 27 and the secondary current discharge time have a relationship as shown in FIG. 6, and the voltage of the main capacitor at which the inversion of the secondary current IC input signal from the low level to the high level cannot be detected can be determined.

The circuit operation is omitted since it is similar to that of the first embodiment. A flow chart of strobe charging in the second embodiment is shown in FIG. 10 and a circuit configuration is shown in FIG.

The circuit configuration of FIG. 9 differs from that of the first embodiment in that there is no inverter (130) and AND circuit (132), and accordingly, the output terminal and control of the AND circuit (132) are controlled. The description is omitted because the circuit 105 is simply disconnected.

The strobe charging operation of the second embodiment will be described with reference to the flowchart of FIG.

First, in step (S301), the detection of the charging voltage of the main capacitor is performed by the voltage charging voltage detection circuit (1
12) A / D in the control IC (105) by the voltage via
(105b), and the detection result is detected by the microcomputer (105
a) Store in internal RAM. Next, in step (S302), based on the detection result performed in step (S301),
It is determined whether to charge the battery. Here, the microcomputer (10
5a) If the result of the A / D of the internal RAM is the charge completion voltage, the process proceeds to step (S314) to set the charge OK flag and end the charge sequence. Step (S30
If the result of A / D of the RAM in the microcomputer (105a) is not charging completed in 2), the process proceeds to step (S303), and if the result of the A / D of the RAM in the microcomputer (105a) is the predetermined voltage V1 or more. , Proceeds to step (S309), starts the charging timer, and proceeds to step (S310)
And proceeds to the second charging mode of FIG. 3 (B) described in the first embodiment. In step (S303), the result of A / D of the RAM in the microcomputer (105a) is the predetermined voltage V1.
If not, proceed to step (S304) to start the charging timer.

Next, the charging for detecting the secondary current described in FIG. 3A is started (S305), and step (S306).
The control IC detects the charging voltage of the main capacitor (109) by the voltage through the voltage charging voltage detection circuit (112).
The detection is performed by the A / D (105b) in (105) and the detection result is stored in the RAM in the microcomputer (105a). Next, in step (S307), based on the detection result obtained in step (S306), if the charging voltage is equal to or lower than the predetermined voltage V1,
It proceeds to step (S308). Next, step (S30
It is determined whether the charging timer started in 4) has passed a predetermined time. If the charging timer has passed the predetermined time, the process proceeds to step (S316) to stop the charging operation started in step (S305). , Step (S315)
Then, the flag of charging NG is set and the charging sequence is ended. If the charging timer has not elapsed the predetermined time, the process returns to step (S306) and step (S30).
While performing the secondary current detection driving started in 5), the steps of step (S306) and step (S308) are repeated, and in step (S307), the main capacitor (10
When it is detected that the charging voltage in 9) is equal to or higher than the predetermined voltage V1, the process proceeds to step (S310), and the fixed off-time driving described in FIG. 3B is started.

In the following, the flow chart of strobe charging will be omitted because the step numbers only differ.

Although the FET (107) is used as the switch element in the first and second embodiments,
The invention is not limited to this, and a bipolar transistor may be used.

[0061]

As described above, the main capacitor and the battery serving as the power source, the flyback DC / DC converter for boosting the battery voltage to charge the main capacitor, and the DC / DC converter A switch element for controlling on / off of a primary current, a drive control means for controlling drive of the switch element, a secondary current detecting means for detecting a secondary current of the DC / DC converter, and the flyback DC / DC converter are provided. In a capacitor charging device having a determination means for determining whether or not a charging operation is performed, the drive control means turns the switch element from off to on when the secondary current detection means detects the discharge of the secondary current. A first charging mode to be performed and a second charging mode to drive the switch element for a fixed off time; If it is determined that charging is stopped during charging, switching from the first charging mode to the second charging mode to cause oscillation causes emission of secondary current that reduces loss time of charging time. It is possible to prevent oscillation stop even in the case of using a low-speed microcomputer in the charging for detecting and performing the primary drive.

[Brief description of drawings]

FIG. 1 is a circuit and block diagram of a first embodiment of a camera of the present invention.

FIG. 2 is a flowchart 1 of a camera operation according to the first and second embodiments.

FIG. 3 is a timing chart of the booster circuits according to the first and second embodiments.

FIG. 4 is a flowchart 2 of the camera operation according to the first and second embodiments.

FIG. 5 is a flowchart of strobe charging according to the first embodiment.

FIG. 6 Secondary current emission time characteristics of flyback converter

FIG. 7 is a flowchart of charging mode switching according to the first embodiment.

FIG. 8 is a timing chart of a conventional flyback converter.

FIG. 9 is a circuit and block diagram of a second embodiment of a camera of the present invention.

FIG. 10 is a flowchart of strobe charging according to the second embodiment.

FIG. 11 is a timing chart of a conventional flyback converter.

FIG. 12 is a diagram for explaining the first embodiment.

[Explanation of symbols]

101 batteries 105 Control IC 106 transformer 107 FET 108 High voltage rectifier diode 109 Main capacitor 110 trigger circuit 111 discharge tube 112 Charge voltage detection circuit 120 diodes 130 inverter 132 AND circuit

Claims (7)

[Claims] 1. A battery serving as a main capacitor and a power source, a flyback DC / DC converter for boosting the battery voltage to charge the main capacitor, and the DC / DC converter.
A switch element for controlling ON / OFF of the primary current of the DC converter, a drive control means for controlling the drive of the switch element, a secondary current detecting means for detecting a secondary current of the DC / DC converter, and the flyback DC / In a capacitor charging device having a determination means for determining whether or not a DC converter is performing a charging operation, the drive control means is turned off to the switch element when the secondary current detection means detects the discharge of the secondary current. From the first charging mode to turn on from and a second charging mode to drive the switch element with a fixed off time, if it is determined by the determination means that charging is stopped during charging, A capacitor charging device characterized by switching from a first charging mode to the second charging mode for oscillation. 2. The determination means according to claim 1, wherein the DC /
The operation state of the DC / DC converter is detected at a timing of a predetermined time longer than the oscillation cycle of the DC converter,
A capacitor charging device, characterized in that when the state appearing while oscillation is stopped is detected, the oscillation of the booster circuit is stopped. 3. A battery serving as a main capacitor and a power source, a flyback DC / DC converter for boosting the battery voltage to charge the main capacitor, and the DC / DC converter.
A switch element for controlling ON / OFF of the primary current of the DC converter, a drive control means for controlling the drive of the switch element, a secondary current detecting means for detecting a secondary current of the DC / DC converter, and a voltage of the main capacitor are provided. In the capacitor charging device having a voltage detection unit for detecting, the drive control unit includes a first charging mode in which the switching element is turned on from off when the secondary current detection unit detects emission of a secondary current, and The switch element has a second charging mode in which the driving is performed with a fixed off time, and when the voltage of the voltage detecting means is a predetermined voltage or more, the first charging mode is switched to the second charging mode to oscillate. A capacitor charging device characterized in that 4. The detector of the secondary current detector according to claim 1 is a diode, and the cathode of the diode and the anode of the high-voltage rectifier diode are connected to each other, and the anode of the diode is A capacitor charging device characterized in that it is connected to a negative electrode of a main capacitor and the high-voltage rectifying diode is composed of a circuit connected to the transformer. 5. The capacitor charging device according to claim 1, wherein the ON control of the SW element is performed by pulse control. 6. The switch element according to claim 1 or 3,
A capacitor charging device characterized by being a FET. 7. The switch element according to claim 1 or 3,
A capacitor charging device characterized by being a bipolar transistor.